fpu_emu.c revision 1.30
1 /* $NetBSD: fpu_emu.c,v 1.30 2020/07/15 09:16:35 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.30 2020/07/15 09:16:35 rin Exp $"); 80 81 #ifdef _KERNEL_OPT 82 #include "opt_ddb.h" 83 #endif 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/evcnt.h> 88 #include <sys/proc.h> 89 #include <sys/siginfo.h> 90 #include <sys/signal.h> 91 #include <sys/signalvar.h> 92 #include <sys/syslog.h> 93 94 #include <powerpc/instr.h> 95 #include <powerpc/psl.h> 96 97 #include <machine/fpu.h> 98 #include <machine/reg.h> 99 #include <machine/trap.h> 100 101 #include <powerpc/fpu/fpu_emu.h> 102 #include <powerpc/fpu/fpu_extern.h> 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static struct evcnt fpu_emu_ev_##name = \ 106 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 107 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 108 109 #define FPU_EMU_EVCNT_INCR(name) \ 110 fpu_emu_ev_##name.ev_count++ 111 112 FPU_EMU_EVCNT_DECL(stfiwx); 113 FPU_EMU_EVCNT_DECL(fpstore); 114 FPU_EMU_EVCNT_DECL(fpload); 115 FPU_EMU_EVCNT_DECL(fcmpu); 116 FPU_EMU_EVCNT_DECL(frsp); 117 FPU_EMU_EVCNT_DECL(fctiw); 118 FPU_EMU_EVCNT_DECL(fcmpo); 119 FPU_EMU_EVCNT_DECL(mtfsb1); 120 FPU_EMU_EVCNT_DECL(fnegabs); 121 FPU_EMU_EVCNT_DECL(mcrfs); 122 FPU_EMU_EVCNT_DECL(mtfsb0); 123 FPU_EMU_EVCNT_DECL(fmr); 124 FPU_EMU_EVCNT_DECL(mtfsfi); 125 FPU_EMU_EVCNT_DECL(fnabs); 126 FPU_EMU_EVCNT_DECL(fabs); 127 FPU_EMU_EVCNT_DECL(mffs); 128 FPU_EMU_EVCNT_DECL(mtfsf); 129 FPU_EMU_EVCNT_DECL(fctid); 130 FPU_EMU_EVCNT_DECL(fcfid); 131 FPU_EMU_EVCNT_DECL(fdiv); 132 FPU_EMU_EVCNT_DECL(fsub); 133 FPU_EMU_EVCNT_DECL(fadd); 134 FPU_EMU_EVCNT_DECL(fsqrt); 135 FPU_EMU_EVCNT_DECL(fsel); 136 FPU_EMU_EVCNT_DECL(fpres); 137 FPU_EMU_EVCNT_DECL(fmul); 138 FPU_EMU_EVCNT_DECL(frsqrte); 139 FPU_EMU_EVCNT_DECL(fmulsub); 140 FPU_EMU_EVCNT_DECL(fmuladd); 141 FPU_EMU_EVCNT_DECL(fnmsub); 142 FPU_EMU_EVCNT_DECL(fnmadd); 143 144 /* FPSR exception masks */ 145 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 146 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 147 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 148 FPSCR_VXSQRT|FPSCR_VXCVI) 149 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 150 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 151 152 153 int fpe_debug = 0; 154 155 #ifdef DDB 156 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 157 #endif 158 159 #ifdef DEBUG 160 /* 161 * Dump a `fpn' structure. 162 */ 163 void 164 fpu_dumpfpn(struct fpn *fp) 165 { 166 static const char *class[] = { 167 "SNAN", "QNAN", "ZERO", "NUM", "INF" 168 }; 169 170 KASSERT(fp != NULL); 171 172 printf("%s %c.%x %x %x %xE%d\n", class[fp->fp_class + 2], 173 fp->fp_sign ? '-' : ' ', 174 fp->fp_mant[0], fp->fp_mant[1], 175 fp->fp_mant[2], fp->fp_mant[3], 176 fp->fp_exp); 177 } 178 #endif 179 180 /* 181 * fpu_execute returns the following error numbers (0 = no error): 182 */ 183 #define FPE 1 /* take a floating point exception */ 184 #define NOTFPU 2 /* not an FPU instruction */ 185 #define FAULT 3 186 187 188 /* 189 * Emulate a floating-point instruction. 190 * Return zero for success, else signal number. 191 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 192 */ 193 bool 194 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 195 { 196 struct pcb *pcb; 197 union instr insn; 198 struct fpemu fe; 199 200 KSI_INIT_TRAP(ksi); 201 ksi->ksi_signo = 0; 202 ksi->ksi_addr = (void *)tf->tf_srr0; 203 204 /* initialize insn.is_datasize to tell it is *not* initialized */ 205 fe.fe_fpstate = fpf; 206 fe.fe_cx = 0; 207 208 /* always set this (to avoid a warning) */ 209 210 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 211 #ifdef DEBUG 212 printf("fpu_emulate: fault reading opcode\n"); 213 #endif 214 ksi->ksi_signo = SIGSEGV; 215 ksi->ksi_trap = EXC_ISI; 216 ksi->ksi_code = SEGV_MAPERR; 217 return true; 218 } 219 220 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 221 insn.i_int, (void *)tf->tf_srr0)); 222 223 if ((insn.i_any.i_opcd == OPC_TWI) || 224 ((insn.i_any.i_opcd == OPC_integer_31) && 225 (insn.i_x.i_xo == OPC31_TW))) { 226 /* Check for the two trap insns. */ 227 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 228 ksi->ksi_signo = SIGTRAP; 229 ksi->ksi_trap = EXC_PGM; 230 ksi->ksi_code = TRAP_BRKPT; 231 return true; 232 } 233 switch (fpu_execute(tf, &fe, &insn)) { 234 case 0: 235 success: 236 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 237 tf->tf_srr0 += 4; 238 return true; 239 240 case FPE: 241 pcb = lwp_getpcb(curlwp); 242 if ((pcb->pcb_flags & PSL_FE_PREC) == 0) 243 goto success; 244 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 245 ksi->ksi_signo = SIGFPE; 246 ksi->ksi_trap = EXC_PGM; 247 return true; 248 249 case FAULT: 250 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 251 ksi->ksi_signo = SIGSEGV; 252 ksi->ksi_trap = EXC_DSI; 253 ksi->ksi_code = SEGV_MAPERR; 254 ksi->ksi_addr = (void *)fe.fe_addr; 255 return true; 256 257 case NOTFPU: 258 default: 259 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 260 #if defined(DDB) && defined(DEBUG) 261 if (fpe_debug & FPE_EX) { 262 printf("fpu_emulate: illegal insn %x at %p:", 263 insn.i_int, (void *) (tf->tf_srr0)); 264 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 265 } 266 #endif 267 return false; 268 } 269 } 270 271 /* 272 * Execute an FPU instruction (one that runs entirely in the FPU; not 273 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 274 * modified to reflect the setting the hardware would have left. 275 * 276 * Note that we do not catch all illegal opcodes, so you can, for instance, 277 * multiply two integers this way. 278 */ 279 int 280 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 281 { 282 struct fpn *fp; 283 union instr instr = *insn; 284 int *a; 285 vaddr_t addr; 286 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 287 unsigned int cond; 288 struct fpreg *fs; 289 290 /* Setup work. */ 291 fp = NULL; 292 fs = fe->fe_fpstate; 293 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 294 295 /* 296 * On PowerPC all floating point values are stored in registers 297 * as doubles, even when used for single precision operations. 298 */ 299 type = FTYPE_DBL; 300 cond = instr.i_any.i_rc; 301 setcr = 0; 302 bf = 0; /* XXX gcc */ 303 304 #if defined(DDB) && defined(DEBUG) 305 if (fpe_debug & FPE_EX) { 306 vaddr_t loc = tf->tf_srr0; 307 308 printf("Trying to emulate: %p ", (void *)loc); 309 opc_disasm(loc, instr.i_int); 310 } 311 #endif 312 313 /* 314 * `Decode' and execute instruction. 315 */ 316 317 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 318 instr.i_any.i_opcd == OPC_integer_31) { 319 /* 320 * Handle load/store insns: 321 * 322 * Convert to/from single if needed, calculate addr, 323 * and update index reg if needed. 324 */ 325 uint64_t buf; 326 size_t size = sizeof(float); 327 int store, update; 328 329 cond = 0; /* ld/st never set condition codes */ 330 331 332 if (instr.i_any.i_opcd == OPC_integer_31) { 333 if (instr.i_x.i_xo == OPC31_STFIWX) { 334 FPU_EMU_EVCNT_INCR(stfiwx); 335 336 /* Store as integer */ 337 ra = instr.i_x.i_ra; 338 rb = instr.i_x.i_rb; 339 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 340 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 341 342 addr = tf->tf_fixreg[rb]; 343 if (ra != 0) 344 addr += tf->tf_fixreg[ra]; 345 rt = instr.i_x.i_rt; 346 a = (int *)&fs->fpreg[rt]; 347 DPRINTF(FPE_INSN, 348 ("fpu_execute: Store INT %x at %p\n", 349 a[1], (void *)addr)); 350 if (copyout(&a[1], (void *)addr, sizeof(int))) { 351 fe->fe_addr = addr; 352 return (FAULT); 353 } 354 return (0); 355 } 356 357 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 358 /* Not an indexed FP load/store op */ 359 return (NOTFPU); 360 361 store = (instr.i_x.i_xo & 0x80); 362 if (instr.i_x.i_xo & 0x40) 363 size = sizeof(double); 364 else 365 type = FTYPE_SNG; 366 update = (instr.i_x.i_xo & 0x20); 367 368 /* calculate EA of load/store */ 369 ra = instr.i_x.i_ra; 370 rb = instr.i_x.i_rb; 371 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 372 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 373 addr = tf->tf_fixreg[rb]; 374 if (ra != 0) 375 addr += tf->tf_fixreg[ra]; 376 rt = instr.i_x.i_rt; 377 } else { 378 store = instr.i_d.i_opcd & 0x4; 379 if (instr.i_d.i_opcd & 0x2) 380 size = sizeof(double); 381 else 382 type = FTYPE_SNG; 383 update = instr.i_d.i_opcd & 0x1; 384 385 /* calculate EA of load/store */ 386 ra = instr.i_d.i_ra; 387 addr = instr.i_d.i_d; 388 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 389 ra, tf->tf_fixreg[ra], addr)); 390 if (ra != 0) 391 addr += tf->tf_fixreg[ra]; 392 rt = instr.i_d.i_rt; 393 } 394 395 if (update && ra == 0) 396 return (NOTFPU); 397 398 if (store) { 399 /* Store */ 400 FPU_EMU_EVCNT_INCR(fpstore); 401 if (type != FTYPE_DBL) { 402 DPRINTF(FPE_INSN, 403 ("fpu_execute: Store SNG at %p\n", 404 (void *)addr)); 405 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 406 fpu_implode(fe, fp, type, (void *)&buf); 407 if (copyout(&buf, (void *)addr, size)) { 408 fe->fe_addr = addr; 409 return (FAULT); 410 } 411 } else { 412 DPRINTF(FPE_INSN, 413 ("fpu_execute: Store DBL at %p\n", 414 (void *)addr)); 415 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 416 fe->fe_addr = addr; 417 return (FAULT); 418 } 419 } 420 } else { 421 /* Load */ 422 FPU_EMU_EVCNT_INCR(fpload); 423 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 424 (void *)addr)); 425 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 426 fe->fe_addr = addr; 427 return (FAULT); 428 } 429 if (type != FTYPE_DBL) { 430 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 431 fpu_implode(fe, fp, FTYPE_DBL, 432 (u_int *)&fs->fpreg[rt]); 433 } 434 } 435 if (update) 436 tf->tf_fixreg[ra] = addr; 437 /* Complete. */ 438 return (0); 439 #ifdef notyet 440 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 441 /* These are 64-bit extenstions */ 442 return (NOTFPU); 443 #endif 444 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 445 instr.i_any.i_opcd == OPC_dp_fp_63) { 446 447 448 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 449 !(instr.i_a.i_xo & OPC63M_MASK)) { 450 /* Format X */ 451 rt = instr.i_x.i_rt; 452 ra = instr.i_x.i_ra; 453 rb = instr.i_x.i_rb; 454 455 456 /* One of the special opcodes.... */ 457 switch (instr.i_x.i_xo) { 458 case OPC63_FCMPU: 459 FPU_EMU_EVCNT_INCR(fcmpu); 460 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 461 rt >>= 2; 462 fpu_explode(fe, &fe->fe_f1, type, ra); 463 fpu_explode(fe, &fe->fe_f2, type, rb); 464 fpu_compare(fe, 0); 465 /* Make sure we do the condition regs. */ 466 cond = 0; 467 /* N.B.: i_rs is already left shifted by two. */ 468 bf = instr.i_x.i_rs & 0xfc; 469 setcr = 1; 470 break; 471 472 case OPC63_FRSP: 473 /* 474 * Convert to single: 475 * 476 * PowerPC uses this to round a double 477 * precision value to single precision, 478 * but values in registers are always 479 * stored in double precision format. 480 */ 481 FPU_EMU_EVCNT_INCR(frsp); 482 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 483 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 484 fpu_implode(fe, fp, FTYPE_SNG, 485 (u_int *)&fs->fpreg[rt]); 486 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 487 type = FTYPE_DBL; 488 break; 489 case OPC63_FCTIW: 490 case OPC63_FCTIWZ: 491 FPU_EMU_EVCNT_INCR(fctiw); 492 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 493 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 494 type = FTYPE_INT; 495 break; 496 case OPC63_FCMPO: 497 FPU_EMU_EVCNT_INCR(fcmpo); 498 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 499 rt >>= 2; 500 fpu_explode(fe, &fe->fe_f1, type, ra); 501 fpu_explode(fe, &fe->fe_f2, type, rb); 502 fpu_compare(fe, 1); 503 /* Make sure we do the condition regs. */ 504 cond = 0; 505 /* N.B.: i_rs is already left shifted by two. */ 506 bf = instr.i_x.i_rs & 0xfc; 507 setcr = 1; 508 break; 509 case OPC63_MTFSB1: 510 FPU_EMU_EVCNT_INCR(mtfsb1); 511 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 512 fe->fe_fpscr |= 513 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 514 break; 515 case OPC63_FNEG: 516 FPU_EMU_EVCNT_INCR(fnegabs); 517 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 518 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 519 sizeof(double)); 520 a = (int *)&fs->fpreg[rt]; 521 *a ^= (1 << 31); 522 break; 523 case OPC63_MCRFS: 524 FPU_EMU_EVCNT_INCR(mcrfs); 525 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 526 cond = 0; 527 rt &= 0x1c; 528 ra &= 0x1c; 529 /* Extract the bits we want */ 530 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 531 /* Clear the bits we copied. */ 532 fe->fe_cx = 533 (FPSR_EX_MSK | (0xf << (28 - ra))); 534 fe->fe_fpscr &= fe->fe_cx; 535 /* Now shove them in the right part of cr */ 536 tf->tf_cr &= ~(0xf << (28 - rt)); 537 tf->tf_cr |= (mask << (28 - rt)); 538 break; 539 case OPC63_MTFSB0: 540 FPU_EMU_EVCNT_INCR(mtfsb0); 541 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 542 fe->fe_fpscr &= 543 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 544 break; 545 case OPC63_FMR: 546 FPU_EMU_EVCNT_INCR(fmr); 547 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 548 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 549 sizeof(double)); 550 break; 551 case OPC63_MTFSFI: 552 FPU_EMU_EVCNT_INCR(mtfsfi); 553 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 554 rb >>= 1; 555 rt &= 0x1c; /* Already left-shifted 4 */ 556 fe->fe_cx = rb << (28 - rt); 557 mask = 0xf<<(28 - rt); 558 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 559 fe->fe_cx; 560 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 561 break; 562 case OPC63_FNABS: 563 FPU_EMU_EVCNT_INCR(fnabs); 564 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 565 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 566 sizeof(double)); 567 a = (int *)&fs->fpreg[rt]; 568 *a |= (1 << 31); 569 break; 570 case OPC63_FABS: 571 FPU_EMU_EVCNT_INCR(fabs); 572 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 573 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 574 sizeof(double)); 575 a = (int *)&fs->fpreg[rt]; 576 *a &= ~(1 << 31); 577 break; 578 case OPC63_MFFS: 579 FPU_EMU_EVCNT_INCR(mffs); 580 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 581 /* XXX FEX is not sticky */ 582 fs->fpscr &= ~FPSCR_FEX; 583 memcpy(&fs->fpreg[rt], &fs->fpscr, 584 sizeof(fs->fpscr)); 585 break; 586 case OPC63_MTFSF: 587 FPU_EMU_EVCNT_INCR(mtfsf); 588 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 589 if ((rt = instr.i_xfl.i_flm) == -1) 590 mask = -1; 591 else { 592 mask = 0; 593 /* Convert 1 bit -> 4 bits */ 594 for (ra = 0; ra < 8; ra ++) 595 if (rt & (1<<ra)) 596 mask |= (0xf<<(4*ra)); 597 } 598 a = (int *)&fs->fpreg[rb]; 599 fe->fe_cx = mask & a[1]; 600 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 601 (fe->fe_cx); 602 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 603 break; 604 case OPC63_FCTID: 605 case OPC63_FCTIDZ: 606 FPU_EMU_EVCNT_INCR(fctid); 607 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 608 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 609 type = FTYPE_LNG; 610 break; 611 case OPC63_FCFID: 612 FPU_EMU_EVCNT_INCR(fcfid); 613 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 614 type = FTYPE_LNG; 615 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 616 type = FTYPE_DBL; 617 break; 618 default: 619 return (NOTFPU); 620 break; 621 } 622 } else { 623 /* Format A */ 624 rt = instr.i_a.i_frt; 625 ra = instr.i_a.i_fra; 626 rb = instr.i_a.i_frb; 627 rc = instr.i_a.i_frc; 628 629 /* 630 * All arithmetic operations work on registers, which 631 * are stored as doubles. 632 */ 633 type = FTYPE_DBL; 634 switch ((unsigned int)instr.i_a.i_xo) { 635 case OPC59_FDIVS: 636 FPU_EMU_EVCNT_INCR(fdiv); 637 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 638 fpu_explode(fe, &fe->fe_f1, type, ra); 639 fpu_explode(fe, &fe->fe_f2, type, rb); 640 fp = fpu_div(fe); 641 break; 642 case OPC59_FSUBS: 643 FPU_EMU_EVCNT_INCR(fsub); 644 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 645 fpu_explode(fe, &fe->fe_f1, type, ra); 646 fpu_explode(fe, &fe->fe_f2, type, rb); 647 fp = fpu_sub(fe); 648 break; 649 case OPC59_FADDS: 650 FPU_EMU_EVCNT_INCR(fadd); 651 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 652 fpu_explode(fe, &fe->fe_f1, type, ra); 653 fpu_explode(fe, &fe->fe_f2, type, rb); 654 fp = fpu_add(fe); 655 break; 656 case OPC59_FSQRTS: 657 FPU_EMU_EVCNT_INCR(fsqrt); 658 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 659 fpu_explode(fe, &fe->fe_f1, type, rb); 660 fp = fpu_sqrt(fe); 661 break; 662 case OPC63M_FSEL: 663 FPU_EMU_EVCNT_INCR(fsel); 664 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 665 a = (int *)&fe->fe_fpstate->fpreg[ra]; 666 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 667 /* fra < 0 */ 668 rc = rb; 669 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 670 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 671 sizeof(double)); 672 break; 673 case OPC59_FRES: 674 FPU_EMU_EVCNT_INCR(fpres); 675 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 676 fpu_explode(fe, &fe->fe_f1, type, rb); 677 fp = fpu_sqrt(fe); 678 /* now we've gotta overwrite the dest reg */ 679 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 680 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 681 fpu_div(fe); 682 break; 683 case OPC59_FMULS: 684 FPU_EMU_EVCNT_INCR(fmul); 685 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 686 fpu_explode(fe, &fe->fe_f1, type, ra); 687 fpu_explode(fe, &fe->fe_f2, type, rc); 688 fp = fpu_mul(fe); 689 break; 690 case OPC63M_FRSQRTE: 691 /* Reciprocal sqrt() estimate */ 692 FPU_EMU_EVCNT_INCR(frsqrte); 693 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 694 fpu_explode(fe, &fe->fe_f1, type, rb); 695 fp = fpu_sqrt(fe); 696 fe->fe_f2 = *fp; 697 /* now we've gotta overwrite the dest reg */ 698 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 699 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 700 fpu_div(fe); 701 break; 702 case OPC59_FMSUBS: 703 FPU_EMU_EVCNT_INCR(fmulsub); 704 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 705 fpu_explode(fe, &fe->fe_f1, type, ra); 706 fpu_explode(fe, &fe->fe_f2, type, rc); 707 fp = fpu_mul(fe); 708 fe->fe_f1 = *fp; 709 fpu_explode(fe, &fe->fe_f2, type, rb); 710 fp = fpu_sub(fe); 711 break; 712 case OPC59_FMADDS: 713 FPU_EMU_EVCNT_INCR(fmuladd); 714 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 715 fpu_explode(fe, &fe->fe_f1, type, ra); 716 fpu_explode(fe, &fe->fe_f2, type, rc); 717 fp = fpu_mul(fe); 718 fe->fe_f1 = *fp; 719 fpu_explode(fe, &fe->fe_f2, type, rb); 720 fp = fpu_add(fe); 721 break; 722 case OPC59_FNMSUBS: 723 FPU_EMU_EVCNT_INCR(fnmsub); 724 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 725 fpu_explode(fe, &fe->fe_f1, type, ra); 726 fpu_explode(fe, &fe->fe_f2, type, rc); 727 fp = fpu_mul(fe); 728 fe->fe_f1 = *fp; 729 fpu_explode(fe, &fe->fe_f2, type, rb); 730 fp = fpu_sub(fe); 731 /* Negate */ 732 fp->fp_sign ^= 1; 733 break; 734 case OPC59_FNMADDS: 735 FPU_EMU_EVCNT_INCR(fnmadd); 736 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 737 fpu_explode(fe, &fe->fe_f1, type, ra); 738 fpu_explode(fe, &fe->fe_f2, type, rc); 739 fp = fpu_mul(fe); 740 fe->fe_f1 = *fp; 741 fpu_explode(fe, &fe->fe_f2, type, rb); 742 fp = fpu_add(fe); 743 /* Negate */ 744 fp->fp_sign ^= 1; 745 break; 746 default: 747 return (NOTFPU); 748 break; 749 } 750 751 /* If the instruction was single precision, round */ 752 if (!(instr.i_any.i_opcd & 0x4)) { 753 fpu_implode(fe, fp, FTYPE_SNG, 754 (u_int *)&fs->fpreg[rt]); 755 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 756 } 757 } 758 } else { 759 return (NOTFPU); 760 } 761 762 /* 763 * ALU operation is complete. Collapse the result and then check 764 * for exceptions. If we got any, and they are enabled, do not 765 * alter the destination register, just stop with an exception. 766 * Otherwise set new current exceptions and accrue. 767 */ 768 if (fp) 769 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 770 cx = fe->fe_cx; 771 fsr = fe->fe_fpscr; 772 if (cx != 0) { 773 fsr &= ~FPSCR_FX; 774 if ((cx^fsr)&FPSR_EX_MSK) 775 fsr |= FPSCR_FX; 776 mask = fsr & FPSR_EX; 777 mask <<= (25-3); 778 if (cx & mask) 779 fsr |= FPSCR_FEX; 780 if (cx & FPSCR_FPRF) { 781 /* Need to replace CC */ 782 fsr &= ~FPSCR_FPRF; 783 } 784 if (cx & (FPSR_EXOP)) 785 fsr |= FPSCR_VX; 786 fsr |= cx; 787 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 788 } 789 790 if (cond) { 791 cond = fsr & 0xf0000000; 792 /* Isolate condition codes */ 793 cond >>= 28; 794 /* Move fpu condition codes to cr[1] */ 795 tf->tf_cr &= (0x0f000000); 796 tf->tf_cr |= (cond<<24); 797 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 798 } 799 800 if (setcr) { 801 cond = fsr & FPSCR_FPCC; 802 /* Isolate condition codes */ 803 cond <<= 16; 804 /* Move fpu condition codes to cr[1] */ 805 tf->tf_cr &= ~(0xf0000000>>bf); 806 tf->tf_cr |= (cond>>bf); 807 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, cond)); 808 } 809 810 ((int *)&fs->fpscr)[1] = fsr; 811 if (fsr & FPSCR_FEX) 812 return(FPE); 813 return (0); /* success */ 814 } 815
Indexes created Fri Sep 26 08:10:20 GMT 2025