fpu_emu.c revision 1.43
1 /* $NetBSD: fpu_emu.c,v 1.43 2022/08/30 11:09:34 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.43 2022/08/30 11:09:34 rin Exp $"); 80 81 #ifdef _KERNEL_OPT 82 #include "opt_ddb.h" 83 #endif 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/evcnt.h> 88 #include <sys/proc.h> 89 #include <sys/siginfo.h> 90 #include <sys/signal.h> 91 #include <sys/signalvar.h> 92 #include <sys/syslog.h> 93 94 #include <powerpc/instr.h> 95 #include <powerpc/psl.h> 96 97 #include <machine/fpu.h> 98 #include <machine/reg.h> 99 #include <machine/trap.h> 100 101 #include <powerpc/fpu/fpu_emu.h> 102 #include <powerpc/fpu/fpu_extern.h> 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static struct evcnt fpu_emu_ev_##name = \ 106 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 107 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 108 109 #define FPU_EMU_EVCNT_INCR(name) \ 110 fpu_emu_ev_##name.ev_count++ 111 112 FPU_EMU_EVCNT_DECL(stfiwx); 113 FPU_EMU_EVCNT_DECL(fpstore); 114 FPU_EMU_EVCNT_DECL(fpload); 115 FPU_EMU_EVCNT_DECL(fcmpu); 116 FPU_EMU_EVCNT_DECL(frsp); 117 FPU_EMU_EVCNT_DECL(fctiw); 118 FPU_EMU_EVCNT_DECL(fcmpo); 119 FPU_EMU_EVCNT_DECL(mtfsb1); 120 FPU_EMU_EVCNT_DECL(fnegabs); 121 FPU_EMU_EVCNT_DECL(mcrfs); 122 FPU_EMU_EVCNT_DECL(mtfsb0); 123 FPU_EMU_EVCNT_DECL(fmr); 124 FPU_EMU_EVCNT_DECL(mtfsfi); 125 FPU_EMU_EVCNT_DECL(fnabs); 126 FPU_EMU_EVCNT_DECL(fabs); 127 FPU_EMU_EVCNT_DECL(mffs); 128 FPU_EMU_EVCNT_DECL(mtfsf); 129 FPU_EMU_EVCNT_DECL(fctid); 130 FPU_EMU_EVCNT_DECL(fcfid); 131 FPU_EMU_EVCNT_DECL(fdiv); 132 FPU_EMU_EVCNT_DECL(fsub); 133 FPU_EMU_EVCNT_DECL(fadd); 134 FPU_EMU_EVCNT_DECL(fsqrt); 135 FPU_EMU_EVCNT_DECL(fsel); 136 FPU_EMU_EVCNT_DECL(fpres); 137 FPU_EMU_EVCNT_DECL(fmul); 138 FPU_EMU_EVCNT_DECL(frsqrte); 139 FPU_EMU_EVCNT_DECL(fmulsub); 140 FPU_EMU_EVCNT_DECL(fmuladd); 141 FPU_EMU_EVCNT_DECL(fnmsub); 142 FPU_EMU_EVCNT_DECL(fnmadd); 143 144 /* FPSR exception masks */ 145 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 146 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 147 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 148 FPSCR_VXSQRT|FPSCR_VXCVI) 149 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 150 #define FPSR_INV (FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 151 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 152 FPSCR_VXSQRT|FPSCR_VXCVI) 153 #define MCRFS_MASK \ 154 ( \ 155 FPSCR_FX | FPSCR_OX | \ 156 FPSCR_UX | FPSCR_ZX | FPSCR_XX | FPSCR_VXSNAN | \ 157 FPSCR_VXISI | FPSCR_VXIDI | FPSCR_VXZDZ | FPSCR_VXIMZ | \ 158 FPSCR_VXVC | \ 159 FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI \ 160 ) 161 162 163 int fpe_debug = 0; 164 165 #ifdef DDB 166 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 167 #endif 168 169 #ifdef DEBUG 170 /* 171 * Dump a `fpn' structure. 172 */ 173 void 174 fpu_dumpfpn(struct fpn *fp) 175 { 176 static const char *class[] = { 177 "SNAN", "QNAN", "ZERO", "NUM", "INF" 178 }; 179 180 KASSERT(fp != NULL); 181 182 printf("%s %c.%x %x %x %xE%d\n", class[fp->fp_class + 2], 183 fp->fp_sign ? '-' : ' ', 184 fp->fp_mant[0], fp->fp_mant[1], 185 fp->fp_mant[2], fp->fp_mant[3], 186 fp->fp_exp); 187 } 188 #endif 189 190 /* 191 * fpu_execute returns the following error numbers (0 = no error): 192 */ 193 #define FPE 1 /* take a floating point exception */ 194 #define NOTFPU 2 /* not an FPU instruction */ 195 #define FAULT 3 196 197 198 /* 199 * Emulate a floating-point instruction. 200 * Return true if insn is consumed anyway. 201 * Otherwise, the caller must take care of it. 202 */ 203 bool 204 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 205 { 206 struct pcb *pcb; 207 union instr insn; 208 struct fpemu fe; 209 210 KSI_INIT_TRAP(ksi); 211 ksi->ksi_signo = 0; 212 ksi->ksi_addr = (void *)tf->tf_srr0; 213 214 /* initialize insn.is_datasize to tell it is *not* initialized */ 215 fe.fe_fpstate = fpf; 216 fe.fe_cx = 0; 217 218 /* always set this (to avoid a warning) */ 219 220 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 221 #ifdef DEBUG 222 printf("fpu_emulate: fault reading opcode\n"); 223 #endif 224 ksi->ksi_signo = SIGSEGV; 225 ksi->ksi_trap = EXC_ISI; 226 ksi->ksi_code = SEGV_MAPERR; 227 return true; 228 } 229 230 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 231 insn.i_int, (void *)tf->tf_srr0)); 232 233 if ((insn.i_any.i_opcd == OPC_TWI) || 234 ((insn.i_any.i_opcd == OPC_integer_31) && 235 (insn.i_x.i_xo == OPC31_TW))) { 236 /* Check for the two trap insns. */ 237 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 238 ksi->ksi_signo = SIGTRAP; 239 ksi->ksi_trap = EXC_PGM; 240 ksi->ksi_code = TRAP_BRKPT; 241 return true; 242 } 243 switch (fpu_execute(tf, &fe, &insn)) { 244 case 0: 245 success: 246 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 247 tf->tf_srr0 += 4; 248 return true; 249 250 case FPE: 251 pcb = lwp_getpcb(curlwp); 252 if ((pcb->pcb_flags & PSL_FE_PREC) == 0) 253 goto success; 254 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 255 ksi->ksi_signo = SIGFPE; 256 ksi->ksi_trap = EXC_PGM; 257 ksi->ksi_code = fpu_get_fault_code(); 258 return true; 259 260 case FAULT: 261 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 262 ksi->ksi_signo = SIGSEGV; 263 ksi->ksi_trap = EXC_DSI; 264 ksi->ksi_code = SEGV_MAPERR; 265 ksi->ksi_addr = (void *)fe.fe_addr; 266 return true; 267 268 case NOTFPU: 269 default: 270 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 271 #if defined(DDB) && defined(DEBUG) 272 if (fpe_debug & FPE_EX) { 273 printf("fpu_emulate: illegal insn %x at %p:", 274 insn.i_int, (void *) (tf->tf_srr0)); 275 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 276 } 277 #endif 278 return false; 279 } 280 } 281 282 /* 283 * Execute an FPU instruction (one that runs entirely in the FPU; not 284 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 285 * modified to reflect the setting the hardware would have left. 286 * 287 * Note that we do not catch all illegal opcodes, so you can, for instance, 288 * multiply two integers this way. 289 */ 290 int 291 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 292 { 293 struct fpn *fp; 294 union instr instr = *insn; 295 int *a; 296 vaddr_t addr; 297 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 298 unsigned int bits, cond; 299 struct fpreg *fs; 300 int i, mtfsb1 = 0; 301 302 /* Setup work. */ 303 fp = NULL; 304 fs = fe->fe_fpstate; 305 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 306 307 /* 308 * On PowerPC all floating point values are stored in registers 309 * as doubles, even when used for single precision operations. 310 */ 311 type = FTYPE_DBL; 312 cond = instr.i_any.i_rc; 313 setcr = 0; 314 bf = 0; /* XXX gcc */ 315 316 #if defined(DDB) && defined(DEBUG) 317 if (fpe_debug & FPE_EX) { 318 vaddr_t loc = tf->tf_srr0; 319 320 printf("Trying to emulate: %p ", (void *)loc); 321 opc_disasm(loc, instr.i_int); 322 } 323 #endif 324 325 /* 326 * `Decode' and execute instruction. 327 */ 328 329 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 330 instr.i_any.i_opcd == OPC_integer_31) { 331 /* 332 * Handle load/store insns: 333 * 334 * Convert to/from single if needed, calculate addr, 335 * and update index reg if needed. 336 */ 337 uint64_t buf; 338 size_t size = sizeof(float); 339 int store, update; 340 341 cond = 0; /* ld/st never set condition codes */ 342 343 344 if (instr.i_any.i_opcd == OPC_integer_31) { 345 if (instr.i_x.i_xo == OPC31_STFIWX) { 346 FPU_EMU_EVCNT_INCR(stfiwx); 347 348 /* Store as integer */ 349 ra = instr.i_x.i_ra; 350 rb = instr.i_x.i_rb; 351 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 352 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 353 354 addr = tf->tf_fixreg[rb]; 355 if (ra != 0) 356 addr += tf->tf_fixreg[ra]; 357 rt = instr.i_x.i_rt; 358 a = (int *)&fs->fpreg[rt]; 359 DPRINTF(FPE_INSN, 360 ("fpu_execute: Store INT %x at %p\n", 361 a[1], (void *)addr)); 362 if (copyout(&a[1], (void *)addr, sizeof(int))) { 363 fe->fe_addr = addr; 364 return (FAULT); 365 } 366 return (0); 367 } 368 369 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 370 /* Not an indexed FP load/store op */ 371 return (NOTFPU); 372 373 store = (instr.i_x.i_xo & 0x80); 374 if (instr.i_x.i_xo & 0x40) 375 size = sizeof(double); 376 else 377 type = FTYPE_SNG; 378 update = (instr.i_x.i_xo & 0x20); 379 380 /* calculate EA of load/store */ 381 ra = instr.i_x.i_ra; 382 rb = instr.i_x.i_rb; 383 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 384 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 385 addr = tf->tf_fixreg[rb]; 386 if (ra != 0) 387 addr += tf->tf_fixreg[ra]; 388 rt = instr.i_x.i_rt; 389 } else { 390 store = instr.i_d.i_opcd & 0x4; 391 if (instr.i_d.i_opcd & 0x2) 392 size = sizeof(double); 393 else 394 type = FTYPE_SNG; 395 update = instr.i_d.i_opcd & 0x1; 396 397 /* calculate EA of load/store */ 398 ra = instr.i_d.i_ra; 399 addr = instr.i_d.i_d; 400 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 401 ra, tf->tf_fixreg[ra], addr)); 402 if (ra != 0) 403 addr += tf->tf_fixreg[ra]; 404 rt = instr.i_d.i_rt; 405 } 406 407 if (update && ra == 0) 408 return (NOTFPU); 409 410 if (store) { 411 /* Store */ 412 FPU_EMU_EVCNT_INCR(fpstore); 413 if (type != FTYPE_DBL) { 414 DPRINTF(FPE_INSN, 415 ("fpu_execute: Store SNG at %p\n", 416 (void *)addr)); 417 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 418 fpu_implode(fe, fp, type, (void *)&buf); 419 if (copyout(&buf, (void *)addr, size)) { 420 fe->fe_addr = addr; 421 return (FAULT); 422 } 423 } else { 424 DPRINTF(FPE_INSN, 425 ("fpu_execute: Store DBL at %p\n", 426 (void *)addr)); 427 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 428 fe->fe_addr = addr; 429 return (FAULT); 430 } 431 } 432 } else { 433 /* Load */ 434 FPU_EMU_EVCNT_INCR(fpload); 435 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 436 (void *)addr)); 437 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 438 fe->fe_addr = addr; 439 return (FAULT); 440 } 441 if (type != FTYPE_DBL) { 442 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 443 fpu_implode(fe, fp, FTYPE_DBL, 444 (u_int *)&fs->fpreg[rt]); 445 } 446 } 447 if (update) 448 tf->tf_fixreg[ra] = addr; 449 /* Complete. */ 450 return (0); 451 #ifdef notyet 452 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 453 /* These are 64-bit extenstions */ 454 return (NOTFPU); 455 #endif 456 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 457 instr.i_any.i_opcd == OPC_dp_fp_63) { 458 459 460 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 461 !(instr.i_a.i_xo & OPC63M_MASK)) { 462 /* Format X */ 463 rt = instr.i_x.i_rt; 464 ra = instr.i_x.i_ra; 465 rb = instr.i_x.i_rb; 466 467 468 /* One of the special opcodes.... */ 469 switch (instr.i_x.i_xo) { 470 case OPC63_FCMPU: 471 FPU_EMU_EVCNT_INCR(fcmpu); 472 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 473 rt >>= 2; 474 fpu_explode(fe, &fe->fe_f1, type, ra); 475 fpu_explode(fe, &fe->fe_f2, type, rb); 476 fpu_compare(fe, 0); 477 /* Make sure we do the condition regs. */ 478 cond = 0; 479 /* N.B.: i_rs is already left shifted by two. */ 480 bf = instr.i_x.i_rs & 0xfc; 481 setcr = 1; 482 break; 483 484 case OPC63_FRSP: 485 /* 486 * Convert to single: 487 * 488 * PowerPC uses this to round a double 489 * precision value to single precision, 490 * but values in registers are always 491 * stored in double precision format. 492 */ 493 FPU_EMU_EVCNT_INCR(frsp); 494 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 495 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 496 fpu_implode(fe, fp, FTYPE_SNG, 497 (u_int *)&fs->fpreg[rt]); 498 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 499 type = FTYPE_DBL; 500 break; 501 case OPC63_FCTIW: 502 case OPC63_FCTIWZ: 503 FPU_EMU_EVCNT_INCR(fctiw); 504 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 505 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 506 type = FTYPE_INT; 507 if (instr.i_x.i_xo == OPC63_FCTIWZ) 508 type |= FTYPE_RD_RZ; 509 break; 510 case OPC63_FCMPO: 511 FPU_EMU_EVCNT_INCR(fcmpo); 512 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 513 rt >>= 2; 514 fpu_explode(fe, &fe->fe_f1, type, ra); 515 fpu_explode(fe, &fe->fe_f2, type, rb); 516 fpu_compare(fe, 1); 517 /* Make sure we do the condition regs. */ 518 cond = 0; 519 /* N.B.: i_rs is already left shifted by two. */ 520 bf = instr.i_x.i_rs & 0xfc; 521 setcr = 1; 522 break; 523 case OPC63_MTFSB1: 524 FPU_EMU_EVCNT_INCR(mtfsb1); 525 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 526 mtfsb1 = 1; 527 fe->fe_cx = (1 << (31 - rt)) & 528 ~(FPSCR_FEX | FPSCR_VX); 529 break; 530 case OPC63_FNEG: 531 FPU_EMU_EVCNT_INCR(fnegabs); 532 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 533 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 534 sizeof(double)); 535 a = (int *)&fs->fpreg[rt]; 536 *a ^= (1 << 31); 537 break; 538 case OPC63_MCRFS: 539 FPU_EMU_EVCNT_INCR(mcrfs); 540 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 541 cond = 0; 542 rt &= 0x1c; 543 ra &= 0x1c; 544 /* Extract the bits we want */ 545 bits = (fe->fe_fpscr >> (28 - ra)) & 0xf; 546 /* Clear the bits we copied. */ 547 mask = (0xf << (28 - ra)) & MCRFS_MASK; 548 fe->fe_fpscr &= ~mask; 549 /* Now shove them in the right part of cr */ 550 tf->tf_cr &= ~(0xf << (28 - rt)); 551 tf->tf_cr |= bits << (28 - rt); 552 break; 553 case OPC63_MTFSB0: 554 FPU_EMU_EVCNT_INCR(mtfsb0); 555 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 556 fe->fe_fpscr &= ~(1 << (31 - rt)) | 557 (FPSCR_FEX | FPSCR_VX); 558 break; 559 case OPC63_FMR: 560 FPU_EMU_EVCNT_INCR(fmr); 561 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 562 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 563 sizeof(double)); 564 break; 565 case OPC63_MTFSFI: 566 FPU_EMU_EVCNT_INCR(mtfsfi); 567 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 568 rb >>= 1; 569 rt &= 0x1c; /* Already left-shifted 4 */ 570 bits = rb << (28 - rt); 571 mask = 0xf << (28 - rt); 572 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | bits; 573 break; 574 case OPC63_FNABS: 575 FPU_EMU_EVCNT_INCR(fnabs); 576 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 577 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 578 sizeof(double)); 579 a = (int *)&fs->fpreg[rt]; 580 *a |= (1 << 31); 581 break; 582 case OPC63_FABS: 583 FPU_EMU_EVCNT_INCR(fabs); 584 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 585 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 586 sizeof(double)); 587 a = (int *)&fs->fpreg[rt]; 588 *a &= ~(1 << 31); 589 break; 590 case OPC63_MFFS: 591 FPU_EMU_EVCNT_INCR(mffs); 592 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 593 memcpy(&fs->fpreg[rt], &fs->fpscr, 594 sizeof(fs->fpscr)); 595 break; 596 case OPC63_MTFSF: 597 FPU_EMU_EVCNT_INCR(mtfsf); 598 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 599 if ((rt = instr.i_xfl.i_flm) == -1) { 600 mask = -1; 601 } else { 602 mask = 0; 603 /* Convert 1 bit -> 4 bits */ 604 for (i = 0; i < 8; i++) 605 if (rt & (1 << i)) 606 mask |= 607 (0xf << (4 * i)); 608 } 609 a = (int *)&fs->fpreg[rb]; 610 bits = a[1] & mask; 611 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | bits; 612 break; 613 case OPC63_FCTID: 614 case OPC63_FCTIDZ: 615 FPU_EMU_EVCNT_INCR(fctid); 616 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 617 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 618 type = FTYPE_LNG; 619 if (instr.i_x.i_xo == OPC63_FCTIDZ) 620 type |= FTYPE_RD_RZ; 621 break; 622 case OPC63_FCFID: 623 FPU_EMU_EVCNT_INCR(fcfid); 624 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 625 type = FTYPE_LNG; 626 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 627 type = FTYPE_DBL; 628 break; 629 default: 630 return (NOTFPU); 631 break; 632 } 633 } else { 634 /* Format A */ 635 rt = instr.i_a.i_frt; 636 ra = instr.i_a.i_fra; 637 rb = instr.i_a.i_frb; 638 rc = instr.i_a.i_frc; 639 640 /* 641 * All arithmetic operations work on registers, which 642 * are stored as doubles. 643 */ 644 type = FTYPE_DBL; 645 switch ((unsigned int)instr.i_a.i_xo) { 646 case OPC59_FDIVS: 647 FPU_EMU_EVCNT_INCR(fdiv); 648 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 649 fpu_explode(fe, &fe->fe_f1, type, ra); 650 fpu_explode(fe, &fe->fe_f2, type, rb); 651 fp = fpu_div(fe); 652 break; 653 case OPC59_FSUBS: 654 FPU_EMU_EVCNT_INCR(fsub); 655 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 656 fpu_explode(fe, &fe->fe_f1, type, ra); 657 fpu_explode(fe, &fe->fe_f2, type, rb); 658 fp = fpu_sub(fe); 659 break; 660 case OPC59_FADDS: 661 FPU_EMU_EVCNT_INCR(fadd); 662 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 663 fpu_explode(fe, &fe->fe_f1, type, ra); 664 fpu_explode(fe, &fe->fe_f2, type, rb); 665 fp = fpu_add(fe); 666 break; 667 case OPC59_FSQRTS: 668 FPU_EMU_EVCNT_INCR(fsqrt); 669 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 670 fpu_explode(fe, &fe->fe_f1, type, rb); 671 fp = fpu_sqrt(fe); 672 break; 673 case OPC63M_FSEL: 674 FPU_EMU_EVCNT_INCR(fsel); 675 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 676 a = (int *)&fe->fe_fpstate->fpreg[ra]; 677 if ((( a[0] & 0x80000000) && 678 ((a[0] & 0x7fffffff) | a[1])) || 679 (( a[0] & 0x7ff00000) && 680 ((a[0] & 0x000fffff) | a[1]))) { 681 /* negative/NaN or NaN */ 682 rc = rb; 683 } 684 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 685 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 686 sizeof(double)); 687 break; 688 case OPC59_FRES: 689 FPU_EMU_EVCNT_INCR(fpres); 690 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 691 fpu_explode(fe, &fe->fe_f1, type, rb); 692 fp = fpu_sqrt(fe); 693 /* now we've gotta overwrite the dest reg */ 694 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 695 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 696 fpu_div(fe); 697 break; 698 case OPC59_FMULS: 699 FPU_EMU_EVCNT_INCR(fmul); 700 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 701 fpu_explode(fe, &fe->fe_f1, type, ra); 702 fpu_explode(fe, &fe->fe_f2, type, rc); 703 fp = fpu_mul(fe); 704 break; 705 case OPC63M_FRSQRTE: 706 /* Reciprocal sqrt() estimate */ 707 FPU_EMU_EVCNT_INCR(frsqrte); 708 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 709 fpu_explode(fe, &fe->fe_f1, type, rb); 710 fp = fpu_sqrt(fe); 711 fe->fe_f2 = *fp; 712 /* now we've gotta overwrite the dest reg */ 713 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 714 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 715 fpu_div(fe); 716 break; 717 case OPC59_FMSUBS: 718 FPU_EMU_EVCNT_INCR(fmulsub); 719 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 720 fpu_explode(fe, &fe->fe_f1, type, ra); 721 fpu_explode(fe, &fe->fe_f2, type, rc); 722 fp = fpu_mul(fe); 723 fe->fe_f1 = *fp; 724 fpu_explode(fe, &fe->fe_f2, type, rb); 725 fp = fpu_sub(fe); 726 break; 727 case OPC59_FMADDS: 728 FPU_EMU_EVCNT_INCR(fmuladd); 729 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 730 fpu_explode(fe, &fe->fe_f1, type, ra); 731 fpu_explode(fe, &fe->fe_f2, type, rc); 732 fp = fpu_mul(fe); 733 fe->fe_f1 = *fp; 734 fpu_explode(fe, &fe->fe_f2, type, rb); 735 fp = fpu_add(fe); 736 break; 737 case OPC59_FNMSUBS: 738 FPU_EMU_EVCNT_INCR(fnmsub); 739 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 740 fpu_explode(fe, &fe->fe_f1, type, ra); 741 fpu_explode(fe, &fe->fe_f2, type, rc); 742 fp = fpu_mul(fe); 743 fe->fe_f1 = *fp; 744 fpu_explode(fe, &fe->fe_f2, type, rb); 745 fp = fpu_sub(fe); 746 /* Negate */ 747 fp->fp_sign ^= 1; 748 break; 749 case OPC59_FNMADDS: 750 FPU_EMU_EVCNT_INCR(fnmadd); 751 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 752 fpu_explode(fe, &fe->fe_f1, type, ra); 753 fpu_explode(fe, &fe->fe_f2, type, rc); 754 fp = fpu_mul(fe); 755 fe->fe_f1 = *fp; 756 fpu_explode(fe, &fe->fe_f2, type, rb); 757 fp = fpu_add(fe); 758 /* Negate */ 759 fp->fp_sign ^= 1; 760 break; 761 default: 762 return (NOTFPU); 763 break; 764 } 765 766 /* If the instruction was single precision, round */ 767 if (!(instr.i_any.i_opcd & 0x4)) { 768 fpu_implode(fe, fp, FTYPE_SNG, 769 (u_int *)&fs->fpreg[rt]); 770 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 771 } 772 } 773 } else { 774 return (NOTFPU); 775 } 776 777 /* 778 * ALU operation is complete. Collapse the result and then check 779 * for exceptions. If we got any, and they are enabled, do not 780 * alter the destination register, just stop with an exception. 781 * Otherwise set new current exceptions and accrue. 782 */ 783 if (fp) 784 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 785 cx = fe->fe_cx; 786 fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX); 787 if (cx != 0) { 788 if (mtfsb1 == 0 && (cx & FPSCR_FPRF) != 0) { 789 /* Need to replace CC */ 790 fsr &= ~FPSCR_FPRF; 791 } 792 fsr |= cx; 793 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 794 } 795 if (fsr & FPSR_INV) 796 fsr |= FPSCR_VX; 797 mask = (fsr & FPSR_EX) << (25 - 3); 798 if (fsr & mask) 799 fsr |= FPSCR_FEX; 800 if ((fsr ^ fe->fe_fpscr) & FPSR_EX_MSK) 801 fsr |= FPSCR_FX; 802 803 if (cond) { 804 cond = fsr & 0xf0000000; 805 /* Isolate condition codes */ 806 cond >>= 28; 807 /* Move fpu condition codes to cr[1] */ 808 tf->tf_cr &= ~(0x0f000000); 809 tf->tf_cr |= (cond<<24); 810 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 811 } 812 813 if (setcr) { 814 cond = fsr & FPSCR_FPCC; 815 /* Isolate condition codes */ 816 cond <<= 16; 817 /* Move fpu condition codes to cr[bf/4] */ 818 tf->tf_cr &= ~(0xf0000000>>bf); 819 tf->tf_cr |= (cond>>bf); 820 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, cond)); 821 } 822 823 ((int *)&fs->fpscr)[1] = fsr; 824 if (fsr & FPSCR_FEX) 825 return(FPE); 826 return (0); /* success */ 827 } 828
Indexes created Tue Sep 23 23:09:58 GMT 2025