fpu_emu.c revision 1.5
1 /* $NetBSD: fpu_emu.c,v 1.5 2002/11/25 02:45:46 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. All advertising materials mentioning features or use of this software 60 * must display the following acknowledgement: 61 * This product includes software developed by the University of 62 * California, Berkeley and its contributors. 63 * 4. Neither the name of the University nor the names of its contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 71 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 72 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 73 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 74 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 75 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 76 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 77 * SUCH DAMAGE. 78 * 79 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 80 */ 81 82 #include "opt_ddb.h" 83 84 #include <sys/param.h> 85 #include <sys/proc.h> 86 #include <sys/signal.h> 87 #include <sys/systm.h> 88 #include <sys/syslog.h> 89 #include <sys/signalvar.h> 90 #include <sys/device.h> /* for evcnt */ 91 92 #include <powerpc/instr.h> 93 #include <machine/reg.h> 94 #include <machine/fpu.h> 95 96 #include <powerpc/fpu/fpu_emu.h> 97 #include <powerpc/fpu/fpu_extern.h> 98 99 #define FPU_EMU_EVCNT_DECL(name) \ 100 static struct evcnt fpu_emu_ev_##name = \ 101 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 102 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 103 104 #define FPU_EMU_EVCNT_INCR(name) \ 105 fpu_emu_ev_##name.ev_count++ 106 107 FPU_EMU_EVCNT_DECL(stfiwx); 108 FPU_EMU_EVCNT_DECL(fpstore); 109 FPU_EMU_EVCNT_DECL(fpload); 110 FPU_EMU_EVCNT_DECL(fcmpu); 111 FPU_EMU_EVCNT_DECL(frsp); 112 FPU_EMU_EVCNT_DECL(fctiw); 113 FPU_EMU_EVCNT_DECL(fcmpo); 114 FPU_EMU_EVCNT_DECL(mtfsb1); 115 FPU_EMU_EVCNT_DECL(fnegabs); 116 FPU_EMU_EVCNT_DECL(mcrfs); 117 FPU_EMU_EVCNT_DECL(mtfsb0); 118 FPU_EMU_EVCNT_DECL(fmr); 119 FPU_EMU_EVCNT_DECL(mtfsfi); 120 FPU_EMU_EVCNT_DECL(fnabs); 121 FPU_EMU_EVCNT_DECL(fabs); 122 FPU_EMU_EVCNT_DECL(mffs); 123 FPU_EMU_EVCNT_DECL(mtfsf); 124 FPU_EMU_EVCNT_DECL(fctid); 125 FPU_EMU_EVCNT_DECL(fcfid); 126 FPU_EMU_EVCNT_DECL(fdiv); 127 FPU_EMU_EVCNT_DECL(fsub); 128 FPU_EMU_EVCNT_DECL(fadd); 129 FPU_EMU_EVCNT_DECL(fsqrt); 130 FPU_EMU_EVCNT_DECL(fsel); 131 FPU_EMU_EVCNT_DECL(fpres); 132 FPU_EMU_EVCNT_DECL(fmul); 133 FPU_EMU_EVCNT_DECL(frsqrte); 134 FPU_EMU_EVCNT_DECL(fmulsub); 135 FPU_EMU_EVCNT_DECL(fmuladd); 136 FPU_EMU_EVCNT_DECL(fnmsub); 137 FPU_EMU_EVCNT_DECL(fnmadd); 138 139 /* FPSR exception masks */ 140 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 141 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 142 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 143 FPSCR_VXSQRT|FPSCR_VXCVI) 144 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 145 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 146 147 148 int fpe_debug = 0; 149 150 #ifdef DDB 151 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 152 #endif 153 154 #ifdef DEBUG 155 /* 156 * Dump a `fpn' structure. 157 */ 158 void 159 fpu_dumpfpn(struct fpn *fp) 160 { 161 static char *class[] = { 162 "SNAN", "QNAN", "ZERO", "NUM", "INF" 163 }; 164 165 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 166 fp->fp_sign ? '-' : ' ', 167 fp->fp_mant[0], fp->fp_mant[1], 168 fp->fp_mant[2], fp->fp_mant[3], 169 fp->fp_exp); 170 } 171 #endif 172 173 /* 174 * fpu_execute returns the following error numbers (0 = no error): 175 */ 176 #define FPE 1 /* take a floating point exception */ 177 #define NOTFPU 2 /* not an FPU instruction */ 178 #define FAULT 3 179 180 181 /* 182 * Emulate a floating-point instruction. 183 * Return zero for success, else signal number. 184 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 185 */ 186 int 187 fpu_emulate(struct trapframe *frame, struct fpreg *fpf) 188 { 189 static union instr insn; 190 static struct fpemu fe; 191 static int lastill = 0; 192 int sig; 193 194 /* initialize insn.is_datasize to tell it is *not* initialized */ 195 fe.fe_fpstate = fpf; 196 fe.fe_cx = 0; 197 198 /* always set this (to avoid a warning) */ 199 200 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 201 #ifdef DEBUG 202 printf("fpu_emulate: fault reading opcode\n"); 203 #endif 204 return SIGSEGV; 205 } 206 207 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 208 insn.i_int, (void *)frame->srr0)); 209 210 211 if ((insn.i_any.i_opcd == OPC_TWI) || 212 ((insn.i_any.i_opcd == OPC_integer_31) && 213 (insn.i_x.i_xo == OPC31_TW))) { 214 /* Check for the two trap insns. */ 215 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 216 return (SIGTRAP); 217 } 218 sig = 0; 219 switch (fpu_execute(frame, &fe, &insn)) { 220 case 0: 221 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 222 frame->srr0 += 4; 223 break; 224 225 case FPE: 226 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 227 sig = SIGFPE; 228 break; 229 230 case FAULT: 231 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 232 sig = SIGSEGV; 233 break; 234 235 case NOTFPU: 236 default: 237 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 238 #ifdef DEBUG 239 if (fpe_debug & FPE_EX) { 240 printf("fpu_emulate: illegal insn %x at %p:", 241 insn.i_int, (void *) (frame->srr0)); 242 opc_disasm((vaddr_t)(frame->srr0), insn.i_int); 243 } 244 #endif 245 /* 246 * XXXX retry an illegal insn once due to cache issues. 247 */ 248 if (lastill == frame->srr0) { 249 sig = SIGILL; 250 #ifdef DEBUG 251 if (fpe_debug & FPE_EX) 252 Debugger(); 253 #endif 254 } 255 lastill = frame->srr0; 256 break; 257 } 258 259 return (sig); 260 } 261 262 /* 263 * Execute an FPU instruction (one that runs entirely in the FPU; not 264 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 265 * modified to reflect the setting the hardware would have left. 266 * 267 * Note that we do not catch all illegal opcodes, so you can, for instance, 268 * multiply two integers this way. 269 */ 270 int 271 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 272 { 273 struct fpn *fp; 274 union instr instr = *insn; 275 int *a; 276 vaddr_t addr; 277 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; 278 struct fpreg *fs; 279 280 /* Setup work. */ 281 fp = NULL; 282 fs = fe->fe_fpstate; 283 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 284 285 /* 286 * On PowerPC all floating point values are stored in registers 287 * as doubles, even when used for single precision operations. 288 */ 289 type = FTYPE_DBL; 290 cond = instr.i_any.i_rc; 291 setcr = 0; 292 293 #if defined(DDB) && defined(DEBUG) 294 if (fpe_debug & FPE_EX) { 295 vaddr_t loc = tf->srr0; 296 297 printf("Trying to emulate: %p ", (void *)loc); 298 opc_disasm(loc, instr.i_int); 299 } 300 #endif 301 302 /* 303 * `Decode' and execute instruction. 304 */ 305 306 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 307 instr.i_any.i_opcd == OPC_integer_31) { 308 /* 309 * Handle load/store insns: 310 * 311 * Convert to/from single if needed, calculate addr, 312 * and update index reg if needed. 313 */ 314 double buf; 315 size_t size = sizeof(float); 316 int store, update; 317 318 cond = 0; /* ld/st never set condition codes */ 319 320 321 if (instr.i_any.i_opcd == OPC_integer_31) { 322 if (instr.i_x.i_xo == OPC31_STFIWX) { 323 FPU_EMU_EVCNT_INCR(stfiwx); 324 325 /* Store as integer */ 326 ra = instr.i_x.i_ra; 327 rb = instr.i_x.i_rb; 328 DPRINTF(FPE_INSN, ("reg %d has %x reg %d has %x\n", 329 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 330 331 addr = tf->fixreg[rb]; 332 if (ra != 0) 333 addr += tf->fixreg[ra]; 334 rt = instr.i_x.i_rt; 335 a = (int *)&fs->fpreg[rt]; 336 DPRINTF(FPE_INSN, 337 ("fpu_execute: Store INT %x at %p\n", 338 a[1], (void *)addr)); 339 if (copyout(&a[1], (void *)addr, sizeof(int))) 340 return (FAULT); 341 return (0); 342 } 343 344 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 345 /* Not an indexed FP load/store op */ 346 return (NOTFPU); 347 348 store = (instr.i_x.i_xo & 0x80); 349 if (instr.i_x.i_xo & 0x40) 350 size = sizeof(double); 351 else 352 type = FTYPE_SNG; 353 update = (instr.i_x.i_xo & 0x20); 354 355 /* calculate EA of load/store */ 356 ra = instr.i_x.i_ra; 357 rb = instr.i_x.i_rb; 358 DPRINTF(FPE_INSN, ("reg %d has %x reg %d has %x\n", 359 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 360 addr = tf->fixreg[rb]; 361 if (ra != 0) 362 addr += tf->fixreg[ra]; 363 rt = instr.i_x.i_rt; 364 } else { 365 store = instr.i_d.i_opcd & 0x4; 366 if (instr.i_d.i_opcd & 0x2) 367 size = sizeof(double); 368 else 369 type = FTYPE_SNG; 370 update = instr.i_d.i_opcd & 0x1; 371 372 /* calculate EA of load/store */ 373 ra = instr.i_d.i_ra; 374 addr = instr.i_d.i_d; 375 DPRINTF(FPE_INSN, ("reg %d has %x displ %lx\n", 376 ra, tf->fixreg[ra], addr)); 377 if (ra != 0) 378 addr += tf->fixreg[ra]; 379 rt = instr.i_d.i_rt; 380 } 381 382 if (update && ra == 0) 383 return (NOTFPU); 384 385 if (store) { 386 /* Store */ 387 FPU_EMU_EVCNT_INCR(fpstore); 388 if (type != FTYPE_DBL) { 389 DPRINTF(FPE_INSN, 390 ("fpu_execute: Store SNG at %p\n", 391 (void *)addr)); 392 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 393 fpu_implode(fe, fp, type, (u_int *)&buf); 394 if (copyout(&buf, (void *)addr, size)) 395 return (FAULT); 396 } else { 397 DPRINTF(FPE_INSN, 398 ("fpu_execute: Store DBL at %p\n", 399 (void *)addr)); 400 if (copyout(&fs->fpreg[rt], (void *)addr, size)) 401 return (FAULT); 402 } 403 } else { 404 /* Load */ 405 FPU_EMU_EVCNT_INCR(fpload); 406 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 407 (void *)addr)); 408 if (copyin((const void *)addr, &fs->fpreg[rt], size)) 409 return (FAULT); 410 if (type != FTYPE_DBL) { 411 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 412 fpu_implode(fe, fp, FTYPE_DBL, 413 (u_int *)&fs->fpreg[rt]); 414 } 415 } 416 if (update) 417 tf->fixreg[ra] = addr; 418 /* Complete. */ 419 return (0); 420 #ifdef notyet 421 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 422 /* These are 64-bit extenstions */ 423 return (NOTFPU); 424 #endif 425 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 426 instr.i_any.i_opcd == OPC_dp_fp_63) { 427 428 429 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 430 !(instr.i_a.i_xo & OPC63M_MASK)) { 431 /* Format X */ 432 rt = instr.i_x.i_rt; 433 ra = instr.i_x.i_ra; 434 rb = instr.i_x.i_rb; 435 436 437 /* One of the special opcodes.... */ 438 switch (instr.i_x.i_xo) { 439 case OPC63_FCMPU: 440 FPU_EMU_EVCNT_INCR(fcmpu); 441 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 442 rt >>= 2; 443 fpu_explode(fe, &fe->fe_f1, type, ra); 444 fpu_explode(fe, &fe->fe_f2, type, rb); 445 fpu_compare(fe, 0); 446 /* Make sure we do the condition regs. */ 447 cond = 0; 448 /* N.B.: i_rs is already left shifted by two. */ 449 bf = instr.i_x.i_rs & 0xfc; 450 setcr = 1; 451 break; 452 453 case OPC63_FRSP: 454 /* 455 * Convert to single: 456 * 457 * PowerPC uses this to round a double 458 * precision value to single precision, 459 * but values in registers are always 460 * stored in double precision format. 461 */ 462 FPU_EMU_EVCNT_INCR(frsp); 463 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 464 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 465 fpu_implode(fe, fp, FTYPE_SNG, 466 (u_int *)&fs->fpreg[rt]); 467 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 468 type = FTYPE_DBL; 469 break; 470 case OPC63_FCTIW: 471 case OPC63_FCTIWZ: 472 FPU_EMU_EVCNT_INCR(fctiw); 473 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 474 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 475 type = FTYPE_INT; 476 break; 477 case OPC63_FCMPO: 478 FPU_EMU_EVCNT_INCR(fcmpo); 479 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 480 rt >>= 2; 481 fpu_explode(fe, &fe->fe_f1, type, ra); 482 fpu_explode(fe, &fe->fe_f2, type, rb); 483 fpu_compare(fe, 1); 484 /* Make sure we do the condition regs. */ 485 cond = 0; 486 /* N.B.: i_rs is already left shifted by two. */ 487 bf = instr.i_x.i_rs & 0xfc; 488 setcr = 1; 489 break; 490 case OPC63_MTFSB1: 491 FPU_EMU_EVCNT_INCR(mtfsb1); 492 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 493 fe->fe_fpscr |= 494 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 495 break; 496 case OPC63_FNEG: 497 FPU_EMU_EVCNT_INCR(fnegabs); 498 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 499 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 500 sizeof(double)); 501 a = (int *)&fs->fpreg[rt]; 502 *a ^= (1 << 31); 503 break; 504 case OPC63_MCRFS: 505 FPU_EMU_EVCNT_INCR(mcrfs); 506 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 507 cond = 0; 508 rt &= 0x1c; 509 ra &= 0x1c; 510 /* Extract the bits we want */ 511 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 512 /* Clear the bits we copied. */ 513 fe->fe_cx = 514 (FPSR_EX_MSK | (0xf << (28 - ra))); 515 fe->fe_fpscr &= fe->fe_cx; 516 /* Now shove them in the right part of cr */ 517 tf->cr &= ~(0xf << (28 - rt)); 518 tf->cr |= (mask << (28 - rt)); 519 break; 520 case OPC63_MTFSB0: 521 FPU_EMU_EVCNT_INCR(mtfsb0); 522 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 523 fe->fe_fpscr &= 524 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 525 break; 526 case OPC63_FMR: 527 FPU_EMU_EVCNT_INCR(fmr); 528 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 529 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 530 sizeof(double)); 531 break; 532 case OPC63_MTFSFI: 533 FPU_EMU_EVCNT_INCR(mtfsfi); 534 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 535 rb >>= 1; 536 rt &= 0x1c; /* Already left-shifted 4 */ 537 fe->fe_cx = rb << (28 - rt); 538 mask = 0xf<<(28 - rt); 539 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 540 fe->fe_cx; 541 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 542 break; 543 case OPC63_FNABS: 544 FPU_EMU_EVCNT_INCR(fnabs); 545 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 546 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 547 sizeof(double)); 548 a = (int *)&fs->fpreg[rt]; 549 *a |= (1 << 31); 550 break; 551 case OPC63_FABS: 552 FPU_EMU_EVCNT_INCR(fabs); 553 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 554 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 555 sizeof(double)); 556 a = (int *)&fs->fpreg[rt]; 557 *a &= ~(1 << 31); 558 break; 559 case OPC63_MFFS: 560 FPU_EMU_EVCNT_INCR(mffs); 561 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 562 memcpy(&fs->fpreg[rt], &fs->fpscr, 563 sizeof(fs->fpscr)); 564 break; 565 case OPC63_MTFSF: 566 FPU_EMU_EVCNT_INCR(mtfsf); 567 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 568 if ((rt = instr.i_xfl.i_flm) == -1) 569 mask = -1; 570 else { 571 mask = 0; 572 /* Convert 1 bit -> 4 bits */ 573 for (ra = 0; ra < 8; ra ++) 574 if (rt & (1<<ra)) 575 mask |= (0xf<<(4*ra)); 576 } 577 a = (int *)&fs->fpreg[rt]; 578 fe->fe_cx = mask & a[1]; 579 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 580 (fe->fe_cx); 581 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 582 break; 583 case OPC63_FCTID: 584 case OPC63_FCTIDZ: 585 FPU_EMU_EVCNT_INCR(fctid); 586 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 587 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 588 type = FTYPE_LNG; 589 break; 590 case OPC63_FCFID: 591 FPU_EMU_EVCNT_INCR(fcfid); 592 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 593 type = FTYPE_LNG; 594 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 595 type = FTYPE_DBL; 596 break; 597 default: 598 return (NOTFPU); 599 break; 600 } 601 } else { 602 /* Format A */ 603 rt = instr.i_a.i_frt; 604 ra = instr.i_a.i_fra; 605 rb = instr.i_a.i_frb; 606 rc = instr.i_a.i_frc; 607 608 type = FTYPE_SNG; 609 if (instr.i_any.i_opcd & 0x4) 610 type = FTYPE_DBL; 611 switch ((unsigned int)instr.i_a.i_xo) { 612 case OPC59_FDIVS: 613 FPU_EMU_EVCNT_INCR(fdiv); 614 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 615 fpu_explode(fe, &fe->fe_f1, type, ra); 616 fpu_explode(fe, &fe->fe_f2, type, rb); 617 fp = fpu_div(fe); 618 break; 619 case OPC59_FSUBS: 620 FPU_EMU_EVCNT_INCR(fsub); 621 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 622 fpu_explode(fe, &fe->fe_f1, type, ra); 623 fpu_explode(fe, &fe->fe_f2, type, rb); 624 fp = fpu_sub(fe); 625 break; 626 case OPC59_FADDS: 627 FPU_EMU_EVCNT_INCR(fadd); 628 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 629 fpu_explode(fe, &fe->fe_f1, type, ra); 630 fpu_explode(fe, &fe->fe_f2, type, rb); 631 fp = fpu_add(fe); 632 break; 633 case OPC59_FSQRTS: 634 FPU_EMU_EVCNT_INCR(fsqrt); 635 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 636 fpu_explode(fe, &fe->fe_f1, type, rb); 637 fp = fpu_sqrt(fe); 638 break; 639 case OPC63M_FSEL: 640 FPU_EMU_EVCNT_INCR(fsel); 641 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 642 a = (int *)&fe->fe_fpstate->fpreg[ra]; 643 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 644 /* fra < 0 */ 645 rc = rb; 646 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 647 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 648 sizeof(double)); 649 break; 650 case OPC59_FRES: 651 FPU_EMU_EVCNT_INCR(fpres); 652 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 653 fpu_explode(fe, &fe->fe_f1, type, rb); 654 fp = fpu_sqrt(fe); 655 /* now we've gotta overwrite the dest reg */ 656 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 657 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 658 fpu_div(fe); 659 break; 660 case OPC59_FMULS: 661 FPU_EMU_EVCNT_INCR(fmul); 662 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 663 fpu_explode(fe, &fe->fe_f1, type, ra); 664 fpu_explode(fe, &fe->fe_f2, type, rc); 665 fp = fpu_mul(fe); 666 break; 667 case OPC63M_FRSQRTE: 668 /* Reciprocal sqrt() estimate */ 669 FPU_EMU_EVCNT_INCR(frsqrte); 670 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 671 fpu_explode(fe, &fe->fe_f1, type, rb); 672 fe->fe_f2 = *fp; 673 /* now we've gotta overwrite the dest reg */ 674 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 675 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 676 fpu_div(fe); 677 break; 678 case OPC59_FMSUBS: 679 FPU_EMU_EVCNT_INCR(fmulsub); 680 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 681 fpu_explode(fe, &fe->fe_f1, type, ra); 682 fpu_explode(fe, &fe->fe_f2, type, rc); 683 fp = fpu_mul(fe); 684 fe->fe_f1 = *fp; 685 fpu_explode(fe, &fe->fe_f2, type, rb); 686 fp = fpu_sub(fe); 687 break; 688 case OPC59_FMADDS: 689 FPU_EMU_EVCNT_INCR(fmuladd); 690 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 691 fpu_explode(fe, &fe->fe_f1, type, ra); 692 fpu_explode(fe, &fe->fe_f2, type, rc); 693 fp = fpu_mul(fe); 694 fe->fe_f1 = *fp; 695 fpu_explode(fe, &fe->fe_f2, type, rb); 696 fp = fpu_add(fe); 697 break; 698 case OPC59_FNMSUBS: 699 FPU_EMU_EVCNT_INCR(fnmsub); 700 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 701 fpu_explode(fe, &fe->fe_f1, type, ra); 702 fpu_explode(fe, &fe->fe_f2, type, rc); 703 fp = fpu_mul(fe); 704 fe->fe_f1 = *fp; 705 fpu_explode(fe, &fe->fe_f2, type, rb); 706 fp = fpu_sub(fe); 707 /* Negate */ 708 fp->fp_sign ^= 1; 709 break; 710 case OPC59_FNMADDS: 711 FPU_EMU_EVCNT_INCR(fnmadd); 712 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 713 fpu_explode(fe, &fe->fe_f1, type, ra); 714 fpu_explode(fe, &fe->fe_f2, type, rc); 715 fp = fpu_mul(fe); 716 fe->fe_f1 = *fp; 717 fpu_explode(fe, &fe->fe_f2, type, rb); 718 fp = fpu_add(fe); 719 /* Negate */ 720 fp->fp_sign ^= 1; 721 break; 722 default: 723 return (NOTFPU); 724 break; 725 } 726 } 727 } else { 728 return (NOTFPU); 729 } 730 731 /* 732 * ALU operation is complete. Collapse the result and then check 733 * for exceptions. If we got any, and they are enabled, do not 734 * alter the destination register, just stop with an exception. 735 * Otherwise set new current exceptions and accrue. 736 */ 737 if (fp) 738 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 739 cx = fe->fe_cx; 740 fsr = fe->fe_fpscr; 741 if (cx != 0) { 742 fsr &= ~FPSCR_FX; 743 if ((cx^fsr)&FPSR_EX_MSK) 744 fsr |= FPSCR_FX; 745 mask = fsr & FPSR_EX; 746 mask <<= (25-3); 747 if (cx & mask) 748 fsr |= FPSCR_FEX; 749 if (cx & FPSCR_FPRF) { 750 /* Need to replace CC */ 751 fsr &= ~FPSCR_FPRF; 752 } 753 if (cx & (FPSR_EXOP)) 754 fsr |= FPSCR_VX; 755 fsr |= cx; 756 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 757 } 758 759 if (cond) { 760 cond = fsr & 0xf0000000; 761 /* Isolate condition codes */ 762 cond >>= 28; 763 /* Move fpu condition codes to cr[1] */ 764 tf->cr &= (0x0f000000); 765 tf->cr |= (cond<<24); 766 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 767 } 768 769 if (setcr) { 770 cond = fsr & FPSCR_FPCC; 771 /* Isolate condition codes */ 772 cond <<= 16; 773 /* Move fpu condition codes to cr[1] */ 774 tf->cr &= ~(0xf0000000>>bf); 775 tf->cr |= (cond>>bf); 776 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->cr, cond)); 777 } 778 779 ((int *)&fs->fpscr)[1] = fsr; 780 if (fsr & FPSCR_FEX) 781 return(FPE); 782 return (0); /* success */ 783 } 784
Indexes created Mon Sep 22 21:09:42 GMT 2025