fpu_emu.c revision 1.52
1 /* $NetBSD: fpu_emu.c,v 1.52 2022/09/04 13:18:33 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.52 2022/09/04 13:18:33 rin Exp $"); 80 81 #ifdef _KERNEL_OPT 82 #include "opt_ddb.h" 83 #endif 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/evcnt.h> 88 #include <sys/proc.h> 89 #include <sys/siginfo.h> 90 #include <sys/signal.h> 91 #include <sys/signalvar.h> 92 #include <sys/syslog.h> 93 94 #include <powerpc/instr.h> 95 #include <powerpc/psl.h> 96 97 #include <machine/fpu.h> 98 #include <machine/reg.h> 99 #include <machine/trap.h> 100 101 #include <powerpc/fpu/fpu_emu.h> 102 #include <powerpc/fpu/fpu_extern.h> 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static struct evcnt fpu_emu_ev_##name = \ 106 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 107 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 108 109 #define FPU_EMU_EVCNT_INCR(name) \ 110 fpu_emu_ev_##name.ev_count++ 111 112 FPU_EMU_EVCNT_DECL(stfiwx); 113 FPU_EMU_EVCNT_DECL(fpstore); 114 FPU_EMU_EVCNT_DECL(fpload); 115 FPU_EMU_EVCNT_DECL(fcmpu); 116 FPU_EMU_EVCNT_DECL(frsp); 117 FPU_EMU_EVCNT_DECL(fctiw); 118 FPU_EMU_EVCNT_DECL(fcmpo); 119 FPU_EMU_EVCNT_DECL(mtfsb1); 120 FPU_EMU_EVCNT_DECL(fnegabs); 121 FPU_EMU_EVCNT_DECL(mcrfs); 122 FPU_EMU_EVCNT_DECL(mtfsb0); 123 FPU_EMU_EVCNT_DECL(fmr); 124 FPU_EMU_EVCNT_DECL(mtfsfi); 125 FPU_EMU_EVCNT_DECL(fnabs); 126 FPU_EMU_EVCNT_DECL(fabs); 127 FPU_EMU_EVCNT_DECL(mffs); 128 FPU_EMU_EVCNT_DECL(mtfsf); 129 FPU_EMU_EVCNT_DECL(fctid); 130 FPU_EMU_EVCNT_DECL(fcfid); 131 FPU_EMU_EVCNT_DECL(fdiv); 132 FPU_EMU_EVCNT_DECL(fsub); 133 FPU_EMU_EVCNT_DECL(fadd); 134 FPU_EMU_EVCNT_DECL(fsqrt); 135 FPU_EMU_EVCNT_DECL(fsel); 136 FPU_EMU_EVCNT_DECL(fpres); 137 FPU_EMU_EVCNT_DECL(fmul); 138 FPU_EMU_EVCNT_DECL(frsqrte); 139 FPU_EMU_EVCNT_DECL(fmulsub); 140 FPU_EMU_EVCNT_DECL(fmuladd); 141 FPU_EMU_EVCNT_DECL(fnmsub); 142 FPU_EMU_EVCNT_DECL(fnmadd); 143 144 /* FPSR exception masks */ 145 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 146 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 147 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 148 FPSCR_VXSQRT|FPSCR_VXCVI) 149 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 150 #define FPSR_INV (FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 151 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 152 FPSCR_VXSQRT|FPSCR_VXCVI) 153 #define MCRFS_MASK \ 154 ( \ 155 FPSCR_FX | FPSCR_OX | \ 156 FPSCR_UX | FPSCR_ZX | FPSCR_XX | FPSCR_VXSNAN | \ 157 FPSCR_VXISI | FPSCR_VXIDI | FPSCR_VXZDZ | FPSCR_VXIMZ | \ 158 FPSCR_VXVC | \ 159 FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI \ 160 ) 161 162 #define FR(reg) (fs->fpreg[reg]) 163 164 int fpe_debug = 0; 165 166 #ifdef DDB 167 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 168 #endif 169 170 #ifdef DEBUG 171 /* 172 * Dump a `fpn' structure. 173 */ 174 void 175 fpu_dumpfpn(struct fpn *fp) 176 { 177 static const char *class[] = { 178 "SNAN", "QNAN", "ZERO", "NUM", "INF" 179 }; 180 181 KASSERT(fp != NULL); 182 183 printf("%s %c.%x %x %x %xE%d\n", class[fp->fp_class + 2], 184 fp->fp_sign ? '-' : ' ', 185 fp->fp_mant[0], fp->fp_mant[1], 186 fp->fp_mant[2], fp->fp_mant[3], 187 fp->fp_exp); 188 } 189 #endif 190 191 /* 192 * fpu_execute returns the following error numbers (0 = no error): 193 */ 194 #define FPE 1 /* take a floating point exception */ 195 #define NOTFPU 2 /* not an FPU instruction */ 196 #define FAULT 3 197 198 199 /* 200 * Emulate a floating-point instruction. 201 * Return true if insn is consumed anyway. 202 * Otherwise, the caller must take care of it. 203 */ 204 bool 205 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 206 { 207 struct pcb *pcb; 208 union instr insn; 209 struct fpemu fe; 210 211 KSI_INIT_TRAP(ksi); 212 ksi->ksi_signo = 0; 213 ksi->ksi_addr = (void *)tf->tf_srr0; 214 215 /* initialize insn.is_datasize to tell it is *not* initialized */ 216 fe.fe_fpstate = fpf; 217 fe.fe_cx = 0; 218 219 /* always set this (to avoid a warning) */ 220 221 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 222 #ifdef DEBUG 223 printf("fpu_emulate: fault reading opcode\n"); 224 #endif 225 ksi->ksi_signo = SIGSEGV; 226 ksi->ksi_trap = EXC_ISI; 227 ksi->ksi_code = SEGV_MAPERR; 228 return true; 229 } 230 231 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 232 insn.i_int, (void *)tf->tf_srr0)); 233 234 if ((insn.i_any.i_opcd == OPC_TWI) || 235 ((insn.i_any.i_opcd == OPC_integer_31) && 236 (insn.i_x.i_xo == OPC31_TW))) { 237 /* Check for the two trap insns. */ 238 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 239 ksi->ksi_signo = SIGTRAP; 240 ksi->ksi_trap = EXC_PGM; 241 ksi->ksi_code = TRAP_BRKPT; 242 return true; 243 } 244 switch (fpu_execute(tf, &fe, &insn)) { 245 case 0: 246 success: 247 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 248 tf->tf_srr0 += 4; 249 return true; 250 251 case FPE: 252 pcb = lwp_getpcb(curlwp); 253 if ((pcb->pcb_flags & PSL_FE_PREC) == 0) 254 goto success; 255 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 256 ksi->ksi_signo = SIGFPE; 257 ksi->ksi_trap = EXC_PGM; 258 ksi->ksi_code = fpu_get_fault_code(); 259 return true; 260 261 case FAULT: 262 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 263 ksi->ksi_signo = SIGSEGV; 264 ksi->ksi_trap = EXC_DSI; 265 ksi->ksi_code = SEGV_MAPERR; 266 ksi->ksi_addr = (void *)fe.fe_addr; 267 return true; 268 269 case NOTFPU: 270 default: 271 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 272 #if defined(DDB) && defined(DEBUG) 273 if (fpe_debug & FPE_EX) { 274 printf("fpu_emulate: illegal insn %x at %p:", 275 insn.i_int, (void *) (tf->tf_srr0)); 276 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 277 } 278 #endif 279 return false; 280 } 281 } 282 283 /* 284 * Execute an FPU instruction (one that runs entirely in the FPU; not 285 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 286 * modified to reflect the setting the hardware would have left. 287 * 288 * Note that we do not catch all illegal opcodes, so you can, for instance, 289 * multiply two integers this way. 290 */ 291 int 292 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 293 { 294 struct fpn *fp; 295 union instr instr = *insn; 296 int *a; 297 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; 298 u_int bits; 299 struct fpreg *fs; 300 int i; 301 302 /* Setup work. */ 303 fp = NULL; 304 fs = fe->fe_fpstate; 305 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 306 307 /* 308 * On PowerPC all floating point values are stored in registers 309 * as doubles, even when used for single precision operations. 310 */ 311 type = FTYPE_DBL; 312 cond = instr.i_any.i_rc; 313 setcr = 0; 314 bf = 0; /* XXX gcc */ 315 316 #if defined(DDB) && defined(DEBUG) 317 if (fpe_debug & FPE_EX) { 318 vaddr_t loc = tf->tf_srr0; 319 320 printf("Trying to emulate: %p ", (void *)loc); 321 opc_disasm(loc, instr.i_int); 322 } 323 #endif 324 325 /* 326 * `Decode' and execute instruction. 327 */ 328 329 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 330 instr.i_any.i_opcd == OPC_integer_31) { 331 /* 332 * Handle load/store insns: 333 * 334 * Convert to/from single if needed, calculate addr, 335 * and update index reg if needed. 336 */ 337 vaddr_t addr; 338 size_t size = sizeof(double); 339 int store, update; 340 341 cond = 0; /* ld/st never set condition codes */ 342 343 344 if (instr.i_any.i_opcd == OPC_integer_31) { 345 if (instr.i_x.i_xo == OPC31_STFIWX) { 346 FPU_EMU_EVCNT_INCR(stfiwx); 347 348 /* Store as integer */ 349 ra = instr.i_x.i_ra; 350 rb = instr.i_x.i_rb; 351 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 352 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 353 354 addr = tf->tf_fixreg[rb]; 355 if (ra != 0) 356 addr += tf->tf_fixreg[ra]; 357 rt = instr.i_x.i_rt; 358 a = (int *)&fs->fpreg[rt]; 359 DPRINTF(FPE_INSN, 360 ("fpu_execute: Store INT %x at %p\n", 361 a[1], (void *)addr)); 362 if (copyout(&a[1], (void *)addr, sizeof(int))) { 363 fe->fe_addr = addr; 364 return (FAULT); 365 } 366 return (0); 367 } 368 369 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 370 /* Not an indexed FP load/store op */ 371 return (NOTFPU); 372 373 store = (instr.i_x.i_xo & 0x80); 374 if ((instr.i_x.i_xo & 0x40) == 0) { 375 type = FTYPE_SNG; 376 size = sizeof(float); 377 } 378 update = (instr.i_x.i_xo & 0x20); 379 380 /* calculate EA of load/store */ 381 ra = instr.i_x.i_ra; 382 rb = instr.i_x.i_rb; 383 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 384 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 385 addr = tf->tf_fixreg[rb]; 386 if (ra != 0) 387 addr += tf->tf_fixreg[ra]; 388 rt = instr.i_x.i_rt; 389 } else { 390 store = instr.i_d.i_opcd & 0x4; 391 if ((instr.i_d.i_opcd & 0x2) == 0) { 392 type = FTYPE_SNG; 393 size = sizeof(float); 394 } 395 update = instr.i_d.i_opcd & 0x1; 396 397 /* calculate EA of load/store */ 398 ra = instr.i_d.i_ra; 399 addr = instr.i_d.i_d; 400 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 401 ra, tf->tf_fixreg[ra], addr)); 402 if (ra != 0) 403 addr += tf->tf_fixreg[ra]; 404 rt = instr.i_d.i_rt; 405 } 406 407 if (update && ra == 0) 408 return (NOTFPU); 409 410 if (store) { 411 /* Store */ 412 FPU_EMU_EVCNT_INCR(fpstore); 413 if (type != FTYPE_DBL) { 414 uint64_t buf; 415 416 DPRINTF(FPE_INSN, 417 ("fpu_execute: Store SNG at %p\n", 418 (void *)addr)); 419 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, 420 FR(rt)); 421 fpu_implode(fe, fp, type, &buf); 422 if (copyout(&buf, (void *)addr, size)) { 423 fe->fe_addr = addr; 424 return (FAULT); 425 } 426 } else { 427 DPRINTF(FPE_INSN, 428 ("fpu_execute: Store DBL at %p\n", 429 (void *)addr)); 430 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 431 fe->fe_addr = addr; 432 return (FAULT); 433 } 434 } 435 } else { 436 /* Load */ 437 FPU_EMU_EVCNT_INCR(fpload); 438 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 439 (void *)addr)); 440 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 441 fe->fe_addr = addr; 442 return (FAULT); 443 } 444 if (type != FTYPE_DBL) { 445 fpu_explode(fe, fp = &fe->fe_f1, type, FR(rt)); 446 fpu_implode(fe, fp, FTYPE_DBL, &FR(rt)); 447 } 448 } 449 if (update) 450 tf->tf_fixreg[ra] = addr; 451 /* Complete. */ 452 return (0); 453 #ifdef notyet 454 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 455 /* These are 64-bit extenstions */ 456 return (NOTFPU); 457 #endif 458 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 459 instr.i_any.i_opcd == OPC_dp_fp_63) { 460 461 462 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 463 !(instr.i_a.i_xo & OPC63M_MASK)) { 464 /* Format X */ 465 rt = instr.i_x.i_rt; 466 ra = instr.i_x.i_ra; 467 rb = instr.i_x.i_rb; 468 469 470 /* One of the special opcodes.... */ 471 switch (instr.i_x.i_xo) { 472 case OPC63_FCMPU: 473 FPU_EMU_EVCNT_INCR(fcmpu); 474 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 475 rt >>= 2; 476 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 477 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 478 fpu_compare(fe, 0); 479 /* Make sure we do the condition regs. */ 480 cond = 0; 481 /* N.B.: i_rs is already left shifted by two. */ 482 bf = instr.i_x.i_rs & 0xfc; 483 setcr = 1; 484 break; 485 486 case OPC63_FRSP: 487 /* 488 * Convert to single: 489 * 490 * PowerPC uses this to round a double 491 * precision value to single precision, 492 * but values in registers are always 493 * stored in double precision format. 494 */ 495 FPU_EMU_EVCNT_INCR(frsp); 496 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 497 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, 498 FR(rb)); 499 fpu_implode(fe, fp, FTYPE_SNG, &FR(rt)); 500 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, 501 FR(rt)); 502 type = FTYPE_DBL | FTYPE_FPSCR; 503 break; 504 case OPC63_FCTIW: 505 case OPC63_FCTIWZ: 506 FPU_EMU_EVCNT_INCR(fctiw); 507 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 508 fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb)); 509 type = FTYPE_INT | FTYPE_FPSCR; 510 if (instr.i_x.i_xo == OPC63_FCTIWZ) 511 type |= FTYPE_RD_RZ; 512 break; 513 case OPC63_FCMPO: 514 FPU_EMU_EVCNT_INCR(fcmpo); 515 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 516 rt >>= 2; 517 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 518 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 519 fpu_compare(fe, 1); 520 /* Make sure we do the condition regs. */ 521 cond = 0; 522 /* N.B.: i_rs is already left shifted by two. */ 523 bf = instr.i_x.i_rs & 0xfc; 524 setcr = 1; 525 break; 526 case OPC63_MTFSB1: 527 FPU_EMU_EVCNT_INCR(mtfsb1); 528 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 529 fe->fe_cx = (1 << (31 - rt)) & 530 ~(FPSCR_FEX | FPSCR_VX); 531 break; 532 case OPC63_FNEG: 533 FPU_EMU_EVCNT_INCR(fnegabs); 534 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 535 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 536 sizeof(double)); 537 a = (int *)&fs->fpreg[rt]; 538 *a ^= (1 << 31); 539 break; 540 case OPC63_MCRFS: 541 FPU_EMU_EVCNT_INCR(mcrfs); 542 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 543 cond = 0; 544 rt &= 0x1c; 545 ra &= 0x1c; 546 /* Extract the bits we want */ 547 bits = (fe->fe_fpscr >> (28 - ra)) & 0xf; 548 /* Clear the bits we copied. */ 549 mask = (0xf << (28 - ra)) & MCRFS_MASK; 550 fe->fe_fpscr &= ~mask; 551 /* Now shove them in the right part of cr */ 552 tf->tf_cr &= ~(0xf << (28 - rt)); 553 tf->tf_cr |= bits << (28 - rt); 554 break; 555 case OPC63_MTFSB0: 556 FPU_EMU_EVCNT_INCR(mtfsb0); 557 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 558 fe->fe_fpscr &= ~(1 << (31 - rt)) | 559 (FPSCR_FEX | FPSCR_VX); 560 break; 561 case OPC63_FMR: 562 FPU_EMU_EVCNT_INCR(fmr); 563 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 564 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 565 sizeof(double)); 566 break; 567 case OPC63_MTFSFI: 568 FPU_EMU_EVCNT_INCR(mtfsfi); 569 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 570 rb >>= 1; 571 rt &= 0x1c; /* Already left-shifted 4 */ 572 bits = rb << (28 - rt); 573 mask = 0xf << (28 - rt); 574 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | bits; 575 break; 576 case OPC63_FNABS: 577 FPU_EMU_EVCNT_INCR(fnabs); 578 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 579 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 580 sizeof(double)); 581 a = (int *)&fs->fpreg[rt]; 582 *a |= (1 << 31); 583 break; 584 case OPC63_FABS: 585 FPU_EMU_EVCNT_INCR(fabs); 586 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 587 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 588 sizeof(double)); 589 a = (int *)&fs->fpreg[rt]; 590 *a &= ~(1 << 31); 591 break; 592 case OPC63_MFFS: 593 FPU_EMU_EVCNT_INCR(mffs); 594 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 595 memcpy(&fs->fpreg[rt], &fs->fpscr, 596 sizeof(fs->fpscr)); 597 break; 598 case OPC63_MTFSF: 599 FPU_EMU_EVCNT_INCR(mtfsf); 600 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 601 if ((rt = instr.i_xfl.i_flm) == -1) { 602 mask = -1; 603 } else { 604 mask = 0; 605 /* Convert 1 bit -> 4 bits */ 606 for (i = 0; i < 8; i++) 607 if (rt & (1 << i)) 608 mask |= 609 (0xf << (4 * i)); 610 } 611 a = (int *)&fs->fpreg[rb]; 612 bits = a[1] & mask; 613 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | bits; 614 break; 615 case OPC63_FCTID: 616 case OPC63_FCTIDZ: 617 FPU_EMU_EVCNT_INCR(fctid); 618 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 619 fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb)); 620 type = FTYPE_LNG | FTYPE_FPSCR; 621 if (instr.i_x.i_xo == OPC63_FCTIDZ) 622 type |= FTYPE_RD_RZ; 623 break; 624 case OPC63_FCFID: 625 FPU_EMU_EVCNT_INCR(fcfid); 626 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 627 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_LNG, 628 FR(rb)); 629 type = FTYPE_DBL | FTYPE_FPSCR; 630 break; 631 default: 632 return (NOTFPU); 633 break; 634 } 635 } else { 636 /* Format A */ 637 rt = instr.i_a.i_frt; 638 ra = instr.i_a.i_fra; 639 rb = instr.i_a.i_frb; 640 rc = instr.i_a.i_frc; 641 642 /* 643 * All arithmetic operations work on registers, which 644 * are stored as doubles. 645 */ 646 type = FTYPE_DBL; 647 switch ((unsigned int)instr.i_a.i_xo) { 648 case OPC59_FDIVS: 649 FPU_EMU_EVCNT_INCR(fdiv); 650 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 651 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 652 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 653 fp = fpu_div(fe); 654 break; 655 case OPC59_FSUBS: 656 FPU_EMU_EVCNT_INCR(fsub); 657 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 658 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 659 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 660 fp = fpu_sub(fe); 661 break; 662 case OPC59_FADDS: 663 FPU_EMU_EVCNT_INCR(fadd); 664 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 665 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 666 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 667 fp = fpu_add(fe); 668 break; 669 case OPC59_FSQRTS: 670 FPU_EMU_EVCNT_INCR(fsqrt); 671 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 672 fpu_explode(fe, &fe->fe_f1, type, FR(rb)); 673 fp = fpu_sqrt(fe); 674 break; 675 case OPC63M_FSEL: 676 FPU_EMU_EVCNT_INCR(fsel); 677 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 678 a = (int *)&fe->fe_fpstate->fpreg[ra]; 679 if ((( a[0] & 0x80000000) && 680 ((a[0] & 0x7fffffff) | a[1])) || 681 (( a[0] & 0x7ff00000) && 682 ((a[0] & 0x000fffff) | a[1]))) { 683 /* negative/NaN or NaN */ 684 rc = rb; 685 } 686 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 687 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 688 sizeof(double)); 689 break; 690 case OPC59_FRES: 691 FPU_EMU_EVCNT_INCR(fpres); 692 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 693 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1); 694 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 695 fp = fpu_div(fe); 696 break; 697 case OPC59_FMULS: 698 FPU_EMU_EVCNT_INCR(fmul); 699 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 700 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 701 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 702 fp = fpu_mul(fe); 703 break; 704 case OPC63M_FRSQRTE: 705 /* Reciprocal sqrt() estimate */ 706 FPU_EMU_EVCNT_INCR(frsqrte); 707 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 708 fpu_explode(fe, &fe->fe_f1, type, FR(rb)); 709 fp = fpu_sqrt(fe); 710 fe->fe_f2 = *fp; 711 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1); 712 fp = fpu_div(fe); 713 break; 714 case OPC59_FMSUBS: 715 FPU_EMU_EVCNT_INCR(fmulsub); 716 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 717 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 718 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 719 fp = fpu_mul(fe); 720 fe->fe_f1 = *fp; 721 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 722 fp = fpu_sub(fe); 723 break; 724 case OPC59_FMADDS: 725 FPU_EMU_EVCNT_INCR(fmuladd); 726 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 727 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 728 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 729 fp = fpu_mul(fe); 730 fe->fe_f1 = *fp; 731 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 732 fp = fpu_add(fe); 733 break; 734 case OPC59_FNMSUBS: 735 FPU_EMU_EVCNT_INCR(fnmsub); 736 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 737 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 738 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 739 fp = fpu_mul(fe); 740 fe->fe_f1 = *fp; 741 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 742 fp = fpu_sub(fe); 743 /* Negate */ 744 fp->fp_sign ^= 1; 745 break; 746 case OPC59_FNMADDS: 747 FPU_EMU_EVCNT_INCR(fnmadd); 748 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 749 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 750 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 751 fp = fpu_mul(fe); 752 fe->fe_f1 = *fp; 753 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 754 fp = fpu_add(fe); 755 /* Negate */ 756 fp->fp_sign ^= 1; 757 break; 758 default: 759 return (NOTFPU); 760 break; 761 } 762 763 /* If the instruction was single precision, round */ 764 if (!(instr.i_any.i_opcd & 0x4)) { 765 fpu_implode(fe, fp, FTYPE_SNG | FTYPE_FPSCR, 766 &FR(rt)); 767 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, 768 FR(rt)); 769 } else 770 type |= FTYPE_FPSCR; 771 } 772 } else { 773 return (NOTFPU); 774 } 775 776 /* 777 * ALU operation is complete. Collapse the result and then check 778 * for exceptions. If we got any, and they are enabled, do not 779 * alter the destination register, just stop with an exception. 780 * Otherwise set new current exceptions and accrue. 781 */ 782 if (fp) 783 fpu_implode(fe, fp, type, &FR(rt)); 784 cx = fe->fe_cx; 785 fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX); 786 if (cx != 0) { 787 fsr |= cx; 788 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 789 } 790 if (fsr & FPSR_INV) 791 fsr |= FPSCR_VX; 792 mask = (fsr & FPSR_EX) << (25 - 3); 793 if (fsr & mask) 794 fsr |= FPSCR_FEX; 795 if ((fsr ^ fe->fe_fpscr) & FPSR_EX_MSK) 796 fsr |= FPSCR_FX; 797 798 if (cond) { 799 bits = fsr & 0xf0000000; 800 /* Isolate condition codes */ 801 bits >>= 28; 802 /* Move fpu condition codes to cr[1] */ 803 tf->tf_cr &= ~(0x0f000000); 804 tf->tf_cr |= (bits << 24); 805 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", bits)); 806 } 807 808 if (setcr) { 809 bits = fsr & FPSCR_FPCC; 810 /* Isolate condition codes */ 811 bits <<= 16; 812 /* Move fpu condition codes to cr[bf/4] */ 813 tf->tf_cr &= ~(0xf0000000>>bf); 814 tf->tf_cr |= (bits >> bf); 815 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, bits)); 816 } 817 818 ((int *)&fs->fpscr)[1] = fsr; 819 if (fsr & FPSCR_FEX) 820 return(FPE); 821 return (0); /* success */ 822 } 823
Indexes created Wed Sep 24 05:09:52 GMT 2025