fpu_emu.c revision 1.55
1 /* $NetBSD: fpu_emu.c,v 1.55 2022/09/07 06:53:03 rin Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.55 2022/09/07 06:53:03 rin Exp $"); 80 81 #ifdef _KERNEL_OPT 82 #include "opt_ddb.h" 83 #endif 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/evcnt.h> 88 #include <sys/proc.h> 89 #include <sys/siginfo.h> 90 #include <sys/signal.h> 91 #include <sys/signalvar.h> 92 #include <sys/syslog.h> 93 94 #include <powerpc/instr.h> 95 #include <powerpc/psl.h> 96 97 #include <machine/fpu.h> 98 #include <machine/reg.h> 99 #include <machine/trap.h> 100 101 #include <powerpc/fpu/fpu_emu.h> 102 #include <powerpc/fpu/fpu_extern.h> 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static struct evcnt fpu_emu_ev_##name = \ 106 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 107 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 108 109 #define FPU_EMU_EVCNT_INCR(name) \ 110 fpu_emu_ev_##name.ev_count++ 111 112 FPU_EMU_EVCNT_DECL(stfiwx); 113 FPU_EMU_EVCNT_DECL(fpstore); 114 FPU_EMU_EVCNT_DECL(fpload); 115 FPU_EMU_EVCNT_DECL(fcmpu); 116 FPU_EMU_EVCNT_DECL(frsp); 117 FPU_EMU_EVCNT_DECL(fctiw); 118 FPU_EMU_EVCNT_DECL(fcmpo); 119 FPU_EMU_EVCNT_DECL(mtfsb1); 120 FPU_EMU_EVCNT_DECL(fnegabs); 121 FPU_EMU_EVCNT_DECL(mcrfs); 122 FPU_EMU_EVCNT_DECL(mtfsb0); 123 FPU_EMU_EVCNT_DECL(fmr); 124 FPU_EMU_EVCNT_DECL(mtfsfi); 125 FPU_EMU_EVCNT_DECL(fnabs); 126 FPU_EMU_EVCNT_DECL(fabs); 127 FPU_EMU_EVCNT_DECL(mffs); 128 FPU_EMU_EVCNT_DECL(mtfsf); 129 FPU_EMU_EVCNT_DECL(fctid); 130 FPU_EMU_EVCNT_DECL(fcfid); 131 FPU_EMU_EVCNT_DECL(fdiv); 132 FPU_EMU_EVCNT_DECL(fsub); 133 FPU_EMU_EVCNT_DECL(fadd); 134 FPU_EMU_EVCNT_DECL(fsqrt); 135 FPU_EMU_EVCNT_DECL(fsel); 136 FPU_EMU_EVCNT_DECL(fpres); 137 FPU_EMU_EVCNT_DECL(fmul); 138 FPU_EMU_EVCNT_DECL(frsqrte); 139 FPU_EMU_EVCNT_DECL(fmsub); 140 FPU_EMU_EVCNT_DECL(fmadd); 141 FPU_EMU_EVCNT_DECL(fnmsub); 142 FPU_EMU_EVCNT_DECL(fnmadd); 143 144 /* FPSR exception masks */ 145 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 146 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 147 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 148 FPSCR_VXSQRT|FPSCR_VXCVI) 149 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 150 #define FPSR_INV (FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 151 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 152 FPSCR_VXSQRT|FPSCR_VXCVI) 153 #define MCRFS_MASK \ 154 ( \ 155 FPSCR_FX | FPSCR_OX | \ 156 FPSCR_UX | FPSCR_ZX | FPSCR_XX | FPSCR_VXSNAN | \ 157 FPSCR_VXISI | FPSCR_VXIDI | FPSCR_VXZDZ | FPSCR_VXIMZ | \ 158 FPSCR_VXVC | \ 159 FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI \ 160 ) 161 162 #define FR(reg) (fs->fpreg[reg]) 163 164 int fpe_debug = 0; 165 166 #ifdef DDB 167 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 168 #endif 169 170 static int fpu_execute(struct trapframe *, struct fpemu *, union instr *); 171 172 #ifdef DEBUG 173 /* 174 * Dump a `fpn' structure. 175 */ 176 void 177 fpu_dumpfpn(struct fpn *fp) 178 { 179 static const char *class[] = { 180 "SNAN", "QNAN", "ZERO", "NUM", "INF" 181 }; 182 183 KASSERT(fp != NULL); 184 185 printf("%s %c.%x %x %x %xE%d\n", class[fp->fp_class + 2], 186 fp->fp_sign ? '-' : ' ', 187 fp->fp_mant[0], fp->fp_mant[1], 188 fp->fp_mant[2], fp->fp_mant[3], 189 fp->fp_exp); 190 } 191 #endif 192 193 /* 194 * fpu_execute returns the following error numbers (0 = no error): 195 */ 196 #define FPE 1 /* take a floating point exception */ 197 #define NOTFPU 2 /* not an FPU instruction */ 198 #define FAULT 3 199 200 201 /* 202 * Emulate a floating-point instruction. 203 * Return true if insn is consumed anyway. 204 * Otherwise, the caller must take care of it. 205 */ 206 bool 207 fpu_emulate(struct trapframe *tf, struct fpreg *fpf, ksiginfo_t *ksi) 208 { 209 struct pcb *pcb; 210 union instr insn; 211 struct fpemu fe; 212 213 KSI_INIT_TRAP(ksi); 214 ksi->ksi_signo = 0; 215 ksi->ksi_addr = (void *)tf->tf_srr0; 216 217 /* initialize insn.is_datasize to tell it is *not* initialized */ 218 fe.fe_fpstate = fpf; 219 fe.fe_cx = 0; 220 221 /* always set this (to avoid a warning) */ 222 223 if (copyin((void *) (tf->tf_srr0), &insn.i_int, sizeof (insn.i_int))) { 224 #ifdef DEBUG 225 printf("fpu_emulate: fault reading opcode\n"); 226 #endif 227 ksi->ksi_signo = SIGSEGV; 228 ksi->ksi_trap = EXC_ISI; 229 ksi->ksi_code = SEGV_MAPERR; 230 return true; 231 } 232 233 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 234 insn.i_int, (void *)tf->tf_srr0)); 235 236 if ((insn.i_any.i_opcd == OPC_TWI) || 237 ((insn.i_any.i_opcd == OPC_integer_31) && 238 (insn.i_x.i_xo == OPC31_TW))) { 239 /* Check for the two trap insns. */ 240 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 241 ksi->ksi_signo = SIGTRAP; 242 ksi->ksi_trap = EXC_PGM; 243 ksi->ksi_code = TRAP_BRKPT; 244 return true; 245 } 246 switch (fpu_execute(tf, &fe, &insn)) { 247 case 0: 248 success: 249 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 250 tf->tf_srr0 += 4; 251 return true; 252 253 case FPE: 254 pcb = lwp_getpcb(curlwp); 255 if ((pcb->pcb_flags & PSL_FE_PREC) == 0) 256 goto success; 257 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 258 ksi->ksi_signo = SIGFPE; 259 ksi->ksi_trap = EXC_PGM; 260 ksi->ksi_code = fpu_get_fault_code(); 261 return true; 262 263 case FAULT: 264 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 265 ksi->ksi_signo = SIGSEGV; 266 ksi->ksi_trap = EXC_DSI; 267 ksi->ksi_code = SEGV_MAPERR; 268 ksi->ksi_addr = (void *)fe.fe_addr; 269 return true; 270 271 case NOTFPU: 272 default: 273 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 274 #if defined(DDB) && defined(DEBUG) 275 if (fpe_debug & FPE_EX) { 276 printf("fpu_emulate: illegal insn %x at %p:", 277 insn.i_int, (void *) (tf->tf_srr0)); 278 opc_disasm((vaddr_t)(tf->tf_srr0), insn.i_int); 279 } 280 #endif 281 return false; 282 } 283 } 284 285 /* 286 * Execute an FPU instruction (one that runs entirely in the FPU; not 287 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 288 * modified to reflect the setting the hardware would have left. 289 * 290 * Note that we do not catch all illegal opcodes, so you can, for instance, 291 * multiply two integers this way. 292 */ 293 static int 294 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 295 { 296 struct fpn *fp; 297 union instr instr = *insn; 298 int *a; 299 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; 300 u_int bits; 301 struct fpreg *fs; 302 int i; 303 304 /* Setup work. */ 305 fp = NULL; 306 fs = fe->fe_fpstate; 307 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 308 309 /* 310 * On PowerPC all floating point values are stored in registers 311 * as doubles, even when used for single precision operations. 312 */ 313 type = FTYPE_DBL; 314 cond = instr.i_any.i_rc; 315 setcr = 0; 316 bf = 0; /* XXX gcc */ 317 318 #if defined(DDB) && defined(DEBUG) 319 if (fpe_debug & FPE_EX) { 320 vaddr_t loc = tf->tf_srr0; 321 322 printf("Trying to emulate: %p ", (void *)loc); 323 opc_disasm(loc, instr.i_int); 324 } 325 #endif 326 327 /* 328 * `Decode' and execute instruction. 329 */ 330 331 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 332 instr.i_any.i_opcd == OPC_integer_31) { 333 /* 334 * Handle load/store insns: 335 * 336 * Convert to/from single if needed, calculate addr, 337 * and update index reg if needed. 338 */ 339 vaddr_t addr; 340 size_t size = sizeof(double); 341 int store, update; 342 343 cond = 0; /* ld/st never set condition codes */ 344 345 346 if (instr.i_any.i_opcd == OPC_integer_31) { 347 if (instr.i_x.i_xo == OPC31_STFIWX) { 348 FPU_EMU_EVCNT_INCR(stfiwx); 349 350 /* Store as integer */ 351 ra = instr.i_x.i_ra; 352 rb = instr.i_x.i_rb; 353 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 354 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 355 356 addr = tf->tf_fixreg[rb]; 357 if (ra != 0) 358 addr += tf->tf_fixreg[ra]; 359 rt = instr.i_x.i_rt; 360 a = (int *)&fs->fpreg[rt]; 361 DPRINTF(FPE_INSN, 362 ("fpu_execute: Store INT %x at %p\n", 363 a[1], (void *)addr)); 364 if (copyout(&a[1], (void *)addr, sizeof(int))) { 365 fe->fe_addr = addr; 366 return (FAULT); 367 } 368 return (0); 369 } 370 371 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 372 /* Not an indexed FP load/store op */ 373 return (NOTFPU); 374 375 store = (instr.i_x.i_xo & 0x80); 376 if ((instr.i_x.i_xo & 0x40) == 0) { 377 type = FTYPE_SNG; 378 size = sizeof(float); 379 } 380 update = (instr.i_x.i_xo & 0x20); 381 382 /* calculate EA of load/store */ 383 ra = instr.i_x.i_ra; 384 rb = instr.i_x.i_rb; 385 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 386 ra, tf->tf_fixreg[ra], rb, tf->tf_fixreg[rb])); 387 addr = tf->tf_fixreg[rb]; 388 if (ra != 0) 389 addr += tf->tf_fixreg[ra]; 390 rt = instr.i_x.i_rt; 391 } else { 392 store = instr.i_d.i_opcd & 0x4; 393 if ((instr.i_d.i_opcd & 0x2) == 0) { 394 type = FTYPE_SNG; 395 size = sizeof(float); 396 } 397 update = instr.i_d.i_opcd & 0x1; 398 399 /* calculate EA of load/store */ 400 ra = instr.i_d.i_ra; 401 addr = instr.i_d.i_d; 402 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 403 ra, tf->tf_fixreg[ra], addr)); 404 if (ra != 0) 405 addr += tf->tf_fixreg[ra]; 406 rt = instr.i_d.i_rt; 407 } 408 409 if (update && ra == 0) 410 return (NOTFPU); 411 412 if (store) { 413 /* Store */ 414 FPU_EMU_EVCNT_INCR(fpstore); 415 if (type != FTYPE_DBL) { 416 uint64_t buf; 417 418 DPRINTF(FPE_INSN, 419 ("fpu_execute: Store SNG at %p\n", 420 (void *)addr)); 421 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, 422 FR(rt)); 423 fpu_implode(fe, fp, type, &buf); 424 if (copyout(&buf, (void *)addr, size)) { 425 fe->fe_addr = addr; 426 return (FAULT); 427 } 428 } else { 429 DPRINTF(FPE_INSN, 430 ("fpu_execute: Store DBL at %p\n", 431 (void *)addr)); 432 if (copyout(&fs->fpreg[rt], (void *)addr, size)) { 433 fe->fe_addr = addr; 434 return (FAULT); 435 } 436 } 437 } else { 438 /* Load */ 439 FPU_EMU_EVCNT_INCR(fpload); 440 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 441 (void *)addr)); 442 if (copyin((const void *)addr, &fs->fpreg[rt], size)) { 443 fe->fe_addr = addr; 444 return (FAULT); 445 } 446 if (type != FTYPE_DBL) { 447 fpu_explode(fe, fp = &fe->fe_f1, type, FR(rt)); 448 fpu_implode(fe, fp, FTYPE_DBL, &FR(rt)); 449 } 450 } 451 if (update) 452 tf->tf_fixreg[ra] = addr; 453 /* Complete. */ 454 return (0); 455 #ifdef notyet 456 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 457 /* These are 64-bit extenstions */ 458 return (NOTFPU); 459 #endif 460 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 461 instr.i_any.i_opcd == OPC_dp_fp_63) { 462 463 464 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 465 !(instr.i_a.i_xo & OPC63M_MASK)) { 466 /* Format X */ 467 rt = instr.i_x.i_rt; 468 ra = instr.i_x.i_ra; 469 rb = instr.i_x.i_rb; 470 471 472 /* One of the special opcodes.... */ 473 switch (instr.i_x.i_xo) { 474 case OPC63_FCMPU: 475 FPU_EMU_EVCNT_INCR(fcmpu); 476 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 477 rt >>= 2; 478 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 479 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 480 fpu_compare(fe, 0); 481 /* Make sure we do the condition regs. */ 482 cond = 0; 483 /* N.B.: i_rs is already left shifted by two. */ 484 bf = instr.i_x.i_rs & 0xfc; 485 setcr = 1; 486 break; 487 488 case OPC63_FRSP: 489 /* 490 * Convert to single: 491 * 492 * PowerPC uses this to round a double 493 * precision value to single precision, 494 * but values in registers are always 495 * stored in double precision format. 496 */ 497 FPU_EMU_EVCNT_INCR(frsp); 498 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 499 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, 500 FR(rb)); 501 fpu_implode(fe, fp, FTYPE_SNG, &FR(rt)); 502 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, 503 FR(rt)); 504 type = FTYPE_DBL | FTYPE_FPSCR; 505 break; 506 case OPC63_FCTIW: 507 case OPC63_FCTIWZ: 508 FPU_EMU_EVCNT_INCR(fctiw); 509 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 510 fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb)); 511 type = FTYPE_INT | FTYPE_FPSCR; 512 if (instr.i_x.i_xo == OPC63_FCTIWZ) 513 type |= FTYPE_RD_RZ; 514 break; 515 case OPC63_FCMPO: 516 FPU_EMU_EVCNT_INCR(fcmpo); 517 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 518 rt >>= 2; 519 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 520 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 521 fpu_compare(fe, 1); 522 /* Make sure we do the condition regs. */ 523 cond = 0; 524 /* N.B.: i_rs is already left shifted by two. */ 525 bf = instr.i_x.i_rs & 0xfc; 526 setcr = 1; 527 break; 528 case OPC63_MTFSB1: 529 FPU_EMU_EVCNT_INCR(mtfsb1); 530 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 531 fe->fe_cx = (1 << (31 - rt)) & 532 ~(FPSCR_FEX | FPSCR_VX); 533 break; 534 case OPC63_FNEG: 535 FPU_EMU_EVCNT_INCR(fnegabs); 536 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 537 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 538 sizeof(double)); 539 a = (int *)&fs->fpreg[rt]; 540 *a ^= (1 << 31); 541 break; 542 case OPC63_MCRFS: 543 FPU_EMU_EVCNT_INCR(mcrfs); 544 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 545 cond = 0; 546 rt &= 0x1c; 547 ra &= 0x1c; 548 /* Extract the bits we want */ 549 bits = (fe->fe_fpscr >> (28 - ra)) & 0xf; 550 /* Clear the bits we copied. */ 551 mask = (0xf << (28 - ra)) & MCRFS_MASK; 552 fe->fe_fpscr &= ~mask; 553 /* Now shove them in the right part of cr */ 554 tf->tf_cr &= ~(0xf << (28 - rt)); 555 tf->tf_cr |= bits << (28 - rt); 556 break; 557 case OPC63_MTFSB0: 558 FPU_EMU_EVCNT_INCR(mtfsb0); 559 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 560 fe->fe_fpscr &= ~(1 << (31 - rt)) | 561 (FPSCR_FEX | FPSCR_VX); 562 break; 563 case OPC63_FMR: 564 FPU_EMU_EVCNT_INCR(fmr); 565 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 566 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 567 sizeof(double)); 568 break; 569 case OPC63_MTFSFI: 570 FPU_EMU_EVCNT_INCR(mtfsfi); 571 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 572 rb >>= 1; 573 rt &= 0x1c; /* Already left-shifted 4 */ 574 bits = rb << (28 - rt); 575 mask = 0xf << (28 - rt); 576 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | bits; 577 break; 578 case OPC63_FNABS: 579 FPU_EMU_EVCNT_INCR(fnabs); 580 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 581 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 582 sizeof(double)); 583 a = (int *)&fs->fpreg[rt]; 584 *a |= (1 << 31); 585 break; 586 case OPC63_FABS: 587 FPU_EMU_EVCNT_INCR(fabs); 588 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 589 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 590 sizeof(double)); 591 a = (int *)&fs->fpreg[rt]; 592 *a &= ~(1 << 31); 593 break; 594 case OPC63_MFFS: 595 FPU_EMU_EVCNT_INCR(mffs); 596 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 597 memcpy(&fs->fpreg[rt], &fs->fpscr, 598 sizeof(fs->fpscr)); 599 break; 600 case OPC63_MTFSF: 601 FPU_EMU_EVCNT_INCR(mtfsf); 602 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 603 if ((rt = instr.i_xfl.i_flm) == -1) { 604 mask = -1; 605 } else { 606 mask = 0; 607 /* Convert 1 bit -> 4 bits */ 608 for (i = 0; i < 8; i++) 609 if (rt & (1 << i)) 610 mask |= 611 (0xf << (4 * i)); 612 } 613 a = (int *)&fs->fpreg[rb]; 614 bits = a[1] & mask; 615 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | bits; 616 break; 617 case OPC63_FCTID: 618 case OPC63_FCTIDZ: 619 FPU_EMU_EVCNT_INCR(fctid); 620 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 621 fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb)); 622 type = FTYPE_LNG | FTYPE_FPSCR; 623 if (instr.i_x.i_xo == OPC63_FCTIDZ) 624 type |= FTYPE_RD_RZ; 625 break; 626 case OPC63_FCFID: 627 FPU_EMU_EVCNT_INCR(fcfid); 628 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 629 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_LNG, 630 FR(rb)); 631 type = FTYPE_DBL | FTYPE_FPSCR; 632 break; 633 default: 634 return (NOTFPU); 635 break; 636 } 637 } else { 638 /* Format A */ 639 rt = instr.i_a.i_frt; 640 ra = instr.i_a.i_fra; 641 rb = instr.i_a.i_frb; 642 rc = instr.i_a.i_frc; 643 644 /* 645 * All arithmetic operations work on registers, which 646 * are stored as doubles. 647 */ 648 type = FTYPE_DBL; 649 switch ((unsigned int)instr.i_a.i_xo) { 650 case OPC59_FDIVS: 651 FPU_EMU_EVCNT_INCR(fdiv); 652 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 653 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 654 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 655 fp = fpu_div(fe); 656 break; 657 case OPC59_FSUBS: 658 FPU_EMU_EVCNT_INCR(fsub); 659 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 660 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 661 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 662 fp = fpu_sub(fe); 663 break; 664 case OPC59_FADDS: 665 FPU_EMU_EVCNT_INCR(fadd); 666 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 667 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 668 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 669 fp = fpu_add(fe); 670 break; 671 case OPC59_FSQRTS: 672 FPU_EMU_EVCNT_INCR(fsqrt); 673 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 674 fpu_explode(fe, &fe->fe_f1, type, FR(rb)); 675 fp = fpu_sqrt(fe); 676 break; 677 case OPC63M_FSEL: 678 FPU_EMU_EVCNT_INCR(fsel); 679 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 680 a = (int *)&fe->fe_fpstate->fpreg[ra]; 681 if ((( a[0] & 0x80000000) && 682 ((a[0] & 0x7fffffff) | a[1])) || 683 (( a[0] & 0x7ff00000) && 684 ((a[0] & 0x000fffff) | a[1]))) { 685 /* negative/NaN or NaN */ 686 rc = rb; 687 } 688 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 689 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 690 sizeof(double)); 691 break; 692 case OPC59_FRES: 693 FPU_EMU_EVCNT_INCR(fpres); 694 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 695 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1); 696 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 697 fp = fpu_div(fe); 698 break; 699 case OPC59_FMULS: 700 FPU_EMU_EVCNT_INCR(fmul); 701 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 702 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 703 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 704 fp = fpu_mul(fe); 705 break; 706 case OPC63M_FRSQRTE: 707 /* Reciprocal sqrt() estimate */ 708 FPU_EMU_EVCNT_INCR(frsqrte); 709 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 710 fpu_explode(fe, &fe->fe_f1, type, FR(rb)); 711 fp = fpu_sqrt(fe); 712 fe->fe_f2 = *fp; 713 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1); 714 fp = fpu_div(fe); 715 break; 716 case OPC59_FMSUBS: 717 FPU_EMU_EVCNT_INCR(fmsub); 718 DPRINTF(FPE_INSN, ("fpu_execute: FMSUB\n")); 719 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 720 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 721 fp = fpu_mul(fe); 722 fe->fe_f1 = *fp; 723 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 724 fp = fpu_sub(fe); 725 break; 726 case OPC59_FMADDS: 727 FPU_EMU_EVCNT_INCR(fmadd); 728 DPRINTF(FPE_INSN, ("fpu_execute: FMADD\n")); 729 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 730 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 731 fp = fpu_mul(fe); 732 fe->fe_f1 = *fp; 733 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 734 fp = fpu_add(fe); 735 break; 736 case OPC59_FNMSUBS: 737 FPU_EMU_EVCNT_INCR(fnmsub); 738 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 739 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 740 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 741 fp = fpu_mul(fe); 742 fe->fe_f1 = *fp; 743 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 744 fp = fpu_sub(fe); 745 /* Negate */ 746 fp->fp_sign ^= 1; 747 break; 748 case OPC59_FNMADDS: 749 FPU_EMU_EVCNT_INCR(fnmadd); 750 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 751 fpu_explode(fe, &fe->fe_f1, type, FR(ra)); 752 fpu_explode(fe, &fe->fe_f2, type, FR(rc)); 753 fp = fpu_mul(fe); 754 fe->fe_f1 = *fp; 755 fpu_explode(fe, &fe->fe_f2, type, FR(rb)); 756 fp = fpu_add(fe); 757 /* Negate */ 758 fp->fp_sign ^= 1; 759 break; 760 default: 761 return (NOTFPU); 762 break; 763 } 764 765 /* If the instruction was single precision, round */ 766 if (!(instr.i_any.i_opcd & 0x4)) { 767 fpu_implode(fe, fp, FTYPE_SNG | FTYPE_FPSCR, 768 &FR(rt)); 769 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, 770 FR(rt)); 771 } else 772 type |= FTYPE_FPSCR; 773 } 774 } else { 775 return (NOTFPU); 776 } 777 778 /* 779 * ALU operation is complete. Collapse the result and then check 780 * for exceptions. If we got any, and they are enabled, do not 781 * alter the destination register, just stop with an exception. 782 * Otherwise set new current exceptions and accrue. 783 */ 784 if (fp) 785 fpu_implode(fe, fp, type, &FR(rt)); 786 cx = fe->fe_cx; 787 fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX); 788 if (cx != 0) { 789 fsr |= cx; 790 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 791 } 792 if (fsr & FPSR_INV) 793 fsr |= FPSCR_VX; 794 mask = (fsr & FPSR_EX) << (25 - 3); 795 if (fsr & mask) 796 fsr |= FPSCR_FEX; 797 if ((fsr ^ fe->fe_fpscr) & FPSR_EX_MSK) 798 fsr |= FPSCR_FX; 799 800 if (cond) { 801 bits = fsr & 0xf0000000; 802 /* Isolate condition codes */ 803 bits >>= 28; 804 /* Move fpu condition codes to cr[1] */ 805 tf->tf_cr &= ~(0x0f000000); 806 tf->tf_cr |= (bits << 24); 807 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", bits)); 808 } 809 810 if (setcr) { 811 bits = fsr & FPSCR_FPCC; 812 /* Isolate condition codes */ 813 bits <<= 16; 814 /* Move fpu condition codes to cr[bf/4] */ 815 tf->tf_cr &= ~(0xf0000000>>bf); 816 tf->tf_cr |= (bits >> bf); 817 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->tf_cr, bits)); 818 } 819 820 ((int *)&fs->fpscr)[1] = fsr; 821 if (fsr & FPSCR_FEX) 822 return(FPE); 823 return (0); /* success */ 824 } 825
Indexes created Tue Sep 23 02:09:52 GMT 2025