fpu_emu.c revision 1.8
1 /* $NetBSD: fpu_emu.c,v 1.8 2003/07/15 02:54:43 lukem Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. All advertising materials mentioning features or use of this software 60 * must display the following acknowledgement: 61 * This product includes software developed by the University of 62 * California, Berkeley and its contributors. 63 * 4. Neither the name of the University nor the names of its contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 71 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 72 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 73 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 74 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 75 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 76 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 77 * SUCH DAMAGE. 78 * 79 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.8 2003/07/15 02:54:43 lukem Exp $"); 84 85 #include "opt_ddb.h" 86 87 #include <sys/param.h> 88 #include <sys/proc.h> 89 #include <sys/signal.h> 90 #include <sys/systm.h> 91 #include <sys/syslog.h> 92 #include <sys/signalvar.h> 93 #include <sys/device.h> /* for evcnt */ 94 95 #include <powerpc/instr.h> 96 #include <machine/reg.h> 97 #include <machine/fpu.h> 98 99 #include <powerpc/fpu/fpu_emu.h> 100 #include <powerpc/fpu/fpu_extern.h> 101 102 #define FPU_EMU_EVCNT_DECL(name) \ 103 static struct evcnt fpu_emu_ev_##name = \ 104 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 105 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 106 107 #define FPU_EMU_EVCNT_INCR(name) \ 108 fpu_emu_ev_##name.ev_count++ 109 110 FPU_EMU_EVCNT_DECL(stfiwx); 111 FPU_EMU_EVCNT_DECL(fpstore); 112 FPU_EMU_EVCNT_DECL(fpload); 113 FPU_EMU_EVCNT_DECL(fcmpu); 114 FPU_EMU_EVCNT_DECL(frsp); 115 FPU_EMU_EVCNT_DECL(fctiw); 116 FPU_EMU_EVCNT_DECL(fcmpo); 117 FPU_EMU_EVCNT_DECL(mtfsb1); 118 FPU_EMU_EVCNT_DECL(fnegabs); 119 FPU_EMU_EVCNT_DECL(mcrfs); 120 FPU_EMU_EVCNT_DECL(mtfsb0); 121 FPU_EMU_EVCNT_DECL(fmr); 122 FPU_EMU_EVCNT_DECL(mtfsfi); 123 FPU_EMU_EVCNT_DECL(fnabs); 124 FPU_EMU_EVCNT_DECL(fabs); 125 FPU_EMU_EVCNT_DECL(mffs); 126 FPU_EMU_EVCNT_DECL(mtfsf); 127 FPU_EMU_EVCNT_DECL(fctid); 128 FPU_EMU_EVCNT_DECL(fcfid); 129 FPU_EMU_EVCNT_DECL(fdiv); 130 FPU_EMU_EVCNT_DECL(fsub); 131 FPU_EMU_EVCNT_DECL(fadd); 132 FPU_EMU_EVCNT_DECL(fsqrt); 133 FPU_EMU_EVCNT_DECL(fsel); 134 FPU_EMU_EVCNT_DECL(fpres); 135 FPU_EMU_EVCNT_DECL(fmul); 136 FPU_EMU_EVCNT_DECL(frsqrte); 137 FPU_EMU_EVCNT_DECL(fmulsub); 138 FPU_EMU_EVCNT_DECL(fmuladd); 139 FPU_EMU_EVCNT_DECL(fnmsub); 140 FPU_EMU_EVCNT_DECL(fnmadd); 141 142 /* FPSR exception masks */ 143 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 144 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 145 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 146 FPSCR_VXSQRT|FPSCR_VXCVI) 147 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 148 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 149 150 151 int fpe_debug = 0; 152 153 #ifdef DDB 154 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 155 #endif 156 157 #ifdef DEBUG 158 /* 159 * Dump a `fpn' structure. 160 */ 161 void 162 fpu_dumpfpn(struct fpn *fp) 163 { 164 static char *class[] = { 165 "SNAN", "QNAN", "ZERO", "NUM", "INF" 166 }; 167 168 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 169 fp->fp_sign ? '-' : ' ', 170 fp->fp_mant[0], fp->fp_mant[1], 171 fp->fp_mant[2], fp->fp_mant[3], 172 fp->fp_exp); 173 } 174 #endif 175 176 /* 177 * fpu_execute returns the following error numbers (0 = no error): 178 */ 179 #define FPE 1 /* take a floating point exception */ 180 #define NOTFPU 2 /* not an FPU instruction */ 181 #define FAULT 3 182 183 184 /* 185 * Emulate a floating-point instruction. 186 * Return zero for success, else signal number. 187 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 188 */ 189 int 190 fpu_emulate(struct trapframe *frame, struct fpreg *fpf) 191 { 192 static union instr insn; 193 static struct fpemu fe; 194 static int lastill = 0; 195 int sig; 196 197 /* initialize insn.is_datasize to tell it is *not* initialized */ 198 fe.fe_fpstate = fpf; 199 fe.fe_cx = 0; 200 201 /* always set this (to avoid a warning) */ 202 203 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 204 #ifdef DEBUG 205 printf("fpu_emulate: fault reading opcode\n"); 206 #endif 207 return SIGSEGV; 208 } 209 210 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 211 insn.i_int, (void *)frame->srr0)); 212 213 214 if ((insn.i_any.i_opcd == OPC_TWI) || 215 ((insn.i_any.i_opcd == OPC_integer_31) && 216 (insn.i_x.i_xo == OPC31_TW))) { 217 /* Check for the two trap insns. */ 218 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 219 return (SIGTRAP); 220 } 221 sig = 0; 222 switch (fpu_execute(frame, &fe, &insn)) { 223 case 0: 224 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 225 frame->srr0 += 4; 226 break; 227 228 case FPE: 229 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 230 sig = SIGFPE; 231 break; 232 233 case FAULT: 234 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 235 sig = SIGSEGV; 236 break; 237 238 case NOTFPU: 239 default: 240 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 241 #ifdef DEBUG 242 if (fpe_debug & FPE_EX) { 243 printf("fpu_emulate: illegal insn %x at %p:", 244 insn.i_int, (void *) (frame->srr0)); 245 opc_disasm((vaddr_t)(frame->srr0), insn.i_int); 246 } 247 #endif 248 /* 249 * XXXX retry an illegal insn once due to cache issues. 250 */ 251 if (lastill == frame->srr0) { 252 sig = SIGILL; 253 #ifdef DEBUG 254 if (fpe_debug & FPE_EX) 255 Debugger(); 256 #endif 257 } 258 lastill = frame->srr0; 259 break; 260 } 261 262 return (sig); 263 } 264 265 /* 266 * Execute an FPU instruction (one that runs entirely in the FPU; not 267 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 268 * modified to reflect the setting the hardware would have left. 269 * 270 * Note that we do not catch all illegal opcodes, so you can, for instance, 271 * multiply two integers this way. 272 */ 273 int 274 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 275 { 276 struct fpn *fp; 277 union instr instr = *insn; 278 int *a; 279 vaddr_t addr; 280 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; 281 struct fpreg *fs; 282 283 /* Setup work. */ 284 fp = NULL; 285 fs = fe->fe_fpstate; 286 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 287 288 /* 289 * On PowerPC all floating point values are stored in registers 290 * as doubles, even when used for single precision operations. 291 */ 292 type = FTYPE_DBL; 293 cond = instr.i_any.i_rc; 294 setcr = 0; 295 296 #if defined(DDB) && defined(DEBUG) 297 if (fpe_debug & FPE_EX) { 298 vaddr_t loc = tf->srr0; 299 300 printf("Trying to emulate: %p ", (void *)loc); 301 opc_disasm(loc, instr.i_int); 302 } 303 #endif 304 305 /* 306 * `Decode' and execute instruction. 307 */ 308 309 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 310 instr.i_any.i_opcd == OPC_integer_31) { 311 /* 312 * Handle load/store insns: 313 * 314 * Convert to/from single if needed, calculate addr, 315 * and update index reg if needed. 316 */ 317 double buf; 318 size_t size = sizeof(float); 319 int store, update; 320 321 cond = 0; /* ld/st never set condition codes */ 322 323 324 if (instr.i_any.i_opcd == OPC_integer_31) { 325 if (instr.i_x.i_xo == OPC31_STFIWX) { 326 FPU_EMU_EVCNT_INCR(stfiwx); 327 328 /* Store as integer */ 329 ra = instr.i_x.i_ra; 330 rb = instr.i_x.i_rb; 331 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 332 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 333 334 addr = tf->fixreg[rb]; 335 if (ra != 0) 336 addr += tf->fixreg[ra]; 337 rt = instr.i_x.i_rt; 338 a = (int *)&fs->fpreg[rt]; 339 DPRINTF(FPE_INSN, 340 ("fpu_execute: Store INT %x at %p\n", 341 a[1], (void *)addr)); 342 if (copyout(&a[1], (void *)addr, sizeof(int))) 343 return (FAULT); 344 return (0); 345 } 346 347 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 348 /* Not an indexed FP load/store op */ 349 return (NOTFPU); 350 351 store = (instr.i_x.i_xo & 0x80); 352 if (instr.i_x.i_xo & 0x40) 353 size = sizeof(double); 354 else 355 type = FTYPE_SNG; 356 update = (instr.i_x.i_xo & 0x20); 357 358 /* calculate EA of load/store */ 359 ra = instr.i_x.i_ra; 360 rb = instr.i_x.i_rb; 361 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 362 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 363 addr = tf->fixreg[rb]; 364 if (ra != 0) 365 addr += tf->fixreg[ra]; 366 rt = instr.i_x.i_rt; 367 } else { 368 store = instr.i_d.i_opcd & 0x4; 369 if (instr.i_d.i_opcd & 0x2) 370 size = sizeof(double); 371 else 372 type = FTYPE_SNG; 373 update = instr.i_d.i_opcd & 0x1; 374 375 /* calculate EA of load/store */ 376 ra = instr.i_d.i_ra; 377 addr = instr.i_d.i_d; 378 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 379 ra, tf->fixreg[ra], addr)); 380 if (ra != 0) 381 addr += tf->fixreg[ra]; 382 rt = instr.i_d.i_rt; 383 } 384 385 if (update && ra == 0) 386 return (NOTFPU); 387 388 if (store) { 389 /* Store */ 390 FPU_EMU_EVCNT_INCR(fpstore); 391 if (type != FTYPE_DBL) { 392 DPRINTF(FPE_INSN, 393 ("fpu_execute: Store SNG at %p\n", 394 (void *)addr)); 395 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 396 fpu_implode(fe, fp, type, (void *)&buf); 397 if (copyout(&buf, (void *)addr, size)) 398 return (FAULT); 399 } else { 400 DPRINTF(FPE_INSN, 401 ("fpu_execute: Store DBL at %p\n", 402 (void *)addr)); 403 if (copyout(&fs->fpreg[rt], (void *)addr, size)) 404 return (FAULT); 405 } 406 } else { 407 /* Load */ 408 FPU_EMU_EVCNT_INCR(fpload); 409 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 410 (void *)addr)); 411 if (copyin((const void *)addr, &fs->fpreg[rt], size)) 412 return (FAULT); 413 if (type != FTYPE_DBL) { 414 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 415 fpu_implode(fe, fp, FTYPE_DBL, 416 (u_int *)&fs->fpreg[rt]); 417 } 418 } 419 if (update) 420 tf->fixreg[ra] = addr; 421 /* Complete. */ 422 return (0); 423 #ifdef notyet 424 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 425 /* These are 64-bit extenstions */ 426 return (NOTFPU); 427 #endif 428 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 429 instr.i_any.i_opcd == OPC_dp_fp_63) { 430 431 432 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 433 !(instr.i_a.i_xo & OPC63M_MASK)) { 434 /* Format X */ 435 rt = instr.i_x.i_rt; 436 ra = instr.i_x.i_ra; 437 rb = instr.i_x.i_rb; 438 439 440 /* One of the special opcodes.... */ 441 switch (instr.i_x.i_xo) { 442 case OPC63_FCMPU: 443 FPU_EMU_EVCNT_INCR(fcmpu); 444 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 445 rt >>= 2; 446 fpu_explode(fe, &fe->fe_f1, type, ra); 447 fpu_explode(fe, &fe->fe_f2, type, rb); 448 fpu_compare(fe, 0); 449 /* Make sure we do the condition regs. */ 450 cond = 0; 451 /* N.B.: i_rs is already left shifted by two. */ 452 bf = instr.i_x.i_rs & 0xfc; 453 setcr = 1; 454 break; 455 456 case OPC63_FRSP: 457 /* 458 * Convert to single: 459 * 460 * PowerPC uses this to round a double 461 * precision value to single precision, 462 * but values in registers are always 463 * stored in double precision format. 464 */ 465 FPU_EMU_EVCNT_INCR(frsp); 466 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 467 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 468 fpu_implode(fe, fp, FTYPE_SNG, 469 (u_int *)&fs->fpreg[rt]); 470 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 471 type = FTYPE_DBL; 472 break; 473 case OPC63_FCTIW: 474 case OPC63_FCTIWZ: 475 FPU_EMU_EVCNT_INCR(fctiw); 476 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 477 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 478 type = FTYPE_INT; 479 break; 480 case OPC63_FCMPO: 481 FPU_EMU_EVCNT_INCR(fcmpo); 482 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 483 rt >>= 2; 484 fpu_explode(fe, &fe->fe_f1, type, ra); 485 fpu_explode(fe, &fe->fe_f2, type, rb); 486 fpu_compare(fe, 1); 487 /* Make sure we do the condition regs. */ 488 cond = 0; 489 /* N.B.: i_rs is already left shifted by two. */ 490 bf = instr.i_x.i_rs & 0xfc; 491 setcr = 1; 492 break; 493 case OPC63_MTFSB1: 494 FPU_EMU_EVCNT_INCR(mtfsb1); 495 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 496 fe->fe_fpscr |= 497 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 498 break; 499 case OPC63_FNEG: 500 FPU_EMU_EVCNT_INCR(fnegabs); 501 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 502 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 503 sizeof(double)); 504 a = (int *)&fs->fpreg[rt]; 505 *a ^= (1 << 31); 506 break; 507 case OPC63_MCRFS: 508 FPU_EMU_EVCNT_INCR(mcrfs); 509 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 510 cond = 0; 511 rt &= 0x1c; 512 ra &= 0x1c; 513 /* Extract the bits we want */ 514 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 515 /* Clear the bits we copied. */ 516 fe->fe_cx = 517 (FPSR_EX_MSK | (0xf << (28 - ra))); 518 fe->fe_fpscr &= fe->fe_cx; 519 /* Now shove them in the right part of cr */ 520 tf->cr &= ~(0xf << (28 - rt)); 521 tf->cr |= (mask << (28 - rt)); 522 break; 523 case OPC63_MTFSB0: 524 FPU_EMU_EVCNT_INCR(mtfsb0); 525 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 526 fe->fe_fpscr &= 527 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 528 break; 529 case OPC63_FMR: 530 FPU_EMU_EVCNT_INCR(fmr); 531 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 532 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 533 sizeof(double)); 534 break; 535 case OPC63_MTFSFI: 536 FPU_EMU_EVCNT_INCR(mtfsfi); 537 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 538 rb >>= 1; 539 rt &= 0x1c; /* Already left-shifted 4 */ 540 fe->fe_cx = rb << (28 - rt); 541 mask = 0xf<<(28 - rt); 542 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 543 fe->fe_cx; 544 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 545 break; 546 case OPC63_FNABS: 547 FPU_EMU_EVCNT_INCR(fnabs); 548 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 549 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 550 sizeof(double)); 551 a = (int *)&fs->fpreg[rt]; 552 *a |= (1 << 31); 553 break; 554 case OPC63_FABS: 555 FPU_EMU_EVCNT_INCR(fabs); 556 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 557 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 558 sizeof(double)); 559 a = (int *)&fs->fpreg[rt]; 560 *a &= ~(1 << 31); 561 break; 562 case OPC63_MFFS: 563 FPU_EMU_EVCNT_INCR(mffs); 564 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 565 memcpy(&fs->fpreg[rt], &fs->fpscr, 566 sizeof(fs->fpscr)); 567 break; 568 case OPC63_MTFSF: 569 FPU_EMU_EVCNT_INCR(mtfsf); 570 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 571 if ((rt = instr.i_xfl.i_flm) == -1) 572 mask = -1; 573 else { 574 mask = 0; 575 /* Convert 1 bit -> 4 bits */ 576 for (ra = 0; ra < 8; ra ++) 577 if (rt & (1<<ra)) 578 mask |= (0xf<<(4*ra)); 579 } 580 a = (int *)&fs->fpreg[rt]; 581 fe->fe_cx = mask & a[1]; 582 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 583 (fe->fe_cx); 584 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 585 break; 586 case OPC63_FCTID: 587 case OPC63_FCTIDZ: 588 FPU_EMU_EVCNT_INCR(fctid); 589 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 590 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 591 type = FTYPE_LNG; 592 break; 593 case OPC63_FCFID: 594 FPU_EMU_EVCNT_INCR(fcfid); 595 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 596 type = FTYPE_LNG; 597 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 598 type = FTYPE_DBL; 599 break; 600 default: 601 return (NOTFPU); 602 break; 603 } 604 } else { 605 /* Format A */ 606 rt = instr.i_a.i_frt; 607 ra = instr.i_a.i_fra; 608 rb = instr.i_a.i_frb; 609 rc = instr.i_a.i_frc; 610 611 type = FTYPE_SNG; 612 if (instr.i_any.i_opcd & 0x4) 613 type = FTYPE_DBL; 614 switch ((unsigned int)instr.i_a.i_xo) { 615 case OPC59_FDIVS: 616 FPU_EMU_EVCNT_INCR(fdiv); 617 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 618 fpu_explode(fe, &fe->fe_f1, type, ra); 619 fpu_explode(fe, &fe->fe_f2, type, rb); 620 fp = fpu_div(fe); 621 break; 622 case OPC59_FSUBS: 623 FPU_EMU_EVCNT_INCR(fsub); 624 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 625 fpu_explode(fe, &fe->fe_f1, type, ra); 626 fpu_explode(fe, &fe->fe_f2, type, rb); 627 fp = fpu_sub(fe); 628 break; 629 case OPC59_FADDS: 630 FPU_EMU_EVCNT_INCR(fadd); 631 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 632 fpu_explode(fe, &fe->fe_f1, type, ra); 633 fpu_explode(fe, &fe->fe_f2, type, rb); 634 fp = fpu_add(fe); 635 break; 636 case OPC59_FSQRTS: 637 FPU_EMU_EVCNT_INCR(fsqrt); 638 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 639 fpu_explode(fe, &fe->fe_f1, type, rb); 640 fp = fpu_sqrt(fe); 641 break; 642 case OPC63M_FSEL: 643 FPU_EMU_EVCNT_INCR(fsel); 644 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 645 a = (int *)&fe->fe_fpstate->fpreg[ra]; 646 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 647 /* fra < 0 */ 648 rc = rb; 649 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 650 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 651 sizeof(double)); 652 break; 653 case OPC59_FRES: 654 FPU_EMU_EVCNT_INCR(fpres); 655 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 656 fpu_explode(fe, &fe->fe_f1, type, rb); 657 fp = fpu_sqrt(fe); 658 /* now we've gotta overwrite the dest reg */ 659 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 660 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 661 fpu_div(fe); 662 break; 663 case OPC59_FMULS: 664 FPU_EMU_EVCNT_INCR(fmul); 665 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 666 fpu_explode(fe, &fe->fe_f1, type, ra); 667 fpu_explode(fe, &fe->fe_f2, type, rc); 668 fp = fpu_mul(fe); 669 break; 670 case OPC63M_FRSQRTE: 671 /* Reciprocal sqrt() estimate */ 672 FPU_EMU_EVCNT_INCR(frsqrte); 673 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 674 fpu_explode(fe, &fe->fe_f1, type, rb); 675 fe->fe_f2 = *fp; 676 /* now we've gotta overwrite the dest reg */ 677 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 678 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 679 fpu_div(fe); 680 break; 681 case OPC59_FMSUBS: 682 FPU_EMU_EVCNT_INCR(fmulsub); 683 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 684 fpu_explode(fe, &fe->fe_f1, type, ra); 685 fpu_explode(fe, &fe->fe_f2, type, rc); 686 fp = fpu_mul(fe); 687 fe->fe_f1 = *fp; 688 fpu_explode(fe, &fe->fe_f2, type, rb); 689 fp = fpu_sub(fe); 690 break; 691 case OPC59_FMADDS: 692 FPU_EMU_EVCNT_INCR(fmuladd); 693 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 694 fpu_explode(fe, &fe->fe_f1, type, ra); 695 fpu_explode(fe, &fe->fe_f2, type, rc); 696 fp = fpu_mul(fe); 697 fe->fe_f1 = *fp; 698 fpu_explode(fe, &fe->fe_f2, type, rb); 699 fp = fpu_add(fe); 700 break; 701 case OPC59_FNMSUBS: 702 FPU_EMU_EVCNT_INCR(fnmsub); 703 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 704 fpu_explode(fe, &fe->fe_f1, type, ra); 705 fpu_explode(fe, &fe->fe_f2, type, rc); 706 fp = fpu_mul(fe); 707 fe->fe_f1 = *fp; 708 fpu_explode(fe, &fe->fe_f2, type, rb); 709 fp = fpu_sub(fe); 710 /* Negate */ 711 fp->fp_sign ^= 1; 712 break; 713 case OPC59_FNMADDS: 714 FPU_EMU_EVCNT_INCR(fnmadd); 715 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 716 fpu_explode(fe, &fe->fe_f1, type, ra); 717 fpu_explode(fe, &fe->fe_f2, type, rc); 718 fp = fpu_mul(fe); 719 fe->fe_f1 = *fp; 720 fpu_explode(fe, &fe->fe_f2, type, rb); 721 fp = fpu_add(fe); 722 /* Negate */ 723 fp->fp_sign ^= 1; 724 break; 725 default: 726 return (NOTFPU); 727 break; 728 } 729 } 730 } else { 731 return (NOTFPU); 732 } 733 734 /* 735 * ALU operation is complete. Collapse the result and then check 736 * for exceptions. If we got any, and they are enabled, do not 737 * alter the destination register, just stop with an exception. 738 * Otherwise set new current exceptions and accrue. 739 */ 740 if (fp) 741 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 742 cx = fe->fe_cx; 743 fsr = fe->fe_fpscr; 744 if (cx != 0) { 745 fsr &= ~FPSCR_FX; 746 if ((cx^fsr)&FPSR_EX_MSK) 747 fsr |= FPSCR_FX; 748 mask = fsr & FPSR_EX; 749 mask <<= (25-3); 750 if (cx & mask) 751 fsr |= FPSCR_FEX; 752 if (cx & FPSCR_FPRF) { 753 /* Need to replace CC */ 754 fsr &= ~FPSCR_FPRF; 755 } 756 if (cx & (FPSR_EXOP)) 757 fsr |= FPSCR_VX; 758 fsr |= cx; 759 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 760 } 761 762 if (cond) { 763 cond = fsr & 0xf0000000; 764 /* Isolate condition codes */ 765 cond >>= 28; 766 /* Move fpu condition codes to cr[1] */ 767 tf->cr &= (0x0f000000); 768 tf->cr |= (cond<<24); 769 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 770 } 771 772 if (setcr) { 773 cond = fsr & FPSCR_FPCC; 774 /* Isolate condition codes */ 775 cond <<= 16; 776 /* Move fpu condition codes to cr[1] */ 777 tf->cr &= ~(0xf0000000>>bf); 778 tf->cr |= (cond>>bf); 779 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->cr, cond)); 780 } 781 782 ((int *)&fs->fpscr)[1] = fsr; 783 if (fsr & FPSCR_FEX) 784 return(FPE); 785 return (0); /* success */ 786 } 787
Indexes created Tue Sep 23 07:09:52 GMT 2025