fpu_emu.c revision 1.9
1 /* $NetBSD: fpu_emu.c,v 1.9 2003/08/07 16:29:17 agc Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.9 2003/08/07 16:29:17 agc Exp $"); 80 81 #include "opt_ddb.h" 82 83 #include <sys/param.h> 84 #include <sys/proc.h> 85 #include <sys/signal.h> 86 #include <sys/systm.h> 87 #include <sys/syslog.h> 88 #include <sys/signalvar.h> 89 #include <sys/device.h> /* for evcnt */ 90 91 #include <powerpc/instr.h> 92 #include <machine/reg.h> 93 #include <machine/fpu.h> 94 95 #include <powerpc/fpu/fpu_emu.h> 96 #include <powerpc/fpu/fpu_extern.h> 97 98 #define FPU_EMU_EVCNT_DECL(name) \ 99 static struct evcnt fpu_emu_ev_##name = \ 100 EVCNT_INITIALIZER(EVCNT_TYPE_TRAP, NULL, "fpemu", #name); \ 101 EVCNT_ATTACH_STATIC(fpu_emu_ev_##name) 102 103 #define FPU_EMU_EVCNT_INCR(name) \ 104 fpu_emu_ev_##name.ev_count++ 105 106 FPU_EMU_EVCNT_DECL(stfiwx); 107 FPU_EMU_EVCNT_DECL(fpstore); 108 FPU_EMU_EVCNT_DECL(fpload); 109 FPU_EMU_EVCNT_DECL(fcmpu); 110 FPU_EMU_EVCNT_DECL(frsp); 111 FPU_EMU_EVCNT_DECL(fctiw); 112 FPU_EMU_EVCNT_DECL(fcmpo); 113 FPU_EMU_EVCNT_DECL(mtfsb1); 114 FPU_EMU_EVCNT_DECL(fnegabs); 115 FPU_EMU_EVCNT_DECL(mcrfs); 116 FPU_EMU_EVCNT_DECL(mtfsb0); 117 FPU_EMU_EVCNT_DECL(fmr); 118 FPU_EMU_EVCNT_DECL(mtfsfi); 119 FPU_EMU_EVCNT_DECL(fnabs); 120 FPU_EMU_EVCNT_DECL(fabs); 121 FPU_EMU_EVCNT_DECL(mffs); 122 FPU_EMU_EVCNT_DECL(mtfsf); 123 FPU_EMU_EVCNT_DECL(fctid); 124 FPU_EMU_EVCNT_DECL(fcfid); 125 FPU_EMU_EVCNT_DECL(fdiv); 126 FPU_EMU_EVCNT_DECL(fsub); 127 FPU_EMU_EVCNT_DECL(fadd); 128 FPU_EMU_EVCNT_DECL(fsqrt); 129 FPU_EMU_EVCNT_DECL(fsel); 130 FPU_EMU_EVCNT_DECL(fpres); 131 FPU_EMU_EVCNT_DECL(fmul); 132 FPU_EMU_EVCNT_DECL(frsqrte); 133 FPU_EMU_EVCNT_DECL(fmulsub); 134 FPU_EMU_EVCNT_DECL(fmuladd); 135 FPU_EMU_EVCNT_DECL(fnmsub); 136 FPU_EMU_EVCNT_DECL(fnmadd); 137 138 /* FPSR exception masks */ 139 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 140 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 141 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 142 FPSCR_VXSQRT|FPSCR_VXCVI) 143 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 144 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 145 146 147 int fpe_debug = 0; 148 149 #ifdef DDB 150 extern vaddr_t opc_disasm(vaddr_t loc, int opcode); 151 #endif 152 153 #ifdef DEBUG 154 /* 155 * Dump a `fpn' structure. 156 */ 157 void 158 fpu_dumpfpn(struct fpn *fp) 159 { 160 static char *class[] = { 161 "SNAN", "QNAN", "ZERO", "NUM", "INF" 162 }; 163 164 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 165 fp->fp_sign ? '-' : ' ', 166 fp->fp_mant[0], fp->fp_mant[1], 167 fp->fp_mant[2], fp->fp_mant[3], 168 fp->fp_exp); 169 } 170 #endif 171 172 /* 173 * fpu_execute returns the following error numbers (0 = no error): 174 */ 175 #define FPE 1 /* take a floating point exception */ 176 #define NOTFPU 2 /* not an FPU instruction */ 177 #define FAULT 3 178 179 180 /* 181 * Emulate a floating-point instruction. 182 * Return zero for success, else signal number. 183 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 184 */ 185 int 186 fpu_emulate(struct trapframe *frame, struct fpreg *fpf) 187 { 188 static union instr insn; 189 static struct fpemu fe; 190 static int lastill = 0; 191 int sig; 192 193 /* initialize insn.is_datasize to tell it is *not* initialized */ 194 fe.fe_fpstate = fpf; 195 fe.fe_cx = 0; 196 197 /* always set this (to avoid a warning) */ 198 199 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 200 #ifdef DEBUG 201 printf("fpu_emulate: fault reading opcode\n"); 202 #endif 203 return SIGSEGV; 204 } 205 206 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 207 insn.i_int, (void *)frame->srr0)); 208 209 210 if ((insn.i_any.i_opcd == OPC_TWI) || 211 ((insn.i_any.i_opcd == OPC_integer_31) && 212 (insn.i_x.i_xo == OPC31_TW))) { 213 /* Check for the two trap insns. */ 214 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 215 return (SIGTRAP); 216 } 217 sig = 0; 218 switch (fpu_execute(frame, &fe, &insn)) { 219 case 0: 220 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 221 frame->srr0 += 4; 222 break; 223 224 case FPE: 225 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 226 sig = SIGFPE; 227 break; 228 229 case FAULT: 230 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 231 sig = SIGSEGV; 232 break; 233 234 case NOTFPU: 235 default: 236 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 237 #ifdef DEBUG 238 if (fpe_debug & FPE_EX) { 239 printf("fpu_emulate: illegal insn %x at %p:", 240 insn.i_int, (void *) (frame->srr0)); 241 opc_disasm((vaddr_t)(frame->srr0), insn.i_int); 242 } 243 #endif 244 /* 245 * XXXX retry an illegal insn once due to cache issues. 246 */ 247 if (lastill == frame->srr0) { 248 sig = SIGILL; 249 #ifdef DEBUG 250 if (fpe_debug & FPE_EX) 251 Debugger(); 252 #endif 253 } 254 lastill = frame->srr0; 255 break; 256 } 257 258 return (sig); 259 } 260 261 /* 262 * Execute an FPU instruction (one that runs entirely in the FPU; not 263 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 264 * modified to reflect the setting the hardware would have left. 265 * 266 * Note that we do not catch all illegal opcodes, so you can, for instance, 267 * multiply two integers this way. 268 */ 269 int 270 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 271 { 272 struct fpn *fp; 273 union instr instr = *insn; 274 int *a; 275 vaddr_t addr; 276 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; 277 struct fpreg *fs; 278 279 /* Setup work. */ 280 fp = NULL; 281 fs = fe->fe_fpstate; 282 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 283 284 /* 285 * On PowerPC all floating point values are stored in registers 286 * as doubles, even when used for single precision operations. 287 */ 288 type = FTYPE_DBL; 289 cond = instr.i_any.i_rc; 290 setcr = 0; 291 292 #if defined(DDB) && defined(DEBUG) 293 if (fpe_debug & FPE_EX) { 294 vaddr_t loc = tf->srr0; 295 296 printf("Trying to emulate: %p ", (void *)loc); 297 opc_disasm(loc, instr.i_int); 298 } 299 #endif 300 301 /* 302 * `Decode' and execute instruction. 303 */ 304 305 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 306 instr.i_any.i_opcd == OPC_integer_31) { 307 /* 308 * Handle load/store insns: 309 * 310 * Convert to/from single if needed, calculate addr, 311 * and update index reg if needed. 312 */ 313 double buf; 314 size_t size = sizeof(float); 315 int store, update; 316 317 cond = 0; /* ld/st never set condition codes */ 318 319 320 if (instr.i_any.i_opcd == OPC_integer_31) { 321 if (instr.i_x.i_xo == OPC31_STFIWX) { 322 FPU_EMU_EVCNT_INCR(stfiwx); 323 324 /* Store as integer */ 325 ra = instr.i_x.i_ra; 326 rb = instr.i_x.i_rb; 327 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 328 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 329 330 addr = tf->fixreg[rb]; 331 if (ra != 0) 332 addr += tf->fixreg[ra]; 333 rt = instr.i_x.i_rt; 334 a = (int *)&fs->fpreg[rt]; 335 DPRINTF(FPE_INSN, 336 ("fpu_execute: Store INT %x at %p\n", 337 a[1], (void *)addr)); 338 if (copyout(&a[1], (void *)addr, sizeof(int))) 339 return (FAULT); 340 return (0); 341 } 342 343 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 344 /* Not an indexed FP load/store op */ 345 return (NOTFPU); 346 347 store = (instr.i_x.i_xo & 0x80); 348 if (instr.i_x.i_xo & 0x40) 349 size = sizeof(double); 350 else 351 type = FTYPE_SNG; 352 update = (instr.i_x.i_xo & 0x20); 353 354 /* calculate EA of load/store */ 355 ra = instr.i_x.i_ra; 356 rb = instr.i_x.i_rb; 357 DPRINTF(FPE_INSN, ("reg %d has %lx reg %d has %lx\n", 358 ra, tf->fixreg[ra], rb, tf->fixreg[rb])); 359 addr = tf->fixreg[rb]; 360 if (ra != 0) 361 addr += tf->fixreg[ra]; 362 rt = instr.i_x.i_rt; 363 } else { 364 store = instr.i_d.i_opcd & 0x4; 365 if (instr.i_d.i_opcd & 0x2) 366 size = sizeof(double); 367 else 368 type = FTYPE_SNG; 369 update = instr.i_d.i_opcd & 0x1; 370 371 /* calculate EA of load/store */ 372 ra = instr.i_d.i_ra; 373 addr = instr.i_d.i_d; 374 DPRINTF(FPE_INSN, ("reg %d has %lx displ %lx\n", 375 ra, tf->fixreg[ra], addr)); 376 if (ra != 0) 377 addr += tf->fixreg[ra]; 378 rt = instr.i_d.i_rt; 379 } 380 381 if (update && ra == 0) 382 return (NOTFPU); 383 384 if (store) { 385 /* Store */ 386 FPU_EMU_EVCNT_INCR(fpstore); 387 if (type != FTYPE_DBL) { 388 DPRINTF(FPE_INSN, 389 ("fpu_execute: Store SNG at %p\n", 390 (void *)addr)); 391 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 392 fpu_implode(fe, fp, type, (void *)&buf); 393 if (copyout(&buf, (void *)addr, size)) 394 return (FAULT); 395 } else { 396 DPRINTF(FPE_INSN, 397 ("fpu_execute: Store DBL at %p\n", 398 (void *)addr)); 399 if (copyout(&fs->fpreg[rt], (void *)addr, size)) 400 return (FAULT); 401 } 402 } else { 403 /* Load */ 404 FPU_EMU_EVCNT_INCR(fpload); 405 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 406 (void *)addr)); 407 if (copyin((const void *)addr, &fs->fpreg[rt], size)) 408 return (FAULT); 409 if (type != FTYPE_DBL) { 410 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 411 fpu_implode(fe, fp, FTYPE_DBL, 412 (u_int *)&fs->fpreg[rt]); 413 } 414 } 415 if (update) 416 tf->fixreg[ra] = addr; 417 /* Complete. */ 418 return (0); 419 #ifdef notyet 420 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 421 /* These are 64-bit extenstions */ 422 return (NOTFPU); 423 #endif 424 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 425 instr.i_any.i_opcd == OPC_dp_fp_63) { 426 427 428 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 429 !(instr.i_a.i_xo & OPC63M_MASK)) { 430 /* Format X */ 431 rt = instr.i_x.i_rt; 432 ra = instr.i_x.i_ra; 433 rb = instr.i_x.i_rb; 434 435 436 /* One of the special opcodes.... */ 437 switch (instr.i_x.i_xo) { 438 case OPC63_FCMPU: 439 FPU_EMU_EVCNT_INCR(fcmpu); 440 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 441 rt >>= 2; 442 fpu_explode(fe, &fe->fe_f1, type, ra); 443 fpu_explode(fe, &fe->fe_f2, type, rb); 444 fpu_compare(fe, 0); 445 /* Make sure we do the condition regs. */ 446 cond = 0; 447 /* N.B.: i_rs is already left shifted by two. */ 448 bf = instr.i_x.i_rs & 0xfc; 449 setcr = 1; 450 break; 451 452 case OPC63_FRSP: 453 /* 454 * Convert to single: 455 * 456 * PowerPC uses this to round a double 457 * precision value to single precision, 458 * but values in registers are always 459 * stored in double precision format. 460 */ 461 FPU_EMU_EVCNT_INCR(frsp); 462 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 463 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 464 fpu_implode(fe, fp, FTYPE_SNG, 465 (u_int *)&fs->fpreg[rt]); 466 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 467 type = FTYPE_DBL; 468 break; 469 case OPC63_FCTIW: 470 case OPC63_FCTIWZ: 471 FPU_EMU_EVCNT_INCR(fctiw); 472 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 473 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 474 type = FTYPE_INT; 475 break; 476 case OPC63_FCMPO: 477 FPU_EMU_EVCNT_INCR(fcmpo); 478 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 479 rt >>= 2; 480 fpu_explode(fe, &fe->fe_f1, type, ra); 481 fpu_explode(fe, &fe->fe_f2, type, rb); 482 fpu_compare(fe, 1); 483 /* Make sure we do the condition regs. */ 484 cond = 0; 485 /* N.B.: i_rs is already left shifted by two. */ 486 bf = instr.i_x.i_rs & 0xfc; 487 setcr = 1; 488 break; 489 case OPC63_MTFSB1: 490 FPU_EMU_EVCNT_INCR(mtfsb1); 491 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 492 fe->fe_fpscr |= 493 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 494 break; 495 case OPC63_FNEG: 496 FPU_EMU_EVCNT_INCR(fnegabs); 497 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 498 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 499 sizeof(double)); 500 a = (int *)&fs->fpreg[rt]; 501 *a ^= (1 << 31); 502 break; 503 case OPC63_MCRFS: 504 FPU_EMU_EVCNT_INCR(mcrfs); 505 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 506 cond = 0; 507 rt &= 0x1c; 508 ra &= 0x1c; 509 /* Extract the bits we want */ 510 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 511 /* Clear the bits we copied. */ 512 fe->fe_cx = 513 (FPSR_EX_MSK | (0xf << (28 - ra))); 514 fe->fe_fpscr &= fe->fe_cx; 515 /* Now shove them in the right part of cr */ 516 tf->cr &= ~(0xf << (28 - rt)); 517 tf->cr |= (mask << (28 - rt)); 518 break; 519 case OPC63_MTFSB0: 520 FPU_EMU_EVCNT_INCR(mtfsb0); 521 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 522 fe->fe_fpscr &= 523 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 524 break; 525 case OPC63_FMR: 526 FPU_EMU_EVCNT_INCR(fmr); 527 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 528 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 529 sizeof(double)); 530 break; 531 case OPC63_MTFSFI: 532 FPU_EMU_EVCNT_INCR(mtfsfi); 533 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 534 rb >>= 1; 535 rt &= 0x1c; /* Already left-shifted 4 */ 536 fe->fe_cx = rb << (28 - rt); 537 mask = 0xf<<(28 - rt); 538 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 539 fe->fe_cx; 540 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 541 break; 542 case OPC63_FNABS: 543 FPU_EMU_EVCNT_INCR(fnabs); 544 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 545 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 546 sizeof(double)); 547 a = (int *)&fs->fpreg[rt]; 548 *a |= (1 << 31); 549 break; 550 case OPC63_FABS: 551 FPU_EMU_EVCNT_INCR(fabs); 552 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 553 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 554 sizeof(double)); 555 a = (int *)&fs->fpreg[rt]; 556 *a &= ~(1 << 31); 557 break; 558 case OPC63_MFFS: 559 FPU_EMU_EVCNT_INCR(mffs); 560 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 561 memcpy(&fs->fpreg[rt], &fs->fpscr, 562 sizeof(fs->fpscr)); 563 break; 564 case OPC63_MTFSF: 565 FPU_EMU_EVCNT_INCR(mtfsf); 566 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 567 if ((rt = instr.i_xfl.i_flm) == -1) 568 mask = -1; 569 else { 570 mask = 0; 571 /* Convert 1 bit -> 4 bits */ 572 for (ra = 0; ra < 8; ra ++) 573 if (rt & (1<<ra)) 574 mask |= (0xf<<(4*ra)); 575 } 576 a = (int *)&fs->fpreg[rt]; 577 fe->fe_cx = mask & a[1]; 578 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 579 (fe->fe_cx); 580 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 581 break; 582 case OPC63_FCTID: 583 case OPC63_FCTIDZ: 584 FPU_EMU_EVCNT_INCR(fctid); 585 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 586 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 587 type = FTYPE_LNG; 588 break; 589 case OPC63_FCFID: 590 FPU_EMU_EVCNT_INCR(fcfid); 591 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 592 type = FTYPE_LNG; 593 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 594 type = FTYPE_DBL; 595 break; 596 default: 597 return (NOTFPU); 598 break; 599 } 600 } else { 601 /* Format A */ 602 rt = instr.i_a.i_frt; 603 ra = instr.i_a.i_fra; 604 rb = instr.i_a.i_frb; 605 rc = instr.i_a.i_frc; 606 607 type = FTYPE_SNG; 608 if (instr.i_any.i_opcd & 0x4) 609 type = FTYPE_DBL; 610 switch ((unsigned int)instr.i_a.i_xo) { 611 case OPC59_FDIVS: 612 FPU_EMU_EVCNT_INCR(fdiv); 613 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 614 fpu_explode(fe, &fe->fe_f1, type, ra); 615 fpu_explode(fe, &fe->fe_f2, type, rb); 616 fp = fpu_div(fe); 617 break; 618 case OPC59_FSUBS: 619 FPU_EMU_EVCNT_INCR(fsub); 620 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 621 fpu_explode(fe, &fe->fe_f1, type, ra); 622 fpu_explode(fe, &fe->fe_f2, type, rb); 623 fp = fpu_sub(fe); 624 break; 625 case OPC59_FADDS: 626 FPU_EMU_EVCNT_INCR(fadd); 627 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 628 fpu_explode(fe, &fe->fe_f1, type, ra); 629 fpu_explode(fe, &fe->fe_f2, type, rb); 630 fp = fpu_add(fe); 631 break; 632 case OPC59_FSQRTS: 633 FPU_EMU_EVCNT_INCR(fsqrt); 634 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 635 fpu_explode(fe, &fe->fe_f1, type, rb); 636 fp = fpu_sqrt(fe); 637 break; 638 case OPC63M_FSEL: 639 FPU_EMU_EVCNT_INCR(fsel); 640 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 641 a = (int *)&fe->fe_fpstate->fpreg[ra]; 642 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 643 /* fra < 0 */ 644 rc = rb; 645 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 646 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 647 sizeof(double)); 648 break; 649 case OPC59_FRES: 650 FPU_EMU_EVCNT_INCR(fpres); 651 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 652 fpu_explode(fe, &fe->fe_f1, type, rb); 653 fp = fpu_sqrt(fe); 654 /* now we've gotta overwrite the dest reg */ 655 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 656 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 657 fpu_div(fe); 658 break; 659 case OPC59_FMULS: 660 FPU_EMU_EVCNT_INCR(fmul); 661 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 662 fpu_explode(fe, &fe->fe_f1, type, ra); 663 fpu_explode(fe, &fe->fe_f2, type, rc); 664 fp = fpu_mul(fe); 665 break; 666 case OPC63M_FRSQRTE: 667 /* Reciprocal sqrt() estimate */ 668 FPU_EMU_EVCNT_INCR(frsqrte); 669 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 670 fpu_explode(fe, &fe->fe_f1, type, rb); 671 fe->fe_f2 = *fp; 672 /* now we've gotta overwrite the dest reg */ 673 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 674 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 675 fpu_div(fe); 676 break; 677 case OPC59_FMSUBS: 678 FPU_EMU_EVCNT_INCR(fmulsub); 679 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 680 fpu_explode(fe, &fe->fe_f1, type, ra); 681 fpu_explode(fe, &fe->fe_f2, type, rc); 682 fp = fpu_mul(fe); 683 fe->fe_f1 = *fp; 684 fpu_explode(fe, &fe->fe_f2, type, rb); 685 fp = fpu_sub(fe); 686 break; 687 case OPC59_FMADDS: 688 FPU_EMU_EVCNT_INCR(fmuladd); 689 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 690 fpu_explode(fe, &fe->fe_f1, type, ra); 691 fpu_explode(fe, &fe->fe_f2, type, rc); 692 fp = fpu_mul(fe); 693 fe->fe_f1 = *fp; 694 fpu_explode(fe, &fe->fe_f2, type, rb); 695 fp = fpu_add(fe); 696 break; 697 case OPC59_FNMSUBS: 698 FPU_EMU_EVCNT_INCR(fnmsub); 699 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 700 fpu_explode(fe, &fe->fe_f1, type, ra); 701 fpu_explode(fe, &fe->fe_f2, type, rc); 702 fp = fpu_mul(fe); 703 fe->fe_f1 = *fp; 704 fpu_explode(fe, &fe->fe_f2, type, rb); 705 fp = fpu_sub(fe); 706 /* Negate */ 707 fp->fp_sign ^= 1; 708 break; 709 case OPC59_FNMADDS: 710 FPU_EMU_EVCNT_INCR(fnmadd); 711 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 712 fpu_explode(fe, &fe->fe_f1, type, ra); 713 fpu_explode(fe, &fe->fe_f2, type, rc); 714 fp = fpu_mul(fe); 715 fe->fe_f1 = *fp; 716 fpu_explode(fe, &fe->fe_f2, type, rb); 717 fp = fpu_add(fe); 718 /* Negate */ 719 fp->fp_sign ^= 1; 720 break; 721 default: 722 return (NOTFPU); 723 break; 724 } 725 } 726 } else { 727 return (NOTFPU); 728 } 729 730 /* 731 * ALU operation is complete. Collapse the result and then check 732 * for exceptions. If we got any, and they are enabled, do not 733 * alter the destination register, just stop with an exception. 734 * Otherwise set new current exceptions and accrue. 735 */ 736 if (fp) 737 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 738 cx = fe->fe_cx; 739 fsr = fe->fe_fpscr; 740 if (cx != 0) { 741 fsr &= ~FPSCR_FX; 742 if ((cx^fsr)&FPSR_EX_MSK) 743 fsr |= FPSCR_FX; 744 mask = fsr & FPSR_EX; 745 mask <<= (25-3); 746 if (cx & mask) 747 fsr |= FPSCR_FEX; 748 if (cx & FPSCR_FPRF) { 749 /* Need to replace CC */ 750 fsr &= ~FPSCR_FPRF; 751 } 752 if (cx & (FPSR_EXOP)) 753 fsr |= FPSCR_VX; 754 fsr |= cx; 755 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 756 } 757 758 if (cond) { 759 cond = fsr & 0xf0000000; 760 /* Isolate condition codes */ 761 cond >>= 28; 762 /* Move fpu condition codes to cr[1] */ 763 tf->cr &= (0x0f000000); 764 tf->cr |= (cond<<24); 765 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 766 } 767 768 if (setcr) { 769 cond = fsr & FPSCR_FPCC; 770 /* Isolate condition codes */ 771 cond <<= 16; 772 /* Move fpu condition codes to cr[1] */ 773 tf->cr &= ~(0xf0000000>>bf); 774 tf->cr |= (cond>>bf); 775 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%x) <= %x\n", bf/4, tf->cr, cond)); 776 } 777 778 ((int *)&fs->fpscr)[1] = fsr; 779 if (fsr & FPSCR_FEX) 780 return(FPE); 781 return (0); /* success */ 782 } 783
Indexes created Tue Sep 23 14:10:03 GMT 2025