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4xx_trap_subr.S revision 1.9 
      1 /*	$NetBSD: 4xx_trap_subr.S,v 1.9 2020/07/12 21:16:23 rin Exp $	*/
      2 
      3 /*
      4  * Copyright 2001 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *      This product includes software developed for the NetBSD Project by
     20  *      Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 /* This file provides necessary handlers for 405GP CPU
     39  * It should be included in locore.S after powerpc/ibm4xx/trap_subr.S
     40  */
     41 
     42 	.text
     43 	.globl	_C_LABEL(pitfitwdog),_C_LABEL(pitfitwdogsize)
     44 
     45 	.align 4
     46 _C_LABEL(pitfitwdog):
     47 	sync
     48 	ba	pitint
     49 	.align 4
     50 	sync
     51 	ba	fitint
     52 	.align 4
     53 	sync
     54 	ba	wdoghandler
     55 _C_LABEL(pitfitwdogsize) = .-_C_LABEL(pitfitwdog)
     56 
     57 pithandler:
     58 	IBM405_ERRATA77_SYNC
     59 	rfi
     60 	ba	.	/* Protect against prefetch */
     61 
     62 wdoghandler:
     63 	IBM405_ERRATA77_SYNC
     64 	rfi
     65 	ba	.	/* Protect against prefetch */
     66 
     67 #define	TLBSTK	0x1000
     68 	.lcomm	tlbstack,TLBSTK,4
     69 	.type	tlbstack,@object
     70 
     71 	.text
     72 /* If an unaligned excception (0x600) and DTLB miss exception (0x1100)
     73    occur at the same time, the interrupt vector offsets of the two
     74    exceptions are logically OR'ed together to produce 0x1700.
     75    See PPC405GP Rev D/E Errata item 51 */
     76 
     77 	.globl _C_LABEL(errata51handler),_C_LABEL(errata51size)
     78 _C_LABEL(errata51handler):
     79 	ba	0x1100
     80 _C_LABEL(errata51size) = .-_C_LABEL(errata51handler)
     81 
     82 	.globl _C_LABEL(tlbdmiss4xx),_C_LABEL(tlbdm4size)
     83 _C_LABEL(tlbdmiss4xx):
     84 	ACCESS_PROLOG(CI_TLBMISSSAVE)
     85 	bla	s4xx_miss
     86 _C_LABEL(tlbdm4size) = .-_C_LABEL(tlbdmiss4xx)
     87 
     88 	.globl _C_LABEL(tlbimiss4xx),_C_LABEL(tlbim4size)
     89 _C_LABEL(tlbimiss4xx):
     90 	ACCESS_PROLOG(CI_TLBMISSSAVE)
     91 	bla	s4xx_miss
     92 _C_LABEL(tlbim4size) = .-_C_LABEL(tlbimiss4xx)
     93 
     94 s4xx_miss:
     95 	.globl	_C_LABEL(pmap_tlbmiss)
     96 
     97 	/* If the kernel stack would fault, don't use it. */
     98 	mfpid	%r30
     99 	li	%r31,KERNEL_PID
    100 	mtpid	%r31
    101 	li	%r31,-FRAMELEN
    102 	tlbsx.	%r31,%r31,%r1
    103 	mtpid	%r30
    104 	beq	1f
    105 
    106 	/*
    107 	 * The kernel stack we want to switch to is not in the TLB.
    108 	 * To solve this problem, we will simulate a kernel
    109 	 * fault on the kernel stack and let the miss handler
    110 	 * bring it in, and return from the trap handler.  The
    111 	 * processor will immediately take the original fault,
    112 	 * which we should be able to handle with the now-valid
    113 	 * kernel stack.
    114 	 */
    115 
    116 	/* Switch to tlbstack */
    117 	addi	%r30,%r1,-FRAMELEN
    118 	lis	%r1,tlbstack+TLBSTK-CALLFRAMELEN@ha
    119 	addi	%r1,%r1,tlbstack+TLBSTK-CALLFRAMELEN@l
    120 	stw	%r30,0(%r1)
    121 
    122 	FRAME_SETUP(CI_TLBMISSSAVE)
    123 
    124 	/* Take an explicit fault at (kernelstack,pid) */
    125 	lwz	%r3,FRAMELEN(%r1)
    126 	li	%r4,KERNEL_PID
    127 	bl	_C_LABEL(pmap_tlbmiss)
    128 	/*
    129 	 * We can retry the old fault or switch stacks and
    130 	 * take it now.  It's easier to retry.
    131 	 */
    132 	mr.	%r3,%r3
    133 	beq	trapexit
    134 
    135 	/* kernel stack not in the pmap? we should panic */
    136 	trap
    137 	b	trapagain
    138 1:
    139 	FRAME_SETUP(CI_TLBMISSSAVE)
    140 	li	%r3,EXC_DTMISS
    141 	lwz	%r4,FRAME_EXC(%r1)
    142 	cmpw	%r3,%r4
    143 	lwz	%r3,FRAME_DEAR(%r1)
    144 	beq	2f
    145 	lwz	%r3,FRAME_SRR0(%r1) /* ITMISS case, TLB miss address in SRR0 */
    146 2:
    147 	lwz	%r4,FRAME_PID(%r1)
    148 	bl	_C_LABEL(pmap_tlbmiss)
    149 	mr.	%r3,%r3
    150 	beq	trapexit
    151 
    152 	/* XXX DEBUG -- make sure we're not on tlbstack */
    153 	lis	%r3,tlbstack@ha
    154 	addi	%r3,%r3,tlbstack@l
    155 	sub	%r7,%r1,%r3
    156 	twllei	%r7,TLBSTK
    157 
    158 	/* PTE not found, time to cause a fault */
    159 	b	trapagain
    160