| History log of /src/sys/arch/powerpc/ibm4xx/4xx_trap_subr.S |
| Revision | | Date | Author | Comments |
| 1.10 |
| 12-Sep-2022 |
rin | Make ibm4xx kernels compiled by clang.
As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...
No binary changes for GCC-compiled kernels.
|
| 1.9 |
| 12-Jul-2020 |
rin | Fix comment.
ibm4xx does not use powerpc/powerpc/trap_subr.S, but
powerpc/ibm4xx/trap_subr.S.
|
| 1.8 |
| 01-Mar-2020 |
rin | Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:
https://elinux.org/images/1/1d/Ppc405gp-errata.pdf
This is because stwcx. is split into two pieces in the pipeline.
We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.
It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:
https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140
For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:
http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html
|
| 1.7 |
| 19-May-2011 |
kiyohara | branches: 1.7.56; 1.7.60;
+ Load TLB-miss-address from SRR0, if ITMISS.
+ Remove a white space.
|
| 1.6 |
| 18-Jan-2011 |
matt | Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.
|
| 1.5 |
| 11-Dec-2005 |
christos | branches: 1.5.100; 1.5.104; 1.5.106;
merge ktrace-lwp.
|
| 1.4 |
| 03-Aug-2003 |
eeh | Use %r<n> for register names.
|
| 1.3 |
| 11-Mar-2003 |
hannken | branches: 1.3.2;
Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".
- different set of device control registers.
- non-standard access to the time base.
- 16 byte cache lines.
Approved by: Eduardo Horvath <eeh@netbsd.org>
|
| 1.2 |
| 11-Jul-2002 |
simonb | Clean up some white space niggles.
|
| 1.1 |
| 13-Jun-2001 |
simonb | branches: 1.1.2; 1.1.8; 1.1.16;
Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.
IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.
|
| 1.1.16.1 |
| 16-Jul-2002 |
gehenna | catch up with -current.
|
| 1.1.8.2 |
| 01-Aug-2002 |
nathanw | Catch up to -current.
|
| 1.1.8.1 |
| 13-Jun-2001 |
nathanw | file 4xx_trap_subr.S was added on branch nathanw_sa on 2002-08-01 02:43:00 +0000
|
| 1.1.2.1 |
| 06-Sep-2002 |
jdolecek | sync kqueue branch with HEAD
|
| 1.3.2.3 |
| 21-Sep-2004 |
skrll | Fix the sync with head I botched.
|
| 1.3.2.2 |
| 18-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.3.2.1 |
| 03-Aug-2004 |
skrll | Sync with HEAD
|
| 1.5.106.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.5.104.1 |
| 07-Jan-2011 |
matt | Deal with new powerpc world.
|
| 1.5.100.2 |
| 31-May-2011 |
rmind | sync with head
|
| 1.5.100.1 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.7.60.1 |
| 03-Mar-2020 |
martin | Pull up following revision(s) (requested by rin in ticket #755):
sys/arch/evbppc/conf/std.virtex: revision 1.4
sys/arch/powerpc/powerpc/trap_subr.S: revision 1.81
sys/arch/powerpc/ibm4xx/4xx_trap_subr.S: revision 1.8
sys/arch/evbppc/conf/std.walnut: revision 1.9
common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h: revision 1.7
sys/arch/powerpc/include/asm.h: revision 1.49
common/lib/libc/arch/powerpc/atomic/atomic_cas.S: revision 1.9
sys/arch/powerpc/ibm4xx/trap_subr.S: revision 1.28
sys/arch/powerpc/include/lock.h: revision 1.15
sys/arch/evbppc/conf/std.obs266: revision 1.3
common/lib/libc/arch/powerpc/atomic/atomic_swap.S: revision 1.8
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.61
sys/arch/powerpc/powerpc/lock_stubs.S: revision 1.12
sys/arch/evbppc/conf/std.obs200: revision 1.5
Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:
https://elinux.org/images/1/1d/Ppc405gp-errata.pdf
This is because stwcx. is split into two pieces in the pipeline.
We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.
It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:
https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140
For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:
http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html
|
| 1.7.56.1 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
