intr.h revision 1.3
1 /* $NetBSD: intr.h,v 1.3 2011/02/08 06:28:56 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _BOOKE_INTR_H_ 38 #define _BOOKE_INTR_H_ 39 40 /* Interrupt priority `levels'. */ 41 #define IPL_NONE 0 /* nothing */ 42 #define IPL_SOFTCLOCK 1 /* software clock interrupt */ 43 #define IPL_SOFTBIO 2 /* software block i/o interrupt */ 44 #define IPL_SOFTNET 3 /* software network interrupt */ 45 #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 46 #define IPL_VM 5 /* memory allocation */ 47 #define IPL_SCHED 6 /* clock */ 48 #define IPL_HIGH 7 /* everything */ 49 #define NIPL 8 50 51 /* Interrupt sharing types. */ 52 #define IST_NONE (NIPL+0) /* none */ 53 #define IST_EDGE (NIPL+1) /* edge-triggered */ 54 #define IST_LEVEL (NIPL+2) /* level-triggered active-low */ 55 #define IST_LEVEL_LOW IST_LEVEL 56 #define IST_LEVEL_HIGH (NIPL+3) /* level-triggered active-high */ 57 #define IST_MSI (NIPL+4) /* message signaling interrupt (PCI) */ 58 #define IST_ONCHIP (NIPL+5) /* on-chip device */ 59 #ifdef __INTR_PRIVATE 60 #define IST_MSIGROUP (NIPL+6) /* openpic msi groups */ 61 #define IST_TIMER (NIPL+7) /* openpic timers */ 62 #define IST_IPI (NIPL+8) /* openpic ipi */ 63 #define IST_MI (NIPL+9) /* openpic message */ 64 #define IST_MAX (NIPL+10) 65 #endif 66 67 #define IPI_DST_ALL -2 68 #define IPI_DST_NOTME -1 69 70 #define __HAVE_FAST_SOFTINTS 1 71 72 #ifndef _LOCORE 73 74 void *intr_establish(int, int, int, int (*)(void *), void *); 75 void intr_disestablish(void *); 76 void intr_cpu_init(struct cpu_info *); 77 void intr_init(void); 78 const char * 79 intr_string(int, int); 80 81 void cpu_send_ipi(cpuid_t, uintptr_t); 82 83 void spl0(void); 84 int splraise(int); 85 void splx(int); 86 #ifdef __INTR_NOINLINE 87 int splhigh(void); 88 int splsched(void); 89 int splvm(void); 90 int splsoftserial(void); 91 int splsoftnet(void); 92 int splsoftbio(void); 93 int splsoftclock(void); 94 #endif 95 96 typedef int ipl_t; 97 typedef struct { 98 ipl_t _ipl; 99 } ipl_cookie_t; 100 101 #ifdef __INTR_PRIVATE 102 103 struct intrsw { 104 void *(*intrsw_establish)(int, int, int, int (*)(void *), void *); 105 void (*intrsw_disestablish)(void *); 106 void (*intrsw_cpu_init)(struct cpu_info *); 107 void (*intrsw_init)(void); 108 void (*intrsw_critintr)(struct trapframe *); 109 void (*intrsw_decrintr)(struct trapframe *); 110 void (*intrsw_extintr)(struct trapframe *); 111 void (*intrsw_fitintr)(struct trapframe *); 112 void (*intrsw_wdogintr)(struct trapframe *); 113 int (*intrsw_splraise)(int); 114 void (*intrsw_spl0)(void); 115 void (*intrsw_splx)(int); 116 const char *(*intrsw_string)(int, int); 117 void (*intrsw_send_ipi)(cpuid_t, uintptr_t); 118 #ifdef __HAVE_FAST_SOFTINTS 119 void (*intrsw_softint_init_md)(struct lwp *, u_int, uintptr_t *); 120 void (*intrsw_softint_trigger)(uintptr_t); 121 #endif 122 }; 123 124 extern const struct intrsw *powerpc_intrsw; 125 void softint_fast_dispatch(struct lwp *, int); 126 #endif /* __INTR_PRIVATE */ 127 128 #ifndef __INTR_NOINLINE 129 static inline int 130 splhigh(void) 131 { 132 133 return splraise(IPL_HIGH); 134 } 135 136 static inline int 137 splsched(void) 138 { 139 140 return splraise(IPL_SCHED); 141 } 142 143 static inline int 144 splvm(void) 145 { 146 147 return splraise(IPL_VM); 148 } 149 150 static inline int 151 splsoftserial(void) 152 { 153 154 return splraise(IPL_SOFTSERIAL); 155 } 156 157 static inline int 158 splsoftnet(void) 159 { 160 161 return splraise(IPL_SOFTNET); 162 } 163 164 static inline int 165 splsoftbio(void) 166 { 167 168 return splraise(IPL_SOFTBIO); 169 } 170 171 static inline int 172 splsoftclock(void) 173 { 174 175 return splraise(IPL_SOFTCLOCK); 176 } 177 178 static inline int 179 splraiseipl(ipl_cookie_t icookie) 180 { 181 182 return splraise(icookie._ipl); 183 } 184 185 static inline ipl_cookie_t 186 makeiplcookie(ipl_t ipl) 187 { 188 189 return (ipl_cookie_t){._ipl = ipl}; 190 } 191 #endif /* !__INTR_NOINLINE */ 192 193 #endif /* !_LOCORE */ 194 #endif /* !_BOOKE_INTR_H_ */ 195
Indexes created Tue Sep 23 21:09:50 GMT 2025