intr.h revision 1.4
1 /* $NetBSD: intr.h,v 1.4 2011/06/05 16:52:25 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef _BOOKE_INTR_H_ 38 #define _BOOKE_INTR_H_ 39 40 /* Interrupt priority `levels'. */ 41 #define IPL_NONE 0 /* nothing */ 42 #define IPL_SOFTCLOCK 1 /* software clock interrupt */ 43 #define IPL_SOFTBIO 2 /* software block i/o interrupt */ 44 #define IPL_SOFTNET 3 /* software network interrupt */ 45 #define IPL_SOFTSERIAL 4 /* software serial interrupt */ 46 #define IPL_VM 5 /* memory allocation */ 47 #define IPL_SCHED 6 /* clock */ 48 #define IPL_HIGH 7 /* everything */ 49 #define NIPL 8 50 51 /* Interrupt sharing types. */ 52 #define IST_NONE (NIPL+0) /* none */ 53 #define IST_EDGE (NIPL+1) /* edge-triggered */ 54 #define IST_LEVEL (NIPL+2) /* level-triggered active-low */ 55 #define IST_LEVEL_LOW IST_LEVEL 56 #define IST_LEVEL_HIGH (NIPL+3) /* level-triggered active-high */ 57 #define IST_MSI (NIPL+4) /* message signaling interrupt (PCI) */ 58 #define IST_ONCHIP (NIPL+5) /* on-chip device */ 59 #ifdef __INTR_PRIVATE 60 #define IST_MSIGROUP (NIPL+6) /* openpic msi groups */ 61 #define IST_TIMER (NIPL+7) /* openpic timers */ 62 #define IST_IPI (NIPL+8) /* openpic ipi */ 63 #define IST_MI (NIPL+9) /* openpic message */ 64 #define IST_MAX (NIPL+10) 65 #endif 66 67 #define IPI_DST_ALL ((cpuid_t)-2) 68 #define IPI_DST_NOTME ((cpuid_t)-1) 69 70 #define IPI_NOMESG 0x0000 71 #define IPI_HALT 0x0001 72 #define IPI_XCALL 0x0002 73 #define IPI_KPREEMPT 0x0004 74 #define IPI_TLB1SYNC 0x0008 75 76 #define __HAVE_FAST_SOFTINTS 1 77 #define SOFTINT_KPREEMPT SOFTINT_COUNT 78 79 #ifndef _LOCORE 80 81 void *intr_establish(int, int, int, int (*)(void *), void *); 82 void intr_disestablish(void *); 83 void intr_cpu_attach(struct cpu_info *); 84 void intr_cpu_hatch(struct cpu_info *); 85 void intr_init(void); 86 const char * 87 intr_string(int, int); 88 89 void cpu_send_ipi(cpuid_t, uint32_t); 90 91 void spl0(void); 92 int splraise(int); 93 void splx(int); 94 #ifdef __INTR_NOINLINE 95 int splhigh(void); 96 int splsched(void); 97 int splvm(void); 98 int splsoftserial(void); 99 int splsoftnet(void); 100 int splsoftbio(void); 101 int splsoftclock(void); 102 #endif 103 104 typedef int ipl_t; 105 typedef struct { 106 ipl_t _ipl; 107 } ipl_cookie_t; 108 109 #ifdef __INTR_PRIVATE 110 111 struct intrsw { 112 void *(*intrsw_establish)(int, int, int, int (*)(void *), void *); 113 void (*intrsw_disestablish)(void *); 114 void (*intrsw_cpu_attach)(struct cpu_info *); 115 void (*intrsw_cpu_hatch)(struct cpu_info *); 116 void (*intrsw_cpu_send_ipi)(cpuid_t, uint32_t); 117 void (*intrsw_init)(void); 118 void (*intrsw_critintr)(struct trapframe *); 119 void (*intrsw_decrintr)(struct trapframe *); 120 void (*intrsw_extintr)(struct trapframe *); 121 void (*intrsw_fitintr)(struct trapframe *); 122 void (*intrsw_wdogintr)(struct trapframe *); 123 int (*intrsw_splraise)(int); 124 void (*intrsw_spl0)(void); 125 void (*intrsw_splx)(int); 126 const char *(*intrsw_string)(int, int); 127 #ifdef __HAVE_FAST_SOFTINTS 128 void (*intrsw_softint_init_md)(struct lwp *, u_int, uintptr_t *); 129 void (*intrsw_softint_trigger)(uintptr_t); 130 #endif 131 }; 132 133 extern const struct intrsw *powerpc_intrsw; 134 void softint_fast_dispatch(struct lwp *, int); 135 #endif /* __INTR_PRIVATE */ 136 137 #ifndef __INTR_NOINLINE 138 static inline int 139 splhigh(void) 140 { 141 142 return splraise(IPL_HIGH); 143 } 144 145 static inline int 146 splsched(void) 147 { 148 149 return splraise(IPL_SCHED); 150 } 151 152 static inline int 153 splvm(void) 154 { 155 156 return splraise(IPL_VM); 157 } 158 159 static inline int 160 splsoftserial(void) 161 { 162 163 return splraise(IPL_SOFTSERIAL); 164 } 165 166 static inline int 167 splsoftnet(void) 168 { 169 170 return splraise(IPL_SOFTNET); 171 } 172 173 static inline int 174 splsoftbio(void) 175 { 176 177 return splraise(IPL_SOFTBIO); 178 } 179 180 static inline int 181 splsoftclock(void) 182 { 183 184 return splraise(IPL_SOFTCLOCK); 185 } 186 187 static inline int 188 splraiseipl(ipl_cookie_t icookie) 189 { 190 191 return splraise(icookie._ipl); 192 } 193 194 static inline ipl_cookie_t 195 makeiplcookie(ipl_t ipl) 196 { 197 198 return (ipl_cookie_t){._ipl = ipl}; 199 } 200 #endif /* !__INTR_NOINLINE */ 201 202 #endif /* !_LOCORE */ 203 #endif /* !_BOOKE_INTR_H_ */ 204
Indexes created Wed Sep 24 05:09:52 GMT 2025