cpu.h revision 1.1 1 1.1 ws /* $NetBSD: cpu.h,v 1.1 1996/09/30 16:34:21 ws Exp $ */
2 1.1 ws
3 1.1 ws /*
4 1.1 ws * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 1.1 ws * Copyright (C) 1995, 1996 TooLs GmbH.
6 1.1 ws * All rights reserved.
7 1.1 ws *
8 1.1 ws * Redistribution and use in source and binary forms, with or without
9 1.1 ws * modification, are permitted provided that the following conditions
10 1.1 ws * are met:
11 1.1 ws * 1. Redistributions of source code must retain the above copyright
12 1.1 ws * notice, this list of conditions and the following disclaimer.
13 1.1 ws * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 ws * notice, this list of conditions and the following disclaimer in the
15 1.1 ws * documentation and/or other materials provided with the distribution.
16 1.1 ws * 3. All advertising materials mentioning features or use of this software
17 1.1 ws * must display the following acknowledgement:
18 1.1 ws * This product includes software developed by TooLs GmbH.
19 1.1 ws * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 1.1 ws * derived from this software without specific prior written permission.
21 1.1 ws *
22 1.1 ws * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 1.1 ws * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 ws * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 ws * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 1.1 ws * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 1.1 ws * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 1.1 ws * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 1.1 ws * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 1.1 ws * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 1.1 ws * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 ws */
33 1.1 ws #ifndef _MACHINE_CPU_H_
34 1.1 ws #define _MACHINE_CPU_H_
35 1.1 ws
36 1.1 ws #include <machine/frame.h>
37 1.1 ws
38 1.1 ws struct machvec {
39 1.1 ws void (*splx) __P((int));
40 1.1 ws void (*irq_establish) __P((int, int, void (*)(void *), void *));
41 1.1 ws };
42 1.1 ws extern struct machvec machine_interface;
43 1.1 ws
44 1.1 ws #include <machine/psl.h>
45 1.1 ws
46 1.1 ws #define irq_establish(irq, level, handler, arg) \
47 1.1 ws ((*machine_interface.irq_establish)((irq), (level), (handler), (arg)))
48 1.1 ws
49 1.1 ws #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
50 1.1 ws #define CLKF_BASEPRI(frame) ((frame)->pri == 0)
51 1.1 ws #define CLKF_PC(frame) ((frame)->srr0)
52 1.1 ws #define CLKF_INTR(frame) ((frame)->depth != 0)
53 1.1 ws
54 1.1 ws #define cpu_swapout(p)
55 1.1 ws #define cpu_wait(p)
56 1.1 ws
57 1.1 ws extern void delay __P((unsigned));
58 1.1 ws #define DELAY(n) delay(n)
59 1.1 ws
60 1.1 ws extern volatile int want_resched;
61 1.1 ws extern volatile int astpending;
62 1.1 ws
63 1.1 ws #define need_resched() (want_resched = 1, astpending = 1)
64 1.1 ws #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1)
65 1.1 ws #define signotify(p) (astpending = 1)
66 1.1 ws
67 1.1 ws #define CACHELINESIZE 32 /* For now XXX */
68 1.1 ws
69 1.1 ws extern __inline void
70 1.1 ws syncicache(from, len)
71 1.1 ws void *from;
72 1.1 ws int len;
73 1.1 ws {
74 1.1 ws int l = len;
75 1.1 ws void *p = from;
76 1.1 ws
77 1.1 ws do {
78 1.1 ws asm volatile ("dcbst 0,%0" :: "r"(p));
79 1.1 ws p += CACHELINESIZE;
80 1.1 ws } while ((l -= CACHELINESIZE) > 0);
81 1.1 ws asm volatile ("sync");
82 1.1 ws do {
83 1.1 ws asm volatile ("icbi 0,%0" :: "r"(from));
84 1.1 ws from += CACHELINESIZE;
85 1.1 ws } while ((len -= CACHELINESIZE) > 0);
86 1.1 ws asm volatile ("isync");
87 1.1 ws }
88 1.1 ws
89 1.1 ws extern char *bootpath;
90 1.1 ws
91 1.1 ws #endif /* _MACHINE_CPU_H_ */
92