cpu.h revision 1.10.6.4 1 1.10.6.4 thorpej /* $NetBSD: cpu.h,v 1.10.6.4 2001/12/08 08:22:43 thorpej Exp $ */
2 1.10.6.2 briggs
3 1.10.6.2 briggs /*
4 1.10.6.2 briggs * Copyright (C) 1999 Wolfgang Solfrank.
5 1.10.6.2 briggs * Copyright (C) 1999 TooLs GmbH.
6 1.10.6.2 briggs * Copyright (C) 1995-1997 Wolfgang Solfrank.
7 1.10.6.2 briggs * Copyright (C) 1995-1997 TooLs GmbH.
8 1.10.6.2 briggs * All rights reserved.
9 1.10.6.2 briggs *
10 1.10.6.2 briggs * Redistribution and use in source and binary forms, with or without
11 1.10.6.2 briggs * modification, are permitted provided that the following conditions
12 1.10.6.2 briggs * are met:
13 1.10.6.2 briggs * 1. Redistributions of source code must retain the above copyright
14 1.10.6.2 briggs * notice, this list of conditions and the following disclaimer.
15 1.10.6.2 briggs * 2. Redistributions in binary form must reproduce the above copyright
16 1.10.6.2 briggs * notice, this list of conditions and the following disclaimer in the
17 1.10.6.2 briggs * documentation and/or other materials provided with the distribution.
18 1.10.6.2 briggs * 3. All advertising materials mentioning features or use of this software
19 1.10.6.2 briggs * must display the following acknowledgement:
20 1.10.6.2 briggs * This product includes software developed by TooLs GmbH.
21 1.10.6.2 briggs * 4. The name of TooLs GmbH may not be used to endorse or promote products
22 1.10.6.2 briggs * derived from this software without specific prior written permission.
23 1.10.6.2 briggs *
24 1.10.6.2 briggs * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25 1.10.6.2 briggs * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 1.10.6.2 briggs * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 1.10.6.2 briggs * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 1.10.6.2 briggs * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 1.10.6.2 briggs * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 1.10.6.2 briggs * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 1.10.6.2 briggs * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 1.10.6.2 briggs * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 1.10.6.2 briggs * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 1.10.6.2 briggs */
35 1.10.6.2 briggs #ifndef _POWERPC_CPU_H_
36 1.10.6.2 briggs #define _POWERPC_CPU_H_
37 1.10.6.2 briggs
38 1.10.6.2 briggs #if defined(_KERNEL_OPT)
39 1.10.6.2 briggs #include "opt_lockdebug.h"
40 1.10.6.2 briggs #include "opt_multiprocessor.h"
41 1.10.6.2 briggs #endif
42 1.10.6.2 briggs
43 1.10.6.2 briggs #include <sys/device.h>
44 1.10.6.2 briggs #include <machine/frame.h>
45 1.10.6.2 briggs #include <machine/psl.h>
46 1.10.6.2 briggs #include <machine/intr.h>
47 1.10.6.2 briggs
48 1.10.6.2 briggs #ifdef _KERNEL
49 1.10.6.2 briggs #include <sys/sched.h>
50 1.10.6.2 briggs struct cpu_info {
51 1.10.6.2 briggs struct schedstate_percpu ci_schedstate; /* scheduler state */
52 1.10.6.2 briggs #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
53 1.10.6.2 briggs u_long ci_spin_locks; /* # of spin locks held */
54 1.10.6.2 briggs u_long ci_simple_locks; /* # of simple locks held */
55 1.10.6.2 briggs #endif
56 1.10.6.2 briggs struct device *ci_dev; /* device of corresponding cpu */
57 1.10.6.2 briggs struct lwp *ci_curproc; /* current owner of the processor */
58 1.10.6.2 briggs
59 1.10.6.2 briggs struct pcb *ci_curpcb;
60 1.10.6.2 briggs struct pmap *ci_curpm;
61 1.10.6.2 briggs struct lwp *ci_fpuproc;
62 1.10.6.2 briggs struct pcb *ci_idle_pcb; /* PA of our idle pcb */
63 1.10.6.2 briggs int ci_cpuid;
64 1.10.6.2 briggs
65 1.10.6.2 briggs int ci_astpending;
66 1.10.6.2 briggs int ci_want_resched;
67 1.10.6.2 briggs u_long ci_lasttb;
68 1.10.6.2 briggs int ci_tickspending;
69 1.10.6.2 briggs int ci_cpl;
70 1.10.6.2 briggs int ci_ipending;
71 1.10.6.2 briggs int ci_intrdepth;
72 1.10.6.2 briggs char *ci_intstk;
73 1.10.6.2 briggs char *ci_spillstk;
74 1.10.6.2 briggs int ci_tempsave[8];
75 1.10.6.2 briggs int ci_ddbsave[8];
76 1.10.6.2 briggs int ci_ipkdbsave[8];
77 1.10.6.2 briggs int ci_disisave[4];
78 1.10.6.2 briggs struct evcnt ci_ev_traps; /* calls to trap() */
79 1.10.6.2 briggs struct evcnt ci_ev_kdsi; /* kernel DSI traps */
80 1.10.6.2 briggs struct evcnt ci_ev_udsi; /* user DSI traps */
81 1.10.6.2 briggs struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
82 1.10.6.2 briggs struct evcnt ci_ev_isi; /* user ISI traps */
83 1.10.6.2 briggs struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
84 1.10.6.2 briggs struct evcnt ci_ev_pgm; /* user PGM traps */
85 1.10.6.2 briggs struct evcnt ci_ev_fpu; /* FPU traps */
86 1.10.6.2 briggs struct evcnt ci_ev_fpusw; /* FPU context switch */
87 1.10.6.2 briggs struct evcnt ci_ev_ali; /* Alignment traps */
88 1.10.6.2 briggs struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
89 1.10.6.2 briggs struct evcnt ci_ev_scalls; /* system call traps */
90 1.10.6.2 briggs struct evcnt ci_ev_vec; /* Altivec traps */
91 1.10.6.2 briggs struct evcnt ci_ev_vecsw; /* Altivec context switches */
92 1.10.6.2 briggs };
93 1.10.6.2 briggs
94 1.10.6.2 briggs #ifdef MULTIPROCESSOR
95 1.10.6.2 briggs static __inline int
96 1.10.6.2 briggs cpu_number()
97 1.10.6.2 briggs {
98 1.10.6.2 briggs int pir;
99 1.10.6.2 briggs
100 1.10.6.2 briggs asm ("mfspr %0,1023" : "=r"(pir));
101 1.10.6.2 briggs return pir;
102 1.10.6.2 briggs }
103 1.10.6.2 briggs
104 1.10.6.2 briggs static __inline struct cpu_info *
105 1.10.6.2 briggs curcpu()
106 1.10.6.2 briggs {
107 1.10.6.2 briggs struct cpu_info *ci;
108 1.10.6.2 briggs
109 1.10.6.2 briggs asm volatile ("mfsprg %0,0" : "=r"(ci));
110 1.10.6.2 briggs return ci;
111 1.10.6.2 briggs }
112 1.10.6.2 briggs
113 1.10.6.2 briggs extern struct cpu_info cpu_info[];
114 1.10.6.2 briggs
115 1.10.6.2 briggs #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
116 1.10.6.2 briggs #define curproc curcpu()->ci_curproc
117 1.10.6.2 briggs #define fpuproc curcpu()->ci_fpuproc
118 1.10.6.2 briggs #define curpcb curcpu()->ci_curpcb
119 1.10.6.2 briggs #define curpm curcpu()->ci_curpm
120 1.10.6.2 briggs #define want_resched curcpu()->ci_want_resched
121 1.10.6.2 briggs #define astpending curcpu()->ci_astpending
122 1.10.6.2 briggs #define intr_depth curcpu()->ci_intrdepth
123 1.10.6.2 briggs
124 1.10.6.2 briggs #else
125 1.10.6.2 briggs extern struct cpu_info cpu_info_store;
126 1.10.6.2 briggs extern volatile int want_resched;
127 1.10.6.2 briggs extern volatile int astpending;
128 1.10.6.2 briggs extern volatile int intr_depth;
129 1.10.6.2 briggs
130 1.10.6.2 briggs #define curcpu() (&cpu_info_store)
131 1.10.6.2 briggs #define cpu_number() 0
132 1.10.6.2 briggs
133 1.10.6.2 briggs #endif /* MULTIPROCESSOR */
134 1.10.6.2 briggs
135 1.10.6.2 briggs #define ppc_cpuid(ci) ((ci)->ci_cpuid)
136 1.10.6.2 briggs
137 1.10.6.2 briggs #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
138 1.10.6.2 briggs #define CLKF_BASEPRI(frame) ((frame)->pri == 0)
139 1.10.6.2 briggs #define CLKF_PC(frame) ((frame)->srr0)
140 1.10.6.2 briggs #define CLKF_INTR(frame) ((frame)->depth > 0)
141 1.10.6.2 briggs
142 1.10.6.3 briggs #define LWP_PC(l) (trapframe(l)->srr0)
143 1.10.6.2 briggs
144 1.10.6.2 briggs #define cpu_swapout(p)
145 1.10.6.2 briggs #define cpu_wait(p)
146 1.10.6.4 thorpej #define cpu_proc_fork(p1, p2)
147 1.10.6.2 briggs
148 1.10.6.2 briggs extern int powersave;
149 1.10.6.2 briggs extern int cpu_timebase;
150 1.10.6.2 briggs extern int cpu_printfataltraps;
151 1.10.6.2 briggs
152 1.10.6.2 briggs extern struct cpu_info *cpu_attach_common(struct device *, int);
153 1.10.6.2 briggs extern void cpu_identify(char *, size_t);
154 1.10.6.2 briggs extern void delay (unsigned int);
155 1.10.6.2 briggs #define DELAY(n) delay(n)
156 1.10.6.2 briggs
157 1.10.6.2 briggs #define need_resched(ci) (want_resched = 1, astpending = 1)
158 1.10.6.2 briggs #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1)
159 1.10.6.2 briggs #define signotify(p) (astpending = 1)
160 1.10.6.2 briggs
161 1.10.6.2 briggs #endif /* _KERNEL */
162 1.10.6.2 briggs
163 1.10.6.2 briggs #if defined(_KERNEL) || defined(_STANDALONE)
164 1.10.6.2 briggs #if !defined(CACHELINESIZE)
165 1.10.6.2 briggs #define CACHELINESIZE 32
166 1.10.6.2 briggs #endif
167 1.10.6.2 briggs #endif
168 1.10.6.2 briggs
169 1.10.6.2 briggs void __syncicache(void *, int);
170 1.10.6.2 briggs
171 1.10.6.2 briggs /*
172 1.10.6.2 briggs * CTL_MACHDEP definitions.
173 1.10.6.2 briggs */
174 1.10.6.2 briggs #define CPU_CACHELINE 1
175 1.10.6.2 briggs #define CPU_TIMEBASE 2
176 1.10.6.2 briggs #define CPU_CPUTEMP 3
177 1.10.6.2 briggs #define CPU_PRINTFATALTRAPS 4
178 1.10.6.2 briggs #define CPU_MAXID 5
179 1.10.6.2 briggs
180 1.10.6.2 briggs #define CTL_MACHDEP_NAMES { \
181 1.10.6.2 briggs { 0, 0 }, \
182 1.10.6.2 briggs { "cachelinesize", CTLTYPE_INT }, \
183 1.10.6.2 briggs { "timebase", CTLTYPE_INT }, \
184 1.10.6.2 briggs { "cputempature", CTLTYPE_INT }, \
185 1.10.6.2 briggs { "printfataltraps", CTLTYPE_INT }, \
186 1.10.6.2 briggs }
187 1.10.6.2 briggs
188 1.10.6.2 briggs #endif /* _POWERPC_CPU_H_ */
189