cpu.h revision 1.29 1 1.29 hannken /* $NetBSD: cpu.h,v 1.29 2003/03/11 10:40:16 hannken Exp $ */
2 1.1 ws
3 1.1 ws /*
4 1.5 ws * Copyright (C) 1999 Wolfgang Solfrank.
5 1.5 ws * Copyright (C) 1999 TooLs GmbH.
6 1.9 matt * Copyright (C) 1995-1997 Wolfgang Solfrank.
7 1.9 matt * Copyright (C) 1995-1997 TooLs GmbH.
8 1.1 ws * All rights reserved.
9 1.1 ws *
10 1.1 ws * Redistribution and use in source and binary forms, with or without
11 1.1 ws * modification, are permitted provided that the following conditions
12 1.1 ws * are met:
13 1.1 ws * 1. Redistributions of source code must retain the above copyright
14 1.1 ws * notice, this list of conditions and the following disclaimer.
15 1.1 ws * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 ws * notice, this list of conditions and the following disclaimer in the
17 1.1 ws * documentation and/or other materials provided with the distribution.
18 1.1 ws * 3. All advertising materials mentioning features or use of this software
19 1.1 ws * must display the following acknowledgement:
20 1.1 ws * This product includes software developed by TooLs GmbH.
21 1.1 ws * 4. The name of TooLs GmbH may not be used to endorse or promote products
22 1.1 ws * derived from this software without specific prior written permission.
23 1.1 ws *
24 1.1 ws * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25 1.1 ws * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 1.1 ws * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 1.1 ws * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 1.1 ws * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 1.1 ws * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 1.1 ws * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 1.1 ws * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 1.1 ws * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 1.1 ws * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 1.1 ws */
35 1.5 ws #ifndef _POWERPC_CPU_H_
36 1.5 ws #define _POWERPC_CPU_H_
37 1.1 ws
38 1.27 matt struct cache_info {
39 1.27 matt int dcache_size;
40 1.27 matt int dcache_line_size;
41 1.27 matt int icache_size;
42 1.27 matt int icache_line_size;
43 1.27 matt };
44 1.27 matt
45 1.27 matt #ifdef _KERNEL
46 1.9 matt #if defined(_KERNEL_OPT)
47 1.9 matt #include "opt_lockdebug.h"
48 1.9 matt #include "opt_multiprocessor.h"
49 1.16 matt #include "opt_ppcarch.h"
50 1.9 matt #endif
51 1.9 matt
52 1.9 matt #include <machine/frame.h>
53 1.9 matt #include <machine/psl.h>
54 1.9 matt #include <machine/intr.h>
55 1.20 matt #include <sys/device.h>
56 1.9 matt
57 1.9 matt #include <sys/sched.h>
58 1.13 nathanw #include <dev/sysmon/sysmonvar.h>
59 1.14 eeh
60 1.9 matt struct cpu_info {
61 1.9 matt struct schedstate_percpu ci_schedstate; /* scheduler state */
62 1.9 matt struct device *ci_dev; /* device of corresponding cpu */
63 1.23 thorpej struct lwp *ci_curlwp; /* current owner of the processor */
64 1.9 matt
65 1.9 matt struct pcb *ci_curpcb;
66 1.9 matt struct pmap *ci_curpm;
67 1.23 thorpej struct lwp *ci_fpulwp;
68 1.23 thorpej struct lwp *ci_veclwp;
69 1.9 matt struct pcb *ci_idle_pcb; /* PA of our idle pcb */
70 1.9 matt int ci_cpuid;
71 1.9 matt
72 1.28 matt volatile int ci_astpending;
73 1.9 matt int ci_want_resched;
74 1.28 matt volatile u_long ci_lasttb;
75 1.28 matt volatile int ci_tickspending;
76 1.9 matt int ci_cpl;
77 1.25 matt int ci_iactive;
78 1.9 matt int ci_ipending;
79 1.9 matt int ci_intrdepth;
80 1.9 matt char *ci_intstk;
81 1.9 matt char *ci_spillstk;
82 1.25 matt register_t ci_tempsave[8];
83 1.25 matt register_t ci_ddbsave[8];
84 1.25 matt register_t ci_ipkdbsave[8];
85 1.25 matt register_t ci_disisave[4];
86 1.14 eeh struct cache_info ci_ci;
87 1.12 nathanw struct sysmon_envsys ci_sysmon;
88 1.12 nathanw struct envsys_tre_data ci_tau_info;
89 1.25 matt struct evcnt ci_ev_clock; /* clock intrs */
90 1.25 matt struct evcnt ci_ev_softclock; /* softclock intrs */
91 1.25 matt struct evcnt ci_ev_softnet; /* softnet intrs */
92 1.25 matt struct evcnt ci_ev_softserial; /* softserial intrs */
93 1.9 matt struct evcnt ci_ev_traps; /* calls to trap() */
94 1.9 matt struct evcnt ci_ev_kdsi; /* kernel DSI traps */
95 1.9 matt struct evcnt ci_ev_udsi; /* user DSI traps */
96 1.9 matt struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
97 1.9 matt struct evcnt ci_ev_isi; /* user ISI traps */
98 1.9 matt struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
99 1.9 matt struct evcnt ci_ev_pgm; /* user PGM traps */
100 1.9 matt struct evcnt ci_ev_fpu; /* FPU traps */
101 1.9 matt struct evcnt ci_ev_fpusw; /* FPU context switch */
102 1.9 matt struct evcnt ci_ev_ali; /* Alignment traps */
103 1.9 matt struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
104 1.9 matt struct evcnt ci_ev_scalls; /* system call traps */
105 1.9 matt struct evcnt ci_ev_vec; /* Altivec traps */
106 1.9 matt struct evcnt ci_ev_vecsw; /* Altivec context switches */
107 1.16 matt struct evcnt ci_ev_umchk; /* user MCHK events */
108 1.25 matt #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
109 1.25 matt u_long ci_spin_locks; /* # of spin locks held */
110 1.25 matt u_long ci_simple_locks; /* # of simple locks held */
111 1.25 matt #endif
112 1.9 matt };
113 1.9 matt
114 1.9 matt #ifdef MULTIPROCESSOR
115 1.9 matt static __inline int
116 1.11 chs cpu_number(void)
117 1.9 matt {
118 1.9 matt int pir;
119 1.9 matt
120 1.9 matt asm ("mfspr %0,1023" : "=r"(pir));
121 1.9 matt return pir;
122 1.9 matt }
123 1.9 matt
124 1.11 chs void cpu_boot_secondary_processors(void);
125 1.9 matt
126 1.9 matt
127 1.9 matt #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
128 1.18 chs #define CPU_INFO_ITERATOR int
129 1.18 chs #define CPU_INFO_FOREACH(cii, ci) \
130 1.18 chs cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++
131 1.18 chs
132 1.9 matt #else
133 1.9 matt
134 1.9 matt #define cpu_number() 0
135 1.9 matt
136 1.18 chs #define CPU_INFO_ITERATOR int
137 1.18 chs #define CPU_INFO_FOREACH(cii, ci) \
138 1.18 chs cii = 0, ci = curcpu(); ci != NULL; ci = NULL
139 1.18 chs
140 1.9 matt #endif /* MULTIPROCESSOR */
141 1.9 matt
142 1.25 matt extern struct cpu_info cpu_info[];
143 1.25 matt
144 1.25 matt static __inline struct cpu_info *
145 1.25 matt curcpu(void)
146 1.25 matt {
147 1.25 matt struct cpu_info *ci;
148 1.25 matt
149 1.25 matt asm volatile ("mfsprg %0,0" : "=r"(ci));
150 1.25 matt return ci;
151 1.25 matt }
152 1.25 matt
153 1.25 matt #define curlwp (curcpu()->ci_curlwp)
154 1.25 matt #define curpcb (curcpu()->ci_curpcb)
155 1.25 matt #define curpm (curcpu()->ci_curpm)
156 1.25 matt
157 1.20 matt static __inline register_t
158 1.18 chs mfmsr(void)
159 1.18 chs {
160 1.20 matt register_t msr;
161 1.18 chs
162 1.18 chs asm volatile ("mfmsr %0" : "=r"(msr));
163 1.18 chs return msr;
164 1.18 chs }
165 1.18 chs
166 1.18 chs static __inline void
167 1.20 matt mtmsr(register_t msr)
168 1.18 chs {
169 1.18 chs
170 1.18 chs asm volatile ("mtmsr %0" : : "r"(msr));
171 1.19 chs }
172 1.19 chs
173 1.19 chs static __inline uint32_t
174 1.19 chs mftbl(void)
175 1.19 chs {
176 1.19 chs uint32_t tbl;
177 1.19 chs
178 1.29 hannken asm volatile (
179 1.29 hannken #ifdef PPC_IBM403
180 1.29 hannken " mftblo %0 \n"
181 1.29 hannken #else
182 1.29 hannken " mftbl %0 \n"
183 1.29 hannken #endif
184 1.29 hannken : "=r" (tbl));
185 1.29 hannken
186 1.19 chs return tbl;
187 1.19 chs }
188 1.19 chs
189 1.19 chs static __inline uint64_t
190 1.19 chs mftb(void)
191 1.19 chs {
192 1.19 chs uint64_t tb;
193 1.19 chs int tmp;
194 1.19 chs
195 1.22 thorpej asm volatile (
196 1.29 hannken #ifdef PPC_IBM403
197 1.29 hannken "1: mftbhi %0 \n"
198 1.29 hannken " mftblo %0+1 \n"
199 1.29 hannken " mftbhi %1 \n"
200 1.29 hannken #else
201 1.22 thorpej "1: mftbu %0 \n"
202 1.22 thorpej " mftb %0+1 \n"
203 1.22 thorpej " mftbu %1 \n"
204 1.29 hannken #endif
205 1.22 thorpej " cmplw %0,%1 \n"
206 1.29 hannken " bne- 1b \n"
207 1.29 hannken : "=r" (tb), "=r"(tmp) :: "cr0");
208 1.29 hannken
209 1.19 chs return tb;
210 1.24 kleink }
211 1.24 kleink
212 1.24 kleink static __inline uint32_t
213 1.24 kleink mfrtcl(void)
214 1.24 kleink {
215 1.24 kleink uint32_t rtcl;
216 1.24 kleink
217 1.24 kleink asm volatile ("mfrtcl %0" : "=r"(rtcl));
218 1.24 kleink return rtcl;
219 1.24 kleink }
220 1.24 kleink
221 1.24 kleink static __inline void
222 1.24 kleink mfrtc(uint32_t *rtcp)
223 1.24 kleink {
224 1.24 kleink uint32_t tmp;
225 1.24 kleink
226 1.24 kleink asm volatile (
227 1.24 kleink "1: mfrtcu %0 \n"
228 1.24 kleink " mfrtcl %1 \n"
229 1.24 kleink " mfrtcu %2 \n"
230 1.24 kleink " cmplw %0,%2 \n"
231 1.24 kleink " bne- 1b"
232 1.24 kleink : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp));
233 1.19 chs }
234 1.19 chs
235 1.19 chs static __inline uint32_t
236 1.19 chs mfpvr(void)
237 1.19 chs {
238 1.19 chs uint32_t pvr;
239 1.19 chs
240 1.19 chs asm volatile ("mfpvr %0" : "=r"(pvr));
241 1.19 chs return (pvr);
242 1.18 chs }
243 1.18 chs
244 1.9 matt #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
245 1.9 matt #define CLKF_BASEPRI(frame) ((frame)->pri == 0)
246 1.9 matt #define CLKF_PC(frame) ((frame)->srr0)
247 1.9 matt #define CLKF_INTR(frame) ((frame)->depth > 0)
248 1.9 matt
249 1.23 thorpej #define LWP_PC(l) (trapframe(l)->srr0)
250 1.9 matt
251 1.9 matt #define cpu_swapout(p)
252 1.9 matt #define cpu_wait(p)
253 1.23 thorpej #define cpu_proc_fork(p1, p2)
254 1.9 matt
255 1.9 matt extern int powersave;
256 1.9 matt extern int cpu_timebase;
257 1.9 matt extern int cpu_printfataltraps;
258 1.16 matt extern char cpu_model[];
259 1.16 matt
260 1.16 matt struct cpu_info *cpu_attach_common(struct device *, int);
261 1.18 chs void cpu_setup(struct device *, struct cpu_info *);
262 1.16 matt void cpu_identify(char *, size_t);
263 1.16 matt void delay (unsigned int);
264 1.16 matt void cpu_probe_cache(void);
265 1.16 matt void dcache_flush_page(vaddr_t);
266 1.16 matt void icache_flush_page(vaddr_t);
267 1.16 matt void dcache_flush(vaddr_t, vsize_t);
268 1.16 matt void icache_flush(vaddr_t, vsize_t);
269 1.9 matt
270 1.9 matt #define DELAY(n) delay(n)
271 1.9 matt
272 1.25 matt #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1)
273 1.25 matt #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1)
274 1.25 matt #define signotify(p) (curcpu()->ci_astpending = 1)
275 1.9 matt
276 1.26 matt #ifdef PPC_OEA
277 1.26 matt void oea_init(void (*)(void));
278 1.26 matt void oea_startup(const char *);
279 1.26 matt void oea_dumpsys(void);
280 1.26 matt void oea_install_extint(void (*)(void));
281 1.16 matt void *mapiodev(paddr_t, psize_t);
282 1.16 matt paddr_t kvtop(caddr_t);
283 1.16 matt void softnet(int);
284 1.16 matt
285 1.16 matt extern paddr_t msgbuf_paddr;
286 1.16 matt extern int cpu_altivec;
287 1.16 matt #endif
288 1.16 matt
289 1.9 matt #endif /* _KERNEL */
290 1.9 matt
291 1.9 matt #if defined(_KERNEL) || defined(_STANDALONE)
292 1.9 matt #if !defined(CACHELINESIZE)
293 1.29 hannken #ifdef PPC_IBM403
294 1.29 hannken #define CACHELINESIZE 16
295 1.29 hannken #else
296 1.9 matt #define CACHELINESIZE 32
297 1.29 hannken #endif
298 1.9 matt #endif
299 1.10 matt #endif
300 1.10 matt
301 1.15 matt void __syncicache(void *, size_t);
302 1.14 eeh
303 1.5 ws /*
304 1.5 ws * CTL_MACHDEP definitions.
305 1.5 ws */
306 1.9 matt #define CPU_CACHELINE 1
307 1.9 matt #define CPU_TIMEBASE 2
308 1.9 matt #define CPU_CPUTEMP 3
309 1.9 matt #define CPU_PRINTFATALTRAPS 4
310 1.14 eeh #define CPU_CACHEINFO 5
311 1.16 matt #define CPU_ALTIVEC 6
312 1.16 matt #define CPU_MODEL 7
313 1.17 matt #define CPU_POWERSAVE 8
314 1.17 matt #define CPU_MAXID 9
315 1.1 ws
316 1.5 ws #define CTL_MACHDEP_NAMES { \
317 1.5 ws { 0, 0 }, \
318 1.5 ws { "cachelinesize", CTLTYPE_INT }, \
319 1.7 matt { "timebase", CTLTYPE_INT }, \
320 1.7 matt { "cputempature", CTLTYPE_INT }, \
321 1.9 matt { "printfataltraps", CTLTYPE_INT }, \
322 1.14 eeh { "cacheinfo", CTLTYPE_STRUCT }, \
323 1.16 matt { "altivec", CTLTYPE_INT }, \
324 1.16 matt { "model", CTLTYPE_STRING }, \
325 1.17 matt { "powersave", CTLTYPE_INT }, \
326 1.1 ws }
327 1.1 ws
328 1.5 ws #endif /* _POWERPC_CPU_H_ */
329