cpu.h revision 1.44 1 1.44 briggs /* $NetBSD: cpu.h,v 1.44 2005/02/03 14:47:09 briggs Exp $ */
2 1.1 ws
3 1.1 ws /*
4 1.5 ws * Copyright (C) 1999 Wolfgang Solfrank.
5 1.5 ws * Copyright (C) 1999 TooLs GmbH.
6 1.9 matt * Copyright (C) 1995-1997 Wolfgang Solfrank.
7 1.9 matt * Copyright (C) 1995-1997 TooLs GmbH.
8 1.1 ws * All rights reserved.
9 1.1 ws *
10 1.1 ws * Redistribution and use in source and binary forms, with or without
11 1.1 ws * modification, are permitted provided that the following conditions
12 1.1 ws * are met:
13 1.1 ws * 1. Redistributions of source code must retain the above copyright
14 1.1 ws * notice, this list of conditions and the following disclaimer.
15 1.1 ws * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 ws * notice, this list of conditions and the following disclaimer in the
17 1.1 ws * documentation and/or other materials provided with the distribution.
18 1.1 ws * 3. All advertising materials mentioning features or use of this software
19 1.1 ws * must display the following acknowledgement:
20 1.1 ws * This product includes software developed by TooLs GmbH.
21 1.1 ws * 4. The name of TooLs GmbH may not be used to endorse or promote products
22 1.1 ws * derived from this software without specific prior written permission.
23 1.1 ws *
24 1.1 ws * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25 1.1 ws * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 1.1 ws * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 1.1 ws * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28 1.1 ws * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 1.1 ws * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 1.1 ws * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 1.1 ws * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 1.1 ws * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 1.1 ws * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 1.1 ws */
35 1.5 ws #ifndef _POWERPC_CPU_H_
36 1.5 ws #define _POWERPC_CPU_H_
37 1.1 ws
38 1.27 matt struct cache_info {
39 1.27 matt int dcache_size;
40 1.27 matt int dcache_line_size;
41 1.27 matt int icache_size;
42 1.27 matt int icache_line_size;
43 1.27 matt };
44 1.27 matt
45 1.27 matt #ifdef _KERNEL
46 1.9 matt #if defined(_KERNEL_OPT)
47 1.9 matt #include "opt_lockdebug.h"
48 1.9 matt #include "opt_multiprocessor.h"
49 1.16 matt #include "opt_ppcarch.h"
50 1.9 matt #endif
51 1.9 matt
52 1.9 matt #include <machine/frame.h>
53 1.9 matt #include <machine/psl.h>
54 1.9 matt #include <machine/intr.h>
55 1.20 matt #include <sys/device.h>
56 1.9 matt
57 1.42 yamt #include <sys/cpu_data.h>
58 1.14 eeh
59 1.9 matt struct cpu_info {
60 1.42 yamt struct cpu_data ci_data; /* MI per-cpu data */
61 1.9 matt struct device *ci_dev; /* device of corresponding cpu */
62 1.23 thorpej struct lwp *ci_curlwp; /* current owner of the processor */
63 1.9 matt
64 1.9 matt struct pcb *ci_curpcb;
65 1.38 matt struct pmap *ci_curpm;
66 1.23 thorpej struct lwp *ci_fpulwp;
67 1.23 thorpej struct lwp *ci_veclwp;
68 1.9 matt struct pcb *ci_idle_pcb; /* PA of our idle pcb */
69 1.9 matt int ci_cpuid;
70 1.9 matt
71 1.28 matt volatile int ci_astpending;
72 1.9 matt int ci_want_resched;
73 1.28 matt volatile u_long ci_lasttb;
74 1.28 matt volatile int ci_tickspending;
75 1.9 matt int ci_cpl;
76 1.25 matt int ci_iactive;
77 1.9 matt int ci_ipending;
78 1.9 matt int ci_intrdepth;
79 1.9 matt char *ci_intstk;
80 1.32 matt #define CPUSAVE_LEN 8
81 1.32 matt register_t ci_tempsave[CPUSAVE_LEN];
82 1.32 matt register_t ci_ddbsave[CPUSAVE_LEN];
83 1.32 matt register_t ci_ipkdbsave[CPUSAVE_LEN];
84 1.32 matt #define CPUSAVE_R28 0 /* where r28 gets saved */
85 1.32 matt #define CPUSAVE_R29 1 /* where r29 gets saved */
86 1.32 matt #define CPUSAVE_R30 2 /* where r30 gets saved */
87 1.32 matt #define CPUSAVE_R31 3 /* where r31 gets saved */
88 1.32 matt #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */
89 1.32 matt #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */
90 1.32 matt #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
91 1.32 matt #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
92 1.32 matt #define DISISAVE_LEN 4
93 1.32 matt register_t ci_disisave[DISISAVE_LEN];
94 1.14 eeh struct cache_info ci_ci;
95 1.40 matt void *ci_sysmon_cookie;
96 1.43 matt void (*ci_idlespin)(void);
97 1.44 briggs uint32_t ci_khz;
98 1.25 matt struct evcnt ci_ev_clock; /* clock intrs */
99 1.25 matt struct evcnt ci_ev_softclock; /* softclock intrs */
100 1.25 matt struct evcnt ci_ev_softnet; /* softnet intrs */
101 1.25 matt struct evcnt ci_ev_softserial; /* softserial intrs */
102 1.9 matt struct evcnt ci_ev_traps; /* calls to trap() */
103 1.9 matt struct evcnt ci_ev_kdsi; /* kernel DSI traps */
104 1.9 matt struct evcnt ci_ev_udsi; /* user DSI traps */
105 1.9 matt struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
106 1.33 matt struct evcnt ci_ev_kisi; /* kernel ISI traps */
107 1.9 matt struct evcnt ci_ev_isi; /* user ISI traps */
108 1.9 matt struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
109 1.9 matt struct evcnt ci_ev_pgm; /* user PGM traps */
110 1.9 matt struct evcnt ci_ev_fpu; /* FPU traps */
111 1.9 matt struct evcnt ci_ev_fpusw; /* FPU context switch */
112 1.9 matt struct evcnt ci_ev_ali; /* Alignment traps */
113 1.9 matt struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
114 1.9 matt struct evcnt ci_ev_scalls; /* system call traps */
115 1.9 matt struct evcnt ci_ev_vec; /* Altivec traps */
116 1.9 matt struct evcnt ci_ev_vecsw; /* Altivec context switches */
117 1.16 matt struct evcnt ci_ev_umchk; /* user MCHK events */
118 1.9 matt };
119 1.9 matt
120 1.9 matt #ifdef MULTIPROCESSOR
121 1.9 matt static __inline int
122 1.11 chs cpu_number(void)
123 1.9 matt {
124 1.9 matt int pir;
125 1.9 matt
126 1.30 matt __asm ("mfspr %0,1023" : "=r"(pir));
127 1.9 matt return pir;
128 1.9 matt }
129 1.9 matt
130 1.11 chs void cpu_boot_secondary_processors(void);
131 1.9 matt
132 1.9 matt
133 1.9 matt #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
134 1.18 chs #define CPU_INFO_ITERATOR int
135 1.18 chs #define CPU_INFO_FOREACH(cii, ci) \
136 1.18 chs cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++
137 1.18 chs
138 1.9 matt #else
139 1.9 matt
140 1.9 matt #define cpu_number() 0
141 1.9 matt
142 1.18 chs #define CPU_INFO_ITERATOR int
143 1.18 chs #define CPU_INFO_FOREACH(cii, ci) \
144 1.18 chs cii = 0, ci = curcpu(); ci != NULL; ci = NULL
145 1.18 chs
146 1.9 matt #endif /* MULTIPROCESSOR */
147 1.9 matt
148 1.25 matt extern struct cpu_info cpu_info[];
149 1.25 matt
150 1.25 matt static __inline struct cpu_info *
151 1.25 matt curcpu(void)
152 1.25 matt {
153 1.25 matt struct cpu_info *ci;
154 1.25 matt
155 1.30 matt __asm __volatile ("mfsprg %0,0" : "=r"(ci));
156 1.25 matt return ci;
157 1.25 matt }
158 1.25 matt
159 1.25 matt #define curlwp (curcpu()->ci_curlwp)
160 1.25 matt #define curpcb (curcpu()->ci_curpcb)
161 1.38 matt #define curpm (curcpu()->ci_curpm)
162 1.25 matt
163 1.20 matt static __inline register_t
164 1.18 chs mfmsr(void)
165 1.18 chs {
166 1.20 matt register_t msr;
167 1.18 chs
168 1.30 matt __asm __volatile ("mfmsr %0" : "=r"(msr));
169 1.18 chs return msr;
170 1.18 chs }
171 1.18 chs
172 1.18 chs static __inline void
173 1.20 matt mtmsr(register_t msr)
174 1.18 chs {
175 1.18 chs
176 1.30 matt __asm __volatile ("mtmsr %0" : : "r"(msr));
177 1.19 chs }
178 1.19 chs
179 1.19 chs static __inline uint32_t
180 1.19 chs mftbl(void)
181 1.19 chs {
182 1.19 chs uint32_t tbl;
183 1.19 chs
184 1.30 matt __asm __volatile (
185 1.29 hannken #ifdef PPC_IBM403
186 1.29 hannken " mftblo %0 \n"
187 1.29 hannken #else
188 1.29 hannken " mftbl %0 \n"
189 1.29 hannken #endif
190 1.29 hannken : "=r" (tbl));
191 1.29 hannken
192 1.19 chs return tbl;
193 1.19 chs }
194 1.19 chs
195 1.19 chs static __inline uint64_t
196 1.19 chs mftb(void)
197 1.19 chs {
198 1.19 chs uint64_t tb;
199 1.32 matt
200 1.32 matt #ifdef _LP64
201 1.32 matt __asm __volatile ("mftb %0" : "=r"(tb));
202 1.32 matt #else
203 1.19 chs int tmp;
204 1.19 chs
205 1.30 matt __asm __volatile (
206 1.29 hannken #ifdef PPC_IBM403
207 1.29 hannken "1: mftbhi %0 \n"
208 1.29 hannken " mftblo %0+1 \n"
209 1.29 hannken " mftbhi %1 \n"
210 1.29 hannken #else
211 1.22 thorpej "1: mftbu %0 \n"
212 1.22 thorpej " mftb %0+1 \n"
213 1.22 thorpej " mftbu %1 \n"
214 1.29 hannken #endif
215 1.22 thorpej " cmplw %0,%1 \n"
216 1.29 hannken " bne- 1b \n"
217 1.29 hannken : "=r" (tb), "=r"(tmp) :: "cr0");
218 1.32 matt #endif
219 1.29 hannken
220 1.19 chs return tb;
221 1.24 kleink }
222 1.24 kleink
223 1.24 kleink static __inline uint32_t
224 1.24 kleink mfrtcl(void)
225 1.24 kleink {
226 1.24 kleink uint32_t rtcl;
227 1.24 kleink
228 1.30 matt __asm __volatile ("mfrtcl %0" : "=r"(rtcl));
229 1.24 kleink return rtcl;
230 1.24 kleink }
231 1.24 kleink
232 1.24 kleink static __inline void
233 1.24 kleink mfrtc(uint32_t *rtcp)
234 1.24 kleink {
235 1.24 kleink uint32_t tmp;
236 1.24 kleink
237 1.30 matt __asm __volatile (
238 1.24 kleink "1: mfrtcu %0 \n"
239 1.24 kleink " mfrtcl %1 \n"
240 1.24 kleink " mfrtcu %2 \n"
241 1.24 kleink " cmplw %0,%2 \n"
242 1.24 kleink " bne- 1b"
243 1.41 kleink : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0");
244 1.19 chs }
245 1.19 chs
246 1.19 chs static __inline uint32_t
247 1.19 chs mfpvr(void)
248 1.19 chs {
249 1.19 chs uint32_t pvr;
250 1.19 chs
251 1.30 matt __asm __volatile ("mfpvr %0" : "=r"(pvr));
252 1.19 chs return (pvr);
253 1.18 chs }
254 1.18 chs
255 1.37 matt /*
256 1.37 matt * CLKF_BASEPRI is dependent on the underlying interrupt code
257 1.37 matt * and can not be defined here. It should be defined in
258 1.37 matt * <machine/intr.h>
259 1.37 matt */
260 1.9 matt #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
261 1.9 matt #define CLKF_PC(frame) ((frame)->srr0)
262 1.9 matt #define CLKF_INTR(frame) ((frame)->depth > 0)
263 1.9 matt
264 1.23 thorpej #define LWP_PC(l) (trapframe(l)->srr0)
265 1.9 matt
266 1.9 matt #define cpu_swapout(p)
267 1.23 thorpej #define cpu_proc_fork(p1, p2)
268 1.9 matt
269 1.9 matt extern int powersave;
270 1.9 matt extern int cpu_timebase;
271 1.9 matt extern int cpu_printfataltraps;
272 1.16 matt extern char cpu_model[];
273 1.16 matt
274 1.16 matt struct cpu_info *cpu_attach_common(struct device *, int);
275 1.18 chs void cpu_setup(struct device *, struct cpu_info *);
276 1.16 matt void cpu_identify(char *, size_t);
277 1.16 matt void delay (unsigned int);
278 1.16 matt void cpu_probe_cache(void);
279 1.16 matt void dcache_flush_page(vaddr_t);
280 1.16 matt void icache_flush_page(vaddr_t);
281 1.16 matt void dcache_flush(vaddr_t, vsize_t);
282 1.16 matt void icache_flush(vaddr_t, vsize_t);
283 1.31 scw void *mapiodev(paddr_t, psize_t);
284 1.9 matt
285 1.9 matt #define DELAY(n) delay(n)
286 1.9 matt
287 1.25 matt #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1)
288 1.25 matt #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1)
289 1.25 matt #define signotify(p) (curcpu()->ci_astpending = 1)
290 1.9 matt
291 1.26 matt #ifdef PPC_OEA
292 1.26 matt void oea_init(void (*)(void));
293 1.26 matt void oea_startup(const char *);
294 1.26 matt void oea_dumpsys(void);
295 1.26 matt void oea_install_extint(void (*)(void));
296 1.16 matt paddr_t kvtop(caddr_t);
297 1.16 matt void softnet(int);
298 1.16 matt
299 1.16 matt extern paddr_t msgbuf_paddr;
300 1.16 matt extern int cpu_altivec;
301 1.16 matt #endif
302 1.16 matt
303 1.9 matt #endif /* _KERNEL */
304 1.9 matt
305 1.9 matt #if defined(_KERNEL) || defined(_STANDALONE)
306 1.9 matt #if !defined(CACHELINESIZE)
307 1.29 hannken #ifdef PPC_IBM403
308 1.29 hannken #define CACHELINESIZE 16
309 1.29 hannken #else
310 1.9 matt #define CACHELINESIZE 32
311 1.29 hannken #endif
312 1.9 matt #endif
313 1.10 matt #endif
314 1.10 matt
315 1.15 matt void __syncicache(void *, size_t);
316 1.14 eeh
317 1.5 ws /*
318 1.5 ws * CTL_MACHDEP definitions.
319 1.5 ws */
320 1.9 matt #define CPU_CACHELINE 1
321 1.9 matt #define CPU_TIMEBASE 2
322 1.9 matt #define CPU_CPUTEMP 3
323 1.9 matt #define CPU_PRINTFATALTRAPS 4
324 1.14 eeh #define CPU_CACHEINFO 5
325 1.16 matt #define CPU_ALTIVEC 6
326 1.16 matt #define CPU_MODEL 7
327 1.17 matt #define CPU_POWERSAVE 8
328 1.17 matt #define CPU_MAXID 9
329 1.1 ws
330 1.5 ws #define CTL_MACHDEP_NAMES { \
331 1.5 ws { 0, 0 }, \
332 1.5 ws { "cachelinesize", CTLTYPE_INT }, \
333 1.7 matt { "timebase", CTLTYPE_INT }, \
334 1.7 matt { "cputempature", CTLTYPE_INT }, \
335 1.9 matt { "printfataltraps", CTLTYPE_INT }, \
336 1.14 eeh { "cacheinfo", CTLTYPE_STRUCT }, \
337 1.16 matt { "altivec", CTLTYPE_INT }, \
338 1.16 matt { "model", CTLTYPE_STRING }, \
339 1.17 matt { "powersave", CTLTYPE_INT }, \
340 1.1 ws }
341 1.1 ws
342 1.5 ws #endif /* _POWERPC_CPU_H_ */
343