cpu.h revision 1.10.6.9
1 /* $NetBSD: cpu.h,v 1.10.6.9 2002/08/01 04:03:21 nathanw Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 #if defined(_KERNEL_OPT) 39 #include "opt_lockdebug.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_ppcarch.h" 42 #endif 43 44 #include <sys/device.h> 45 #include <machine/frame.h> 46 #include <machine/psl.h> 47 #include <machine/intr.h> 48 49 50 struct cache_info { 51 int dcache_size; 52 int dcache_line_size; 53 int icache_size; 54 int icache_line_size; 55 }; 56 57 58 #ifdef _KERNEL 59 #include <sys/sched.h> 60 #include <dev/sysmon/sysmonvar.h> 61 62 struct cpu_info { 63 struct schedstate_percpu ci_schedstate; /* scheduler state */ 64 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 65 u_long ci_spin_locks; /* # of spin locks held */ 66 u_long ci_simple_locks; /* # of simple locks held */ 67 #endif 68 struct device *ci_dev; /* device of corresponding cpu */ 69 struct lwp *ci_curlwp; /* current owner of the processor */ 70 71 struct pcb *ci_curpcb; 72 struct pmap *ci_curpm; 73 struct lwp *ci_fpulwp; 74 struct lwp *ci_veclwp; 75 struct pcb *ci_idle_pcb; /* PA of our idle pcb */ 76 int ci_cpuid; 77 78 int ci_astpending; 79 int ci_want_resched; 80 u_long ci_lasttb; 81 int ci_tickspending; 82 int ci_cpl; 83 int ci_ipending; 84 int ci_intrdepth; 85 char *ci_intstk; 86 char *ci_spillstk; 87 int ci_tempsave[8]; 88 int ci_ddbsave[8]; 89 int ci_ipkdbsave[8]; 90 int ci_disisave[4]; 91 struct cache_info ci_ci; 92 struct sysmon_envsys ci_sysmon; 93 struct envsys_tre_data ci_tau_info; 94 struct evcnt ci_ev_traps; /* calls to trap() */ 95 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 96 struct evcnt ci_ev_udsi; /* user DSI traps */ 97 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 98 struct evcnt ci_ev_isi; /* user ISI traps */ 99 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 100 struct evcnt ci_ev_pgm; /* user PGM traps */ 101 struct evcnt ci_ev_fpu; /* FPU traps */ 102 struct evcnt ci_ev_fpusw; /* FPU context switch */ 103 struct evcnt ci_ev_ali; /* Alignment traps */ 104 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 105 struct evcnt ci_ev_scalls; /* system call traps */ 106 struct evcnt ci_ev_vec; /* Altivec traps */ 107 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 108 struct evcnt ci_ev_umchk; /* user MCHK events */ 109 }; 110 111 #ifdef MULTIPROCESSOR 112 static __inline int 113 cpu_number(void) 114 { 115 int pir; 116 117 asm ("mfspr %0,1023" : "=r"(pir)); 118 return pir; 119 } 120 121 static __inline struct cpu_info * 122 curcpu(void) 123 { 124 struct cpu_info *ci; 125 126 asm volatile ("mfsprg %0,0" : "=r"(ci)); 127 return ci; 128 } 129 130 void cpu_boot_secondary_processors(void); 131 132 extern struct cpu_info cpu_info[]; 133 134 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 135 #define curlwp curcpu()->ci_curlwp 136 #define curpcb curcpu()->ci_curpcb 137 #define curpm curcpu()->ci_curpm 138 #define want_resched curcpu()->ci_want_resched 139 #define astpending curcpu()->ci_astpending 140 #define intr_depth curcpu()->ci_intrdepth 141 142 #define CPU_INFO_ITERATOR int 143 #define CPU_INFO_FOREACH(cii, ci) \ 144 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 145 146 #else 147 extern struct cpu_info cpu_info_store; 148 extern volatile int want_resched; 149 extern volatile int astpending; 150 extern volatile int intr_depth; 151 152 #define curcpu() (&cpu_info_store) 153 #define cpu_number() 0 154 155 #define CPU_INFO_ITERATOR int 156 #define CPU_INFO_FOREACH(cii, ci) \ 157 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 158 159 #endif /* MULTIPROCESSOR */ 160 161 static __inline int 162 mfmsr(void) 163 { 164 int msr; 165 166 asm volatile ("mfmsr %0" : "=r"(msr)); 167 return msr; 168 } 169 170 static __inline void 171 mtmsr(int msr) 172 { 173 174 asm volatile ("mtmsr %0" : : "r"(msr)); 175 } 176 177 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 178 #define CLKF_BASEPRI(frame) ((frame)->pri == 0) 179 #define CLKF_PC(frame) ((frame)->srr0) 180 #define CLKF_INTR(frame) ((frame)->depth > 0) 181 182 #define LWP_PC(l) (trapframe(l)->srr0) 183 184 #define cpu_swapout(p) 185 #define cpu_wait(p) 186 #define cpu_proc_fork(p1, p2) 187 188 extern int powersave; 189 extern int cpu_timebase; 190 extern int cpu_printfataltraps; 191 extern char cpu_model[]; 192 193 struct cpu_info *cpu_attach_common(struct device *, int); 194 void cpu_setup(struct device *, struct cpu_info *); 195 void cpu_identify(char *, size_t); 196 void delay (unsigned int); 197 void cpu_probe_cache(void); 198 void dcache_flush_page(vaddr_t); 199 void icache_flush_page(vaddr_t); 200 void dcache_flush(vaddr_t, vsize_t); 201 void icache_flush(vaddr_t, vsize_t); 202 203 #define DELAY(n) delay(n) 204 205 #define need_resched(ci) (want_resched = 1, astpending = 1) 206 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1) 207 #define signotify(p) (astpending = 1) 208 209 #ifdef PPC_MPC6XX 210 void mpc6xx_init(void (*)(void)); 211 void mpc6xx_startup(const char *); 212 void mpc6xx_dumpsys(void); 213 void mpc6xx_install_extint(void (*)(void)); 214 void *mapiodev(paddr_t, psize_t); 215 paddr_t kvtop(caddr_t); 216 void softnet(int); 217 218 extern paddr_t msgbuf_paddr; 219 extern int cpu_altivec; 220 #endif 221 222 #endif /* _KERNEL */ 223 224 #if defined(_KERNEL) || defined(_STANDALONE) 225 #if !defined(CACHELINESIZE) 226 #define CACHELINESIZE 32 227 #endif 228 #endif 229 230 void __syncicache(void *, size_t); 231 232 /* 233 * CTL_MACHDEP definitions. 234 */ 235 #define CPU_CACHELINE 1 236 #define CPU_TIMEBASE 2 237 #define CPU_CPUTEMP 3 238 #define CPU_PRINTFATALTRAPS 4 239 #define CPU_CACHEINFO 5 240 #define CPU_ALTIVEC 6 241 #define CPU_MODEL 7 242 #define CPU_POWERSAVE 8 243 #define CPU_MAXID 9 244 245 #define CTL_MACHDEP_NAMES { \ 246 { 0, 0 }, \ 247 { "cachelinesize", CTLTYPE_INT }, \ 248 { "timebase", CTLTYPE_INT }, \ 249 { "cputempature", CTLTYPE_INT }, \ 250 { "printfataltraps", CTLTYPE_INT }, \ 251 { "cacheinfo", CTLTYPE_STRUCT }, \ 252 { "altivec", CTLTYPE_INT }, \ 253 { "model", CTLTYPE_STRING }, \ 254 { "powersave", CTLTYPE_INT }, \ 255 } 256 257 #endif /* _POWERPC_CPU_H_ */ 258
Indexes created Wed Oct 15 16:09:53 GMT 2025