cpu.h revision 1.104
1 /* $NetBSD: cpu.h,v 1.104 2018/03/22 15:18:05 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _POWERPC_CPU_H_ 37 #define _POWERPC_CPU_H_ 38 39 struct cache_info { 40 int dcache_size; 41 int dcache_line_size; 42 int icache_size; 43 int icache_line_size; 44 }; 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_lockdebug.h" 49 #include "opt_modular.h" 50 #include "opt_multiprocessor.h" 51 #include "opt_ppcarch.h" 52 #endif 53 54 #ifdef _KERNEL 55 #include <sys/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #include <sys/param.h> 59 #include <sys/kernel.h> 60 #endif 61 62 #include <sys/cpu_data.h> 63 64 struct cpu_info { 65 struct cpu_data ci_data; /* MI per-cpu data */ 66 #ifdef _KERNEL 67 device_t ci_dev; /* device of corresponding cpu */ 68 struct cpu_softc *ci_softc; /* private cpu info */ 69 struct lwp *ci_curlwp; /* current owner of the processor */ 70 71 struct pcb *ci_curpcb; 72 struct pmap *ci_curpm; 73 struct lwp *ci_softlwps[SOFTINT_COUNT]; 74 int ci_cpuid; /* from SPR_PIR */ 75 76 int ci_want_resched; 77 volatile uint64_t ci_lastintr; 78 volatile u_long ci_lasttb; 79 volatile int ci_tickspending; 80 volatile int ci_cpl; 81 volatile int ci_iactive; 82 volatile int ci_idepth; 83 union { 84 #if !defined(PPC_BOOKE) && !defined(_MODULE) 85 volatile imask_t un1_ipending; 86 #define ci_ipending ci_un1.un1_ipending 87 #endif 88 uint64_t un1_pad64; 89 } ci_un1; 90 volatile uint32_t ci_pending_ipis; 91 int ci_mtx_oldspl; 92 int ci_mtx_count; 93 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 94 char *ci_intstk; 95 #endif 96 #define CI_SAVETEMP (0*CPUSAVE_LEN) 97 #define CI_SAVEDDB (1*CPUSAVE_LEN) 98 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) 99 #define CI_SAVEMMU (3*CPUSAVE_LEN) 100 #define CI_SAVEMAX (4*CPUSAVE_LEN) 101 #define CPUSAVE_LEN 8 102 #if !defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 103 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 104 #else 105 #define CPUSAVE_SIZE 128 106 #endif 107 #define CPUSAVE_R28 0 /* where r28 gets saved */ 108 #define CPUSAVE_R29 1 /* where r29 gets saved */ 109 #define CPUSAVE_R30 2 /* where r30 gets saved */ 110 #define CPUSAVE_R31 3 /* where r31 gets saved */ 111 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 112 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 113 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 114 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 115 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 116 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 117 register_t ci_savearea[CPUSAVE_SIZE]; 118 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 119 uint32_t ci_pmap_asid_cur; 120 union pmap_segtab *ci_pmap_segtabs[2]; 121 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 122 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 123 struct pmap_tlb_info *ci_tlb_info; 124 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 125 struct cache_info ci_ci; 126 void *ci_sysmon_cookie; 127 void (*ci_idlespin)(void); 128 uint32_t ci_khz; 129 struct evcnt ci_ev_clock; /* clock intrs */ 130 struct evcnt ci_ev_statclock; /* stat clock */ 131 struct evcnt ci_ev_traps; /* calls to trap() */ 132 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 133 struct evcnt ci_ev_udsi; /* user DSI traps */ 134 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 135 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 136 struct evcnt ci_ev_isi; /* user ISI traps */ 137 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 138 struct evcnt ci_ev_pgm; /* user PGM traps */ 139 struct evcnt ci_ev_debug; /* user debug traps */ 140 struct evcnt ci_ev_fpu; /* FPU traps */ 141 struct evcnt ci_ev_fpusw; /* FPU context switch */ 142 struct evcnt ci_ev_ali; /* Alignment traps */ 143 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 144 struct evcnt ci_ev_scalls; /* system call traps */ 145 struct evcnt ci_ev_vec; /* Altivec traps */ 146 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 147 struct evcnt ci_ev_umchk; /* user MCHK events */ 148 struct evcnt ci_ev_ipi; /* IPIs received */ 149 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 150 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 151 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 152 #endif /* _KERNEL */ 153 }; 154 #endif /* _KERNEL || _KMEMUSER */ 155 156 #ifdef _KERNEL 157 158 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 159 struct cpu_hatch_data { 160 int hatch_running; 161 device_t hatch_self; 162 struct cpu_info *hatch_ci; 163 uint32_t hatch_tbu; 164 uint32_t hatch_tbl; 165 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 166 uint64_t hatch_hid0; 167 #else 168 uint32_t hatch_hid0; 169 #endif 170 uint32_t hatch_pir; 171 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 172 uintptr_t hatch_asr; 173 uintptr_t hatch_sdr1; 174 uint32_t hatch_sr[16]; 175 uintptr_t hatch_ibatu[8], hatch_ibatl[8]; 176 uintptr_t hatch_dbatu[8], hatch_dbatl[8]; 177 #endif 178 #if defined(PPC_BOOKE) 179 vaddr_t hatch_sp; 180 u_int hatch_tlbidx; 181 #endif 182 }; 183 184 struct cpuset_info { 185 kcpuset_t *cpus_running; 186 kcpuset_t *cpus_hatched; 187 kcpuset_t *cpus_paused; 188 kcpuset_t *cpus_resumed; 189 kcpuset_t *cpus_halted; 190 }; 191 192 extern struct cpuset_info cpuset_info; 193 #endif /* MULTIPROCESSOR && !_MODULE */ 194 195 #if defined(MULTIPROCESSOR) || defined(_MODULE) 196 #define cpu_number() (curcpu()->ci_index + 0) 197 198 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 199 #define CPU_INFO_ITERATOR int 200 #define CPU_INFO_FOREACH(cii, ci) \ 201 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++ 202 203 #else 204 #define cpu_number() 0 205 206 #define CPU_IS_PRIMARY(ci) true 207 #define CPU_INFO_ITERATOR int 208 #define CPU_INFO_FOREACH(cii, ci) \ 209 (void)cii, ci = curcpu(); ci != NULL; ci = NULL 210 211 #endif /* MULTIPROCESSOR || _MODULE */ 212 213 extern struct cpu_info cpu_info[]; 214 215 static __inline struct cpu_info * curcpu(void) __pure; 216 static __inline struct cpu_info * 217 curcpu(void) 218 { 219 struct cpu_info *ci; 220 221 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 222 return ci; 223 } 224 225 #ifdef __clang__ 226 #define curlwp (curcpu()->ci_curlwp) 227 #else 228 register struct lwp *powerpc_curlwp __asm("r13"); 229 #define curlwp powerpc_curlwp 230 #endif 231 #define curpcb (curcpu()->ci_curpcb) 232 #define curpm (curcpu()->ci_curpm) 233 234 static __inline register_t 235 mfmsr(void) 236 { 237 register_t msr; 238 239 __asm volatile ("mfmsr %0" : "=r"(msr)); 240 return msr; 241 } 242 243 static __inline void 244 mtmsr(register_t msr) 245 { 246 //KASSERT(msr & PSL_CE); 247 //KASSERT(msr & PSL_DE); 248 __asm volatile ("mtmsr %0" : : "r"(msr)); 249 } 250 251 #if !defined(_MODULE) 252 static __inline uint32_t 253 mftbl(void) 254 { 255 uint32_t tbl; 256 257 __asm volatile ( 258 #ifdef PPC_IBM403 259 " mftblo %[tbl]" "\n" 260 #elif defined(PPC_BOOKE) 261 " mfspr %[tbl],268" "\n" 262 #else 263 " mftbl %[tbl]" "\n" 264 #endif 265 : [tbl] "=r" (tbl)); 266 267 return tbl; 268 } 269 270 static __inline uint64_t 271 mftb(void) 272 { 273 uint64_t tb; 274 275 #ifdef _ARCH_PPC64 276 __asm volatile ("mftb %0" : "=r"(tb)); 277 #else 278 int tmp; 279 280 __asm volatile ( 281 #ifdef PPC_IBM403 282 "1: mftbhi %[tb]" "\n" 283 " mftblo %L[tb]" "\n" 284 " mftbhi %[tmp]" "\n" 285 #elif defined(PPC_BOOKE) 286 "1: mfspr %[tb],269" "\n" 287 " mfspr %L[tb],268" "\n" 288 " mfspr %[tmp],269" "\n" 289 #else 290 "1: mftbu %[tb]" "\n" 291 " mftb %L[tb]" "\n" 292 " mftbu %[tmp]" "\n" 293 #endif 294 " cmplw %[tb],%[tmp]" "\n" 295 " bne- 1b" "\n" 296 : [tb] "=r" (tb), [tmp] "=r"(tmp) 297 :: "cr0"); 298 #endif 299 300 return tb; 301 } 302 303 static __inline uint32_t 304 mfrtcl(void) 305 { 306 uint32_t rtcl; 307 308 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 309 return rtcl; 310 } 311 312 static __inline void 313 mfrtc(uint32_t *rtcp) 314 { 315 uint32_t tmp; 316 317 __asm volatile ( 318 "1: mfrtcu %[rtcu]" "\n" 319 " mfrtcl %[rtcl]" "\n" 320 " mfrtcu %[tmp]" "\n" 321 " cmplw %[rtcu],%[tmp]" "\n" 322 " bne- 1b" 323 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 324 :: "cr0"); 325 } 326 327 static __inline uint64_t 328 rtc_nanosecs(void) 329 { 330 /* 331 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick. 332 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds. 333 * RTCU is seconds, 32 bits. 334 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns) 335 */ 336 uint64_t cycles; 337 uint32_t tmp[2]; 338 339 mfrtc(tmp); 340 341 cycles = tmp[0] * 1000000000; 342 cycles += (tmp[1] >> 7); 343 344 return cycles; 345 } 346 #endif /* !_MODULE */ 347 348 static __inline uint32_t 349 mfpvr(void) 350 { 351 uint32_t pvr; 352 353 __asm volatile ("mfpvr %0" : "=r"(pvr)); 354 return (pvr); 355 } 356 357 #ifdef _MODULE 358 extern const char __CPU_MAXNUM; 359 /* 360 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 361 * corresponding R_PPC_ADDR16_HI relocation. 362 */ 363 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 364 #endif /* _MODULE */ 365 366 #if !defined(_MODULE) 367 extern char *booted_kernel; 368 extern int powersave; 369 extern int cpu_timebase; 370 extern int cpu_printfataltraps; 371 372 struct cpu_info * 373 cpu_attach_common(device_t, int); 374 void cpu_setup(device_t, struct cpu_info *); 375 void cpu_identify(char *, size_t); 376 void cpu_probe_cache(void); 377 378 void dcache_wb_page(vaddr_t); 379 void dcache_wbinv_page(vaddr_t); 380 void dcache_inv_page(vaddr_t); 381 void dcache_zero_page(vaddr_t); 382 void icache_inv_page(vaddr_t); 383 void dcache_wb(vaddr_t, vsize_t); 384 void dcache_wbinv(vaddr_t, vsize_t); 385 void dcache_inv(vaddr_t, vsize_t); 386 void icache_inv(vaddr_t, vsize_t); 387 388 void * mapiodev(paddr_t, psize_t, bool); 389 void unmapiodev(vaddr_t, vsize_t); 390 391 #ifdef MULTIPROCESSOR 392 int md_setup_trampoline(volatile struct cpu_hatch_data *, 393 struct cpu_info *); 394 void md_presync_timebase(volatile struct cpu_hatch_data *); 395 void md_start_timebase(volatile struct cpu_hatch_data *); 396 void md_sync_timebase(volatile struct cpu_hatch_data *); 397 void md_setup_interrupts(void); 398 int cpu_spinup(device_t, struct cpu_info *); 399 register_t 400 cpu_hatch(void); 401 void cpu_spinup_trampoline(void); 402 void cpu_boot_secondary_processors(void); 403 void cpu_halt(void); 404 void cpu_halt_others(void); 405 void cpu_pause(struct trapframe *); 406 void cpu_pause_others(void); 407 void cpu_resume(cpuid_t); 408 void cpu_resume_others(void); 409 int cpu_is_paused(int); 410 void cpu_debug_dump(void); 411 #endif /* MULTIPROCESSOR */ 412 #endif /* !_MODULE */ 413 414 #define cpu_proc_fork(p1, p2) 415 416 #define DELAY(n) delay(n) 417 void delay(unsigned int); 418 419 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 420 #define CLKF_PC(cf) cpu_clkf_pc(cf) 421 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 422 423 bool cpu_clkf_usermode(const struct clockframe *); 424 vaddr_t cpu_clkf_pc(const struct clockframe *); 425 bool cpu_clkf_intr(const struct clockframe *); 426 427 #define LWP_PC(l) cpu_lwp_pc(l) 428 429 vaddr_t cpu_lwp_pc(struct lwp *); 430 431 void cpu_ast(struct lwp *, struct cpu_info *); 432 void * cpu_uarea_alloc(bool); 433 bool cpu_uarea_free(void *); 434 void cpu_need_resched(struct cpu_info *, int); 435 void cpu_signotify(struct lwp *); 436 void cpu_need_proftick(struct lwp *); 437 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 438 439 void cpu_fixup_stubs(void); 440 441 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 442 int cpu_get_dfs(void); 443 void cpu_set_dfs(int); 444 445 void oea_init(void (*)(void)); 446 void oea_startup(const char *); 447 void oea_dumpsys(void); 448 void oea_install_extint(void (*)(void)); 449 paddr_t kvtop(void *); 450 451 extern paddr_t msgbuf_paddr; 452 extern int cpu_altivec; 453 #endif 454 455 #endif /* _KERNEL */ 456 457 /* XXX The below breaks unified pmap on ppc32 */ 458 459 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 460 && (defined(_KERNEL) || defined(_STANDALONE)) 461 #if defined(PPC_IBM403) 462 #define CACHELINESIZE 16 463 #define MAXCACHELINESIZE 16 464 #elif defined (PPC_OEA64_BRIDGE) 465 #define CACHELINESIZE 128 466 #define MAXCACHELINESIZE 128 467 #else 468 #define CACHELINESIZE 32 469 #define MAXCACHELINESIZE 32 470 #endif /* PPC_OEA64_BRIDGE */ 471 #endif 472 473 void __syncicache(void *, size_t); 474 475 /* 476 * CTL_MACHDEP definitions. 477 */ 478 #define CPU_CACHELINE 1 479 #define CPU_TIMEBASE 2 480 #define CPU_CPUTEMP 3 481 #define CPU_PRINTFATALTRAPS 4 482 #define CPU_CACHEINFO 5 483 #define CPU_ALTIVEC 6 484 #define CPU_MODEL 7 485 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 486 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 487 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 488 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 489 #define CPU_MAXID 12 /* number of valid machdep ids */ 490 491 #endif /* _POWERPC_CPU_H_ */ 492
Indexes created Thu Sep 25 16:09:42 GMT 2025