cpu.h revision 1.105
1 /* $NetBSD: cpu.h,v 1.105 2018/05/04 17:01:29 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _POWERPC_CPU_H_ 37 #define _POWERPC_CPU_H_ 38 39 struct cache_info { 40 int dcache_size; 41 int dcache_line_size; 42 int icache_size; 43 int icache_line_size; 44 }; 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_lockdebug.h" 49 #include "opt_modular.h" 50 #include "opt_multiprocessor.h" 51 #include "opt_ppcarch.h" 52 #endif 53 54 #ifdef _KERNEL 55 #include <sys/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #include <sys/param.h> 59 #include <sys/kernel.h> 60 #endif 61 62 #include <sys/cpu_data.h> 63 64 struct cpu_info { 65 struct cpu_data ci_data; /* MI per-cpu data */ 66 #ifdef _KERNEL 67 device_t ci_dev; /* device of corresponding cpu */ 68 struct cpu_softc *ci_softc; /* private cpu info */ 69 struct lwp *ci_curlwp; /* current owner of the processor */ 70 71 struct pcb *ci_curpcb; 72 struct pmap *ci_curpm; 73 struct lwp *ci_softlwps[SOFTINT_COUNT]; 74 int ci_cpuid; /* from SPR_PIR */ 75 76 int ci_want_resched; 77 volatile uint64_t ci_lastintr; 78 volatile u_long ci_lasttb; 79 volatile int ci_tickspending; 80 volatile int ci_cpl; 81 volatile int ci_iactive; 82 volatile int ci_idepth; 83 union { 84 #if !defined(PPC_BOOKE) && !defined(_MODULE) 85 volatile imask_t un1_ipending; 86 #define ci_ipending ci_un1.un1_ipending 87 #endif 88 uint64_t un1_pad64; 89 } ci_un1; 90 volatile uint32_t ci_pending_ipis; 91 int ci_mtx_oldspl; 92 int ci_mtx_count; 93 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 94 char *ci_intstk; 95 #endif 96 #define CI_SAVETEMP (0*CPUSAVE_LEN) 97 #define CI_SAVEDDB (1*CPUSAVE_LEN) 98 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) 99 #define CI_SAVEMMU (3*CPUSAVE_LEN) 100 #define CI_SAVEMAX (4*CPUSAVE_LEN) 101 #define CPUSAVE_LEN 8 102 #if !defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 103 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 104 #else 105 #define CPUSAVE_SIZE 128 106 #endif 107 #define CPUSAVE_R28 0 /* where r28 gets saved */ 108 #define CPUSAVE_R29 1 /* where r29 gets saved */ 109 #define CPUSAVE_R30 2 /* where r30 gets saved */ 110 #define CPUSAVE_R31 3 /* where r31 gets saved */ 111 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 112 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 113 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 114 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 115 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 116 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 117 register_t ci_savearea[CPUSAVE_SIZE]; 118 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 119 uint32_t ci_pmap_asid_cur; 120 union pmap_segtab *ci_pmap_segtabs[2]; 121 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 122 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 123 struct pmap_tlb_info *ci_tlb_info; 124 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 125 struct cache_info ci_ci; 126 void *ci_sysmon_cookie; 127 void (*ci_idlespin)(void); 128 uint32_t ci_khz; 129 struct evcnt ci_ev_clock; /* clock intrs */ 130 struct evcnt ci_ev_statclock; /* stat clock */ 131 struct evcnt ci_ev_traps; /* calls to trap() */ 132 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 133 struct evcnt ci_ev_udsi; /* user DSI traps */ 134 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 135 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 136 struct evcnt ci_ev_isi; /* user ISI traps */ 137 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 138 struct evcnt ci_ev_pgm; /* user PGM traps */ 139 struct evcnt ci_ev_debug; /* user debug traps */ 140 struct evcnt ci_ev_fpu; /* FPU traps */ 141 struct evcnt ci_ev_fpusw; /* FPU context switch */ 142 struct evcnt ci_ev_ali; /* Alignment traps */ 143 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 144 struct evcnt ci_ev_scalls; /* system call traps */ 145 struct evcnt ci_ev_vec; /* Altivec traps */ 146 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 147 struct evcnt ci_ev_umchk; /* user MCHK events */ 148 struct evcnt ci_ev_ipi; /* IPIs received */ 149 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 150 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 151 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 152 #endif /* _KERNEL */ 153 }; 154 #endif /* _KERNEL || _KMEMUSER */ 155 156 #ifdef _KERNEL 157 158 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 159 struct cpu_hatch_data { 160 int hatch_running; 161 device_t hatch_self; 162 struct cpu_info *hatch_ci; 163 uint32_t hatch_tbu; 164 uint32_t hatch_tbl; 165 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 166 uint64_t hatch_hid0; 167 uint64_t hatch_hid4; 168 uint64_t hatch_hid5; 169 #else 170 uint32_t hatch_hid0; 171 #endif 172 uint32_t hatch_pir; 173 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 174 uintptr_t hatch_asr; 175 uintptr_t hatch_sdr1; 176 uint32_t hatch_sr[16]; 177 uintptr_t hatch_ibatu[8], hatch_ibatl[8]; 178 uintptr_t hatch_dbatu[8], hatch_dbatl[8]; 179 #endif 180 #if defined(PPC_BOOKE) 181 vaddr_t hatch_sp; 182 u_int hatch_tlbidx; 183 #endif 184 }; 185 186 struct cpuset_info { 187 kcpuset_t *cpus_running; 188 kcpuset_t *cpus_hatched; 189 kcpuset_t *cpus_paused; 190 kcpuset_t *cpus_resumed; 191 kcpuset_t *cpus_halted; 192 }; 193 194 extern struct cpuset_info cpuset_info; 195 #endif /* MULTIPROCESSOR && !_MODULE */ 196 197 #if defined(MULTIPROCESSOR) || defined(_MODULE) 198 #define cpu_number() (curcpu()->ci_index + 0) 199 200 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 201 #define CPU_INFO_ITERATOR int 202 #define CPU_INFO_FOREACH(cii, ci) \ 203 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++ 204 205 #else 206 #define cpu_number() 0 207 208 #define CPU_IS_PRIMARY(ci) true 209 #define CPU_INFO_ITERATOR int 210 #define CPU_INFO_FOREACH(cii, ci) \ 211 (void)cii, ci = curcpu(); ci != NULL; ci = NULL 212 213 #endif /* MULTIPROCESSOR || _MODULE */ 214 215 extern struct cpu_info cpu_info[]; 216 217 static __inline struct cpu_info * curcpu(void) __pure; 218 static __inline struct cpu_info * 219 curcpu(void) 220 { 221 struct cpu_info *ci; 222 223 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 224 return ci; 225 } 226 227 #ifdef __clang__ 228 #define curlwp (curcpu()->ci_curlwp) 229 #else 230 register struct lwp *powerpc_curlwp __asm("r13"); 231 #define curlwp powerpc_curlwp 232 #endif 233 #define curpcb (curcpu()->ci_curpcb) 234 #define curpm (curcpu()->ci_curpm) 235 236 static __inline register_t 237 mfmsr(void) 238 { 239 register_t msr; 240 241 __asm volatile ("mfmsr %0" : "=r"(msr)); 242 return msr; 243 } 244 245 static __inline void 246 mtmsr(register_t msr) 247 { 248 //KASSERT(msr & PSL_CE); 249 //KASSERT(msr & PSL_DE); 250 __asm volatile ("mtmsr %0" : : "r"(msr)); 251 } 252 253 #if !defined(_MODULE) 254 static __inline uint32_t 255 mftbl(void) 256 { 257 uint32_t tbl; 258 259 __asm volatile ( 260 #ifdef PPC_IBM403 261 " mftblo %[tbl]" "\n" 262 #elif defined(PPC_BOOKE) 263 " mfspr %[tbl],268" "\n" 264 #else 265 " mftbl %[tbl]" "\n" 266 #endif 267 : [tbl] "=r" (tbl)); 268 269 return tbl; 270 } 271 272 static __inline uint64_t 273 mftb(void) 274 { 275 uint64_t tb; 276 277 #ifdef _ARCH_PPC64 278 __asm volatile ("mftb %0" : "=r"(tb)); 279 #else 280 int tmp; 281 282 __asm volatile ( 283 #ifdef PPC_IBM403 284 "1: mftbhi %[tb]" "\n" 285 " mftblo %L[tb]" "\n" 286 " mftbhi %[tmp]" "\n" 287 #elif defined(PPC_BOOKE) 288 "1: mfspr %[tb],269" "\n" 289 " mfspr %L[tb],268" "\n" 290 " mfspr %[tmp],269" "\n" 291 #else 292 "1: mftbu %[tb]" "\n" 293 " mftb %L[tb]" "\n" 294 " mftbu %[tmp]" "\n" 295 #endif 296 " cmplw %[tb],%[tmp]" "\n" 297 " bne- 1b" "\n" 298 : [tb] "=r" (tb), [tmp] "=r"(tmp) 299 :: "cr0"); 300 #endif 301 302 return tb; 303 } 304 305 static __inline uint32_t 306 mfrtcl(void) 307 { 308 uint32_t rtcl; 309 310 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 311 return rtcl; 312 } 313 314 static __inline void 315 mfrtc(uint32_t *rtcp) 316 { 317 uint32_t tmp; 318 319 __asm volatile ( 320 "1: mfrtcu %[rtcu]" "\n" 321 " mfrtcl %[rtcl]" "\n" 322 " mfrtcu %[tmp]" "\n" 323 " cmplw %[rtcu],%[tmp]" "\n" 324 " bne- 1b" 325 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 326 :: "cr0"); 327 } 328 329 static __inline uint64_t 330 rtc_nanosecs(void) 331 { 332 /* 333 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick. 334 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds. 335 * RTCU is seconds, 32 bits. 336 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns) 337 */ 338 uint64_t cycles; 339 uint32_t tmp[2]; 340 341 mfrtc(tmp); 342 343 cycles = tmp[0] * 1000000000; 344 cycles += (tmp[1] >> 7); 345 346 return cycles; 347 } 348 #endif /* !_MODULE */ 349 350 static __inline uint32_t 351 mfpvr(void) 352 { 353 uint32_t pvr; 354 355 __asm volatile ("mfpvr %0" : "=r"(pvr)); 356 return (pvr); 357 } 358 359 #ifdef _MODULE 360 extern const char __CPU_MAXNUM; 361 /* 362 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 363 * corresponding R_PPC_ADDR16_HI relocation. 364 */ 365 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 366 #endif /* _MODULE */ 367 368 #if !defined(_MODULE) 369 extern char *booted_kernel; 370 extern int powersave; 371 extern int cpu_timebase; 372 extern int cpu_printfataltraps; 373 374 struct cpu_info * 375 cpu_attach_common(device_t, int); 376 void cpu_setup(device_t, struct cpu_info *); 377 void cpu_identify(char *, size_t); 378 void cpu_probe_cache(void); 379 380 void dcache_wb_page(vaddr_t); 381 void dcache_wbinv_page(vaddr_t); 382 void dcache_inv_page(vaddr_t); 383 void dcache_zero_page(vaddr_t); 384 void icache_inv_page(vaddr_t); 385 void dcache_wb(vaddr_t, vsize_t); 386 void dcache_wbinv(vaddr_t, vsize_t); 387 void dcache_inv(vaddr_t, vsize_t); 388 void icache_inv(vaddr_t, vsize_t); 389 390 void * mapiodev(paddr_t, psize_t, bool); 391 void unmapiodev(vaddr_t, vsize_t); 392 393 #ifdef MULTIPROCESSOR 394 int md_setup_trampoline(volatile struct cpu_hatch_data *, 395 struct cpu_info *); 396 void md_presync_timebase(volatile struct cpu_hatch_data *); 397 void md_start_timebase(volatile struct cpu_hatch_data *); 398 void md_sync_timebase(volatile struct cpu_hatch_data *); 399 void md_setup_interrupts(void); 400 int cpu_spinup(device_t, struct cpu_info *); 401 register_t 402 cpu_hatch(void); 403 void cpu_spinup_trampoline(void); 404 void cpu_boot_secondary_processors(void); 405 void cpu_halt(void); 406 void cpu_halt_others(void); 407 void cpu_pause(struct trapframe *); 408 void cpu_pause_others(void); 409 void cpu_resume(cpuid_t); 410 void cpu_resume_others(void); 411 int cpu_is_paused(int); 412 void cpu_debug_dump(void); 413 #endif /* MULTIPROCESSOR */ 414 #endif /* !_MODULE */ 415 416 #define cpu_proc_fork(p1, p2) 417 418 #define DELAY(n) delay(n) 419 void delay(unsigned int); 420 421 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 422 #define CLKF_PC(cf) cpu_clkf_pc(cf) 423 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 424 425 bool cpu_clkf_usermode(const struct clockframe *); 426 vaddr_t cpu_clkf_pc(const struct clockframe *); 427 bool cpu_clkf_intr(const struct clockframe *); 428 429 #define LWP_PC(l) cpu_lwp_pc(l) 430 431 vaddr_t cpu_lwp_pc(struct lwp *); 432 433 void cpu_ast(struct lwp *, struct cpu_info *); 434 void * cpu_uarea_alloc(bool); 435 bool cpu_uarea_free(void *); 436 void cpu_need_resched(struct cpu_info *, int); 437 void cpu_signotify(struct lwp *); 438 void cpu_need_proftick(struct lwp *); 439 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 440 441 void cpu_fixup_stubs(void); 442 443 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 444 int cpu_get_dfs(void); 445 void cpu_set_dfs(int); 446 447 void oea_init(void (*)(void)); 448 void oea_startup(const char *); 449 void oea_dumpsys(void); 450 void oea_install_extint(void (*)(void)); 451 paddr_t kvtop(void *); 452 453 extern paddr_t msgbuf_paddr; 454 extern int cpu_altivec; 455 #endif 456 457 #endif /* _KERNEL */ 458 459 /* XXX The below breaks unified pmap on ppc32 */ 460 461 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 462 && (defined(_KERNEL) || defined(_STANDALONE)) 463 #if defined(PPC_IBM403) 464 #define CACHELINESIZE 16 465 #define MAXCACHELINESIZE 16 466 #elif defined (PPC_OEA64_BRIDGE) 467 #define CACHELINESIZE 128 468 #define MAXCACHELINESIZE 128 469 #else 470 #define CACHELINESIZE 32 471 #define MAXCACHELINESIZE 32 472 #endif /* PPC_OEA64_BRIDGE */ 473 #endif 474 475 void __syncicache(void *, size_t); 476 477 /* 478 * CTL_MACHDEP definitions. 479 */ 480 #define CPU_CACHELINE 1 481 #define CPU_TIMEBASE 2 482 #define CPU_CPUTEMP 3 483 #define CPU_PRINTFATALTRAPS 4 484 #define CPU_CACHEINFO 5 485 #define CPU_ALTIVEC 6 486 #define CPU_MODEL 7 487 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 488 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 489 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 490 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 491 #define CPU_MAXID 12 /* number of valid machdep ids */ 492 493 #endif /* _POWERPC_CPU_H_ */ 494
Indexes created Tue Sep 23 02:09:52 GMT 2025