cpu.h revision 1.116
1 /* $NetBSD: cpu.h,v 1.116 2021/02/03 10:37:05 rin Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _POWERPC_CPU_H_ 37 #define _POWERPC_CPU_H_ 38 39 struct cache_info { 40 int dcache_size; 41 int dcache_line_size; 42 int icache_size; 43 int icache_line_size; 44 }; 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_modular.h" 49 #include "opt_multiprocessor.h" 50 #include "opt_ppcarch.h" 51 #endif 52 53 #ifdef _KERNEL 54 #include <sys/intr.h> 55 #include <sys/device_if.h> 56 #include <sys/evcnt.h> 57 #include <sys/param.h> 58 #include <sys/kernel.h> 59 #endif 60 61 #include <sys/cpu_data.h> 62 63 #ifdef _KERNEL 64 #define CI_SAVETEMP (0*CPUSAVE_LEN) 65 #define CI_SAVEDDB (1*CPUSAVE_LEN) 66 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) /* obsolete */ 67 #define CI_SAVEMMU (3*CPUSAVE_LEN) 68 #define CI_SAVEMAX (4*CPUSAVE_LEN) 69 #define CPUSAVE_LEN 8 70 #if defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 71 #define CPUSAVE_SIZE 128 72 #else 73 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 74 CTASSERT(CPUSAVE_SIZE >= 128); 75 #endif 76 #define CPUSAVE_R28 0 /* where r28 gets saved */ 77 #define CPUSAVE_R29 1 /* where r29 gets saved */ 78 #define CPUSAVE_R30 2 /* where r30 gets saved */ 79 #define CPUSAVE_R31 3 /* where r31 gets saved */ 80 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 81 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 82 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 83 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 84 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 85 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 86 #endif /* _KERNEL */ 87 88 struct cpu_info { 89 struct cpu_data ci_data; /* MI per-cpu data */ 90 #ifdef _KERNEL 91 device_t ci_dev; /* device of corresponding cpu */ 92 struct cpu_softc *ci_softc; /* private cpu info */ 93 struct lwp *ci_curlwp; /* current owner of the processor */ 94 struct lwp *ci_onproc; /* current user LWP / kthread */ 95 struct pcb *ci_curpcb; 96 struct pmap *ci_curpm; 97 struct lwp *ci_softlwps[SOFTINT_COUNT]; 98 int ci_cpuid; /* from SPR_PIR */ 99 100 int ci_want_resched; 101 volatile uint64_t ci_lastintr; 102 volatile u_long ci_lasttb; 103 volatile int ci_tickspending; 104 volatile int ci_cpl; 105 volatile int ci_iactive; 106 volatile int ci_idepth; 107 union { 108 #if !defined(PPC_BOOKE) && !defined(_MODULE) 109 volatile imask_t un1_ipending; 110 #define ci_ipending ci_un1.un1_ipending 111 #endif 112 uint64_t un1_pad64; 113 } ci_un1; 114 volatile uint32_t ci_pending_ipis; 115 int ci_mtx_oldspl; 116 int ci_mtx_count; 117 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 118 char *ci_intstk; 119 #endif 120 121 register_t ci_savearea[CPUSAVE_SIZE]; 122 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 123 uint32_t ci_pmap_asid_cur; 124 union pmap_segtab *ci_pmap_segtabs[2]; 125 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 126 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 127 struct pmap_tlb_info *ci_tlb_info; 128 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 129 struct cache_info ci_ci; 130 void *ci_sysmon_cookie; 131 void (*ci_idlespin)(void); 132 uint32_t ci_khz; 133 struct evcnt ci_ev_clock; /* clock intrs */ 134 struct evcnt ci_ev_statclock; /* stat clock */ 135 struct evcnt ci_ev_traps; /* calls to trap() */ 136 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 137 struct evcnt ci_ev_udsi; /* user DSI traps */ 138 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 139 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 140 struct evcnt ci_ev_isi; /* user ISI traps */ 141 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 142 struct evcnt ci_ev_pgm; /* user PGM traps */ 143 struct evcnt ci_ev_debug; /* user debug traps */ 144 struct evcnt ci_ev_fpu; /* FPU traps */ 145 struct evcnt ci_ev_fpusw; /* FPU context switch */ 146 struct evcnt ci_ev_ali; /* Alignment traps */ 147 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 148 struct evcnt ci_ev_scalls; /* system call traps */ 149 struct evcnt ci_ev_vec; /* Altivec traps */ 150 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 151 struct evcnt ci_ev_umchk; /* user MCHK events */ 152 struct evcnt ci_ev_ipi; /* IPIs received */ 153 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 154 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 155 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 156 #endif /* _KERNEL */ 157 }; 158 #endif /* _KERNEL || _KMEMUSER */ 159 160 #ifdef _KERNEL 161 162 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 163 struct cpu_hatch_data { 164 int hatch_running; 165 device_t hatch_self; 166 struct cpu_info *hatch_ci; 167 uint32_t hatch_tbu; 168 uint32_t hatch_tbl; 169 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 170 uint64_t hatch_hid0; 171 uint64_t hatch_hid1; 172 uint64_t hatch_hid4; 173 uint64_t hatch_hid5; 174 #else 175 uint32_t hatch_hid0; 176 #endif 177 uint32_t hatch_pir; 178 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 179 uintptr_t hatch_asr; 180 uintptr_t hatch_sdr1; 181 uint32_t hatch_sr[16]; 182 uintptr_t hatch_ibatu[8], hatch_ibatl[8]; 183 uintptr_t hatch_dbatu[8], hatch_dbatl[8]; 184 #endif 185 #if defined(PPC_BOOKE) 186 vaddr_t hatch_sp; 187 u_int hatch_tlbidx; 188 #endif 189 }; 190 191 struct cpuset_info { 192 kcpuset_t *cpus_running; 193 kcpuset_t *cpus_hatched; 194 kcpuset_t *cpus_paused; 195 kcpuset_t *cpus_resumed; 196 kcpuset_t *cpus_halted; 197 }; 198 199 extern struct cpuset_info cpuset_info; 200 #endif /* MULTIPROCESSOR && !_MODULE */ 201 202 #if defined(MULTIPROCESSOR) || defined(_MODULE) 203 #define cpu_number() (curcpu()->ci_index + 0) 204 205 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 206 #define CPU_INFO_ITERATOR int 207 #define CPU_INFO_FOREACH(cii, ci) \ 208 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++ 209 210 #else 211 #define cpu_number() 0 212 213 #define CPU_IS_PRIMARY(ci) true 214 #define CPU_INFO_ITERATOR int 215 #define CPU_INFO_FOREACH(cii, ci) \ 216 (void)cii, ci = curcpu(); ci != NULL; ci = NULL 217 218 #endif /* MULTIPROCESSOR || _MODULE */ 219 220 extern struct cpu_info cpu_info[]; 221 222 static __inline struct cpu_info * curcpu(void) __pure; 223 static __inline struct cpu_info * 224 curcpu(void) 225 { 226 struct cpu_info *ci; 227 228 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 229 return ci; 230 } 231 232 #ifdef __clang__ 233 #define curlwp (curcpu()->ci_curlwp) 234 #else 235 register struct lwp *powerpc_curlwp __asm("r13"); 236 #define curlwp powerpc_curlwp 237 #endif 238 #define curpcb (curcpu()->ci_curpcb) 239 #define curpm (curcpu()->ci_curpm) 240 241 static __inline register_t 242 mfmsr(void) 243 { 244 register_t msr; 245 246 __asm volatile ("mfmsr %0" : "=r"(msr)); 247 return msr; 248 } 249 250 static __inline void 251 mtmsr(register_t msr) 252 { 253 //KASSERT(msr & PSL_CE); 254 //KASSERT(msr & PSL_DE); 255 __asm volatile ("mtmsr %0" : : "r"(msr)); 256 } 257 258 #if !defined(_MODULE) 259 static __inline uint32_t 260 mftbl(void) 261 { 262 uint32_t tbl; 263 264 __asm volatile ( 265 #ifdef PPC_IBM403 266 " mftblo %[tbl]" "\n" 267 #elif defined(PPC_BOOKE) 268 " mfspr %[tbl],268" "\n" 269 #else 270 " mftbl %[tbl]" "\n" 271 #endif 272 : [tbl] "=r" (tbl)); 273 274 return tbl; 275 } 276 277 static __inline uint64_t 278 mftb(void) 279 { 280 uint64_t tb; 281 282 #ifdef _ARCH_PPC64 283 __asm volatile ("mftb %0" : "=r"(tb)); 284 #else 285 int tmp; 286 287 __asm volatile ( 288 #ifdef PPC_IBM403 289 "1: mftbhi %[tb]" "\n" 290 " mftblo %L[tb]" "\n" 291 " mftbhi %[tmp]" "\n" 292 #elif defined(PPC_BOOKE) 293 "1: mfspr %[tb],269" "\n" 294 " mfspr %L[tb],268" "\n" 295 " mfspr %[tmp],269" "\n" 296 #else 297 "1: mftbu %[tb]" "\n" 298 " mftb %L[tb]" "\n" 299 " mftbu %[tmp]" "\n" 300 #endif 301 " cmplw %[tb],%[tmp]" "\n" 302 " bne- 1b" "\n" 303 : [tb] "=r" (tb), [tmp] "=r"(tmp) 304 :: "cr0"); 305 #endif 306 307 return tb; 308 } 309 310 static __inline uint32_t 311 mfrtcl(void) 312 { 313 uint32_t rtcl; 314 315 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 316 return rtcl; 317 } 318 319 static __inline void 320 mfrtc(uint32_t *rtcp) 321 { 322 uint32_t tmp; 323 324 __asm volatile ( 325 "1: mfrtcu %[rtcu]" "\n" 326 " mfrtcl %[rtcl]" "\n" 327 " mfrtcu %[tmp]" "\n" 328 " cmplw %[rtcu],%[tmp]" "\n" 329 " bne- 1b" 330 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 331 :: "cr0"); 332 } 333 334 static __inline uint64_t 335 rtc_nanosecs(void) 336 { 337 /* 338 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick. 339 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds. 340 * RTCU is seconds, 32 bits. 341 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns) 342 */ 343 uint64_t cycles; 344 uint32_t tmp[2]; 345 346 mfrtc(tmp); 347 348 cycles = tmp[0] * 1000000000; 349 cycles += (tmp[1] >> 7); 350 351 return cycles; 352 } 353 #endif /* !_MODULE */ 354 355 static __inline uint32_t 356 mfpvr(void) 357 { 358 uint32_t pvr; 359 360 __asm volatile ("mfpvr %0" : "=r"(pvr)); 361 return (pvr); 362 } 363 364 #ifdef _MODULE 365 extern const char __CPU_MAXNUM; 366 /* 367 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 368 * corresponding R_PPC_ADDR16_HI relocation. 369 */ 370 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 371 #endif /* _MODULE */ 372 373 #if !defined(_MODULE) 374 extern char *booted_kernel; 375 extern int powersave; 376 extern int cpu_timebase; 377 extern int cpu_printfataltraps; 378 379 struct cpu_info * 380 cpu_attach_common(device_t, int); 381 void cpu_setup(device_t, struct cpu_info *); 382 void cpu_identify(char *, size_t); 383 void cpu_probe_cache(void); 384 385 void dcache_wb_page(vaddr_t); 386 void dcache_wbinv_page(vaddr_t); 387 void dcache_inv_page(vaddr_t); 388 void dcache_zero_page(vaddr_t); 389 void icache_inv_page(vaddr_t); 390 void dcache_wb(vaddr_t, vsize_t); 391 void dcache_wbinv(vaddr_t, vsize_t); 392 void dcache_inv(vaddr_t, vsize_t); 393 void icache_inv(vaddr_t, vsize_t); 394 395 void * mapiodev(paddr_t, psize_t, bool); 396 void unmapiodev(vaddr_t, vsize_t); 397 398 int emulate_mxmsr(struct lwp *, struct trapframe *, uint32_t); 399 400 #ifdef MULTIPROCESSOR 401 int md_setup_trampoline(volatile struct cpu_hatch_data *, 402 struct cpu_info *); 403 void md_presync_timebase(volatile struct cpu_hatch_data *); 404 void md_start_timebase(volatile struct cpu_hatch_data *); 405 void md_sync_timebase(volatile struct cpu_hatch_data *); 406 void md_setup_interrupts(void); 407 int cpu_spinup(device_t, struct cpu_info *); 408 register_t 409 cpu_hatch(void); 410 void cpu_spinup_trampoline(void); 411 void cpu_boot_secondary_processors(void); 412 void cpu_halt(void); 413 void cpu_halt_others(void); 414 void cpu_pause(struct trapframe *); 415 void cpu_pause_others(void); 416 void cpu_resume(cpuid_t); 417 void cpu_resume_others(void); 418 int cpu_is_paused(int); 419 void cpu_debug_dump(void); 420 #endif /* MULTIPROCESSOR */ 421 #endif /* !_MODULE */ 422 423 #define cpu_proc_fork(p1, p2) 424 425 #ifndef __HIDE_DELAY 426 #define DELAY(n) delay(n) 427 void delay(unsigned int); 428 #endif /* __HIDE_DELAY */ 429 430 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 431 #define CLKF_PC(cf) cpu_clkf_pc(cf) 432 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 433 434 bool cpu_clkf_usermode(const struct clockframe *); 435 vaddr_t cpu_clkf_pc(const struct clockframe *); 436 bool cpu_clkf_intr(const struct clockframe *); 437 438 #define LWP_PC(l) cpu_lwp_pc(l) 439 440 vaddr_t cpu_lwp_pc(struct lwp *); 441 442 void cpu_ast(struct lwp *, struct cpu_info *); 443 void * cpu_uarea_alloc(bool); 444 bool cpu_uarea_free(void *); 445 void cpu_signotify(struct lwp *); 446 void cpu_need_proftick(struct lwp *); 447 448 void cpu_fixup_stubs(void); 449 450 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 451 int cpu_get_dfs(void); 452 void cpu_set_dfs(int); 453 454 void oea_init(void (*)(void)); 455 void oea_startup(const char *); 456 void oea_dumpsys(void); 457 void oea_install_extint(void (*)(void)); 458 paddr_t kvtop(void *); 459 460 extern paddr_t msgbuf_paddr; 461 extern int cpu_altivec; 462 #endif 463 464 #endif /* _KERNEL */ 465 466 /* XXX The below breaks unified pmap on ppc32 */ 467 468 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 469 && (defined(_KERNEL) || defined(_STANDALONE)) 470 #if defined(PPC_IBM403) 471 #define CACHELINESIZE 16 472 #define MAXCACHELINESIZE 16 473 #elif defined (PPC_OEA64_BRIDGE) 474 #define CACHELINESIZE 128 475 #define MAXCACHELINESIZE 128 476 #else 477 #define CACHELINESIZE 32 478 #define MAXCACHELINESIZE 32 479 #endif /* PPC_OEA64_BRIDGE */ 480 #endif 481 482 void __syncicache(void *, size_t); 483 484 /* 485 * CTL_MACHDEP definitions. 486 */ 487 #define CPU_CACHELINE 1 488 #define CPU_TIMEBASE 2 489 #define CPU_CPUTEMP 3 490 #define CPU_PRINTFATALTRAPS 4 491 #define CPU_CACHEINFO 5 492 #define CPU_ALTIVEC 6 493 #define CPU_MODEL 7 494 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 495 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 496 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 497 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 498 #define CPU_FPU 12 499 500 #endif /* _POWERPC_CPU_H_ */ 501
Indexes created Tue Sep 23 22:09:46 GMT 2025