cpu.h revision 1.117
1 /* $NetBSD: cpu.h,v 1.117 2021/02/24 16:42:38 thorpej Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _POWERPC_CPU_H_ 37 #define _POWERPC_CPU_H_ 38 39 struct cache_info { 40 int dcache_size; 41 int dcache_line_size; 42 int icache_size; 43 int icache_line_size; 44 }; 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_modular.h" 49 #include "opt_multiprocessor.h" 50 #include "opt_ppcarch.h" 51 #endif 52 53 #ifdef _KERNEL 54 #include <sys/intr.h> 55 #include <sys/device_if.h> 56 #include <sys/evcnt.h> 57 #include <sys/param.h> 58 #include <sys/kernel.h> 59 #endif 60 61 #include <sys/cpu_data.h> 62 63 #ifdef _KERNEL 64 #define CI_SAVETEMP (0*CPUSAVE_LEN) 65 #define CI_SAVEDDB (1*CPUSAVE_LEN) 66 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) /* obsolete */ 67 #define CI_SAVEMMU (3*CPUSAVE_LEN) 68 #define CI_SAVEMAX (4*CPUSAVE_LEN) 69 #define CPUSAVE_LEN 8 70 #if defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 71 #define CPUSAVE_SIZE 128 72 #else 73 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 74 CTASSERT(CPUSAVE_SIZE >= 128); 75 #endif 76 #define CPUSAVE_R28 0 /* where r28 gets saved */ 77 #define CPUSAVE_R29 1 /* where r29 gets saved */ 78 #define CPUSAVE_R30 2 /* where r30 gets saved */ 79 #define CPUSAVE_R31 3 /* where r31 gets saved */ 80 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 81 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 82 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 83 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 84 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 85 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 86 #endif /* _KERNEL */ 87 88 struct cpu_info { 89 struct cpu_data ci_data; /* MI per-cpu data */ 90 #ifdef _KERNEL 91 device_t ci_dev; /* device of corresponding cpu */ 92 struct cpu_softc *ci_softc; /* private cpu info */ 93 struct lwp *ci_curlwp; /* current owner of the processor */ 94 struct lwp *ci_onproc; /* current user LWP / kthread */ 95 struct pcb *ci_curpcb; 96 struct pmap *ci_curpm; 97 #if defined(PPC_OEA) || defined(PPC_OEA601) || defined(PPC_OEA64) || \ 98 defined(PPC_OEA64_BRIDGE) || defined(MODULAR) || defined(_MODULE) 99 void *ci_battable; /* BAT table in use by this CPU */ 100 #endif 101 struct lwp *ci_softlwps[SOFTINT_COUNT]; 102 int ci_cpuid; /* from SPR_PIR */ 103 104 int ci_want_resched; 105 volatile uint64_t ci_lastintr; 106 volatile u_long ci_lasttb; 107 volatile int ci_tickspending; 108 volatile int ci_cpl; 109 volatile int ci_iactive; 110 volatile int ci_idepth; 111 union { 112 #if !defined(PPC_BOOKE) && !defined(_MODULE) 113 volatile imask_t un1_ipending; 114 #define ci_ipending ci_un1.un1_ipending 115 #endif 116 uint64_t un1_pad64; 117 } ci_un1; 118 volatile uint32_t ci_pending_ipis; 119 int ci_mtx_oldspl; 120 int ci_mtx_count; 121 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 122 char *ci_intstk; 123 #endif 124 125 register_t ci_savearea[CPUSAVE_SIZE]; 126 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 127 uint32_t ci_pmap_asid_cur; 128 union pmap_segtab *ci_pmap_segtabs[2]; 129 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 130 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 131 struct pmap_tlb_info *ci_tlb_info; 132 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 133 struct cache_info ci_ci; 134 void *ci_sysmon_cookie; 135 void (*ci_idlespin)(void); 136 uint32_t ci_khz; 137 struct evcnt ci_ev_clock; /* clock intrs */ 138 struct evcnt ci_ev_statclock; /* stat clock */ 139 struct evcnt ci_ev_traps; /* calls to trap() */ 140 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 141 struct evcnt ci_ev_udsi; /* user DSI traps */ 142 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 143 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 144 struct evcnt ci_ev_isi; /* user ISI traps */ 145 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 146 struct evcnt ci_ev_pgm; /* user PGM traps */ 147 struct evcnt ci_ev_debug; /* user debug traps */ 148 struct evcnt ci_ev_fpu; /* FPU traps */ 149 struct evcnt ci_ev_fpusw; /* FPU context switch */ 150 struct evcnt ci_ev_ali; /* Alignment traps */ 151 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 152 struct evcnt ci_ev_scalls; /* system call traps */ 153 struct evcnt ci_ev_vec; /* Altivec traps */ 154 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 155 struct evcnt ci_ev_umchk; /* user MCHK events */ 156 struct evcnt ci_ev_ipi; /* IPIs received */ 157 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 158 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 159 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 160 #endif /* _KERNEL */ 161 }; 162 #endif /* _KERNEL || _KMEMUSER */ 163 164 #ifdef _KERNEL 165 166 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 167 struct cpu_hatch_data { 168 int hatch_running; 169 device_t hatch_self; 170 struct cpu_info *hatch_ci; 171 uint32_t hatch_tbu; 172 uint32_t hatch_tbl; 173 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 174 uint64_t hatch_hid0; 175 uint64_t hatch_hid1; 176 uint64_t hatch_hid4; 177 uint64_t hatch_hid5; 178 #else 179 uint32_t hatch_hid0; 180 #endif 181 uint32_t hatch_pir; 182 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 183 uintptr_t hatch_asr; 184 uintptr_t hatch_sdr1; 185 uint32_t hatch_sr[16]; 186 uintptr_t hatch_ibatu[8], hatch_ibatl[8]; 187 uintptr_t hatch_dbatu[8], hatch_dbatl[8]; 188 #endif 189 #if defined(PPC_BOOKE) 190 vaddr_t hatch_sp; 191 u_int hatch_tlbidx; 192 #endif 193 }; 194 195 struct cpuset_info { 196 kcpuset_t *cpus_running; 197 kcpuset_t *cpus_hatched; 198 kcpuset_t *cpus_paused; 199 kcpuset_t *cpus_resumed; 200 kcpuset_t *cpus_halted; 201 }; 202 203 extern struct cpuset_info cpuset_info; 204 #endif /* MULTIPROCESSOR && !_MODULE */ 205 206 #if defined(MULTIPROCESSOR) || defined(_MODULE) 207 #define cpu_number() (curcpu()->ci_index + 0) 208 209 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 210 #define CPU_INFO_ITERATOR int 211 #define CPU_INFO_FOREACH(cii, ci) \ 212 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++ 213 214 #else 215 #define cpu_number() 0 216 217 #define CPU_IS_PRIMARY(ci) true 218 #define CPU_INFO_ITERATOR int 219 #define CPU_INFO_FOREACH(cii, ci) \ 220 (void)cii, ci = curcpu(); ci != NULL; ci = NULL 221 222 #endif /* MULTIPROCESSOR || _MODULE */ 223 224 extern struct cpu_info cpu_info[]; 225 226 static __inline struct cpu_info * curcpu(void) __pure; 227 static __inline struct cpu_info * 228 curcpu(void) 229 { 230 struct cpu_info *ci; 231 232 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 233 return ci; 234 } 235 236 #ifdef __clang__ 237 #define curlwp (curcpu()->ci_curlwp) 238 #else 239 register struct lwp *powerpc_curlwp __asm("r13"); 240 #define curlwp powerpc_curlwp 241 #endif 242 #define curpcb (curcpu()->ci_curpcb) 243 #define curpm (curcpu()->ci_curpm) 244 245 static __inline register_t 246 mfmsr(void) 247 { 248 register_t msr; 249 250 __asm volatile ("mfmsr %0" : "=r"(msr)); 251 return msr; 252 } 253 254 static __inline void 255 mtmsr(register_t msr) 256 { 257 //KASSERT(msr & PSL_CE); 258 //KASSERT(msr & PSL_DE); 259 __asm volatile ("mtmsr %0" : : "r"(msr)); 260 } 261 262 #if !defined(_MODULE) 263 static __inline uint32_t 264 mftbl(void) 265 { 266 uint32_t tbl; 267 268 __asm volatile ( 269 #ifdef PPC_IBM403 270 " mftblo %[tbl]" "\n" 271 #elif defined(PPC_BOOKE) 272 " mfspr %[tbl],268" "\n" 273 #else 274 " mftbl %[tbl]" "\n" 275 #endif 276 : [tbl] "=r" (tbl)); 277 278 return tbl; 279 } 280 281 static __inline uint64_t 282 mftb(void) 283 { 284 uint64_t tb; 285 286 #ifdef _ARCH_PPC64 287 __asm volatile ("mftb %0" : "=r"(tb)); 288 #else 289 int tmp; 290 291 __asm volatile ( 292 #ifdef PPC_IBM403 293 "1: mftbhi %[tb]" "\n" 294 " mftblo %L[tb]" "\n" 295 " mftbhi %[tmp]" "\n" 296 #elif defined(PPC_BOOKE) 297 "1: mfspr %[tb],269" "\n" 298 " mfspr %L[tb],268" "\n" 299 " mfspr %[tmp],269" "\n" 300 #else 301 "1: mftbu %[tb]" "\n" 302 " mftb %L[tb]" "\n" 303 " mftbu %[tmp]" "\n" 304 #endif 305 " cmplw %[tb],%[tmp]" "\n" 306 " bne- 1b" "\n" 307 : [tb] "=r" (tb), [tmp] "=r"(tmp) 308 :: "cr0"); 309 #endif 310 311 return tb; 312 } 313 314 static __inline uint32_t 315 mfrtcl(void) 316 { 317 uint32_t rtcl; 318 319 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 320 return rtcl; 321 } 322 323 static __inline void 324 mfrtc(uint32_t *rtcp) 325 { 326 uint32_t tmp; 327 328 __asm volatile ( 329 "1: mfrtcu %[rtcu]" "\n" 330 " mfrtcl %[rtcl]" "\n" 331 " mfrtcu %[tmp]" "\n" 332 " cmplw %[rtcu],%[tmp]" "\n" 333 " bne- 1b" 334 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 335 :: "cr0"); 336 } 337 338 static __inline uint64_t 339 rtc_nanosecs(void) 340 { 341 /* 342 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick. 343 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds. 344 * RTCU is seconds, 32 bits. 345 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns) 346 */ 347 uint64_t cycles; 348 uint32_t tmp[2]; 349 350 mfrtc(tmp); 351 352 cycles = tmp[0] * 1000000000; 353 cycles += (tmp[1] >> 7); 354 355 return cycles; 356 } 357 #endif /* !_MODULE */ 358 359 static __inline uint32_t 360 mfpvr(void) 361 { 362 uint32_t pvr; 363 364 __asm volatile ("mfpvr %0" : "=r"(pvr)); 365 return (pvr); 366 } 367 368 #ifdef _MODULE 369 extern const char __CPU_MAXNUM; 370 /* 371 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 372 * corresponding R_PPC_ADDR16_HI relocation. 373 */ 374 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 375 #endif /* _MODULE */ 376 377 #if !defined(_MODULE) 378 extern char *booted_kernel; 379 extern int powersave; 380 extern int cpu_timebase; 381 extern int cpu_printfataltraps; 382 383 struct cpu_info * 384 cpu_attach_common(device_t, int); 385 void cpu_setup(device_t, struct cpu_info *); 386 void cpu_identify(char *, size_t); 387 void cpu_probe_cache(void); 388 389 void dcache_wb_page(vaddr_t); 390 void dcache_wbinv_page(vaddr_t); 391 void dcache_inv_page(vaddr_t); 392 void dcache_zero_page(vaddr_t); 393 void icache_inv_page(vaddr_t); 394 void dcache_wb(vaddr_t, vsize_t); 395 void dcache_wbinv(vaddr_t, vsize_t); 396 void dcache_inv(vaddr_t, vsize_t); 397 void icache_inv(vaddr_t, vsize_t); 398 399 void * mapiodev(paddr_t, psize_t, bool); 400 void unmapiodev(vaddr_t, vsize_t); 401 402 int emulate_mxmsr(struct lwp *, struct trapframe *, uint32_t); 403 404 #ifdef MULTIPROCESSOR 405 int md_setup_trampoline(volatile struct cpu_hatch_data *, 406 struct cpu_info *); 407 void md_presync_timebase(volatile struct cpu_hatch_data *); 408 void md_start_timebase(volatile struct cpu_hatch_data *); 409 void md_sync_timebase(volatile struct cpu_hatch_data *); 410 void md_setup_interrupts(void); 411 int cpu_spinup(device_t, struct cpu_info *); 412 register_t 413 cpu_hatch(void); 414 void cpu_spinup_trampoline(void); 415 void cpu_boot_secondary_processors(void); 416 void cpu_halt(void); 417 void cpu_halt_others(void); 418 void cpu_pause(struct trapframe *); 419 void cpu_pause_others(void); 420 void cpu_resume(cpuid_t); 421 void cpu_resume_others(void); 422 int cpu_is_paused(int); 423 void cpu_debug_dump(void); 424 #endif /* MULTIPROCESSOR */ 425 #endif /* !_MODULE */ 426 427 #define cpu_proc_fork(p1, p2) 428 429 #ifndef __HIDE_DELAY 430 #define DELAY(n) delay(n) 431 void delay(unsigned int); 432 #endif /* __HIDE_DELAY */ 433 434 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 435 #define CLKF_PC(cf) cpu_clkf_pc(cf) 436 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 437 438 bool cpu_clkf_usermode(const struct clockframe *); 439 vaddr_t cpu_clkf_pc(const struct clockframe *); 440 bool cpu_clkf_intr(const struct clockframe *); 441 442 #define LWP_PC(l) cpu_lwp_pc(l) 443 444 vaddr_t cpu_lwp_pc(struct lwp *); 445 446 void cpu_ast(struct lwp *, struct cpu_info *); 447 void * cpu_uarea_alloc(bool); 448 bool cpu_uarea_free(void *); 449 void cpu_signotify(struct lwp *); 450 void cpu_need_proftick(struct lwp *); 451 452 void cpu_fixup_stubs(void); 453 454 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 455 int cpu_get_dfs(void); 456 void cpu_set_dfs(int); 457 458 void oea_init(void (*)(void)); 459 void oea_startup(const char *); 460 void oea_dumpsys(void); 461 void oea_install_extint(void (*)(void)); 462 paddr_t kvtop(void *); 463 464 extern paddr_t msgbuf_paddr; 465 extern int cpu_altivec; 466 #endif 467 468 #endif /* _KERNEL */ 469 470 /* XXX The below breaks unified pmap on ppc32 */ 471 472 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 473 && (defined(_KERNEL) || defined(_STANDALONE)) 474 #if defined(PPC_IBM403) 475 #define CACHELINESIZE 16 476 #define MAXCACHELINESIZE 16 477 #elif defined (PPC_OEA64_BRIDGE) 478 #define CACHELINESIZE 128 479 #define MAXCACHELINESIZE 128 480 #else 481 #define CACHELINESIZE 32 482 #define MAXCACHELINESIZE 32 483 #endif /* PPC_OEA64_BRIDGE */ 484 #endif 485 486 void __syncicache(void *, size_t); 487 488 /* 489 * CTL_MACHDEP definitions. 490 */ 491 #define CPU_CACHELINE 1 492 #define CPU_TIMEBASE 2 493 #define CPU_CPUTEMP 3 494 #define CPU_PRINTFATALTRAPS 4 495 #define CPU_CACHEINFO 5 496 #define CPU_ALTIVEC 6 497 #define CPU_MODEL 7 498 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 499 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 500 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 501 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 502 #define CPU_FPU 12 503 504 #endif /* _POWERPC_CPU_H_ */ 505
Indexes created Sun Sep 21 20:09:37 GMT 2025