cpu.h revision 1.118
1 /* $NetBSD: cpu.h,v 1.118 2021/03/07 14:42:53 rin Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _POWERPC_CPU_H_ 37 #define _POWERPC_CPU_H_ 38 39 struct cache_info { 40 int dcache_size; 41 int dcache_line_size; 42 int icache_size; 43 int icache_line_size; 44 }; 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_modular.h" 49 #include "opt_multiprocessor.h" 50 #include "opt_ppcarch.h" 51 #endif 52 53 #ifdef _KERNEL 54 #include <sys/intr.h> 55 #include <sys/device_if.h> 56 #include <sys/evcnt.h> 57 #include <sys/param.h> 58 #include <sys/kernel.h> 59 #endif 60 61 #include <sys/cpu_data.h> 62 63 #ifdef _KERNEL 64 #define CI_SAVETEMP (0*CPUSAVE_LEN) 65 #define CI_SAVEDDB (1*CPUSAVE_LEN) 66 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) /* obsolete */ 67 #define CI_SAVEMMU (3*CPUSAVE_LEN) 68 #define CI_SAVEMAX (4*CPUSAVE_LEN) 69 #define CPUSAVE_LEN 8 70 #if defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 71 #define CPUSAVE_SIZE 128 72 #else 73 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 74 CTASSERT(CPUSAVE_SIZE >= 128); 75 #endif 76 #define CPUSAVE_R28 0 /* where r28 gets saved */ 77 #define CPUSAVE_R29 1 /* where r29 gets saved */ 78 #define CPUSAVE_R30 2 /* where r30 gets saved */ 79 #define CPUSAVE_R31 3 /* where r31 gets saved */ 80 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 81 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 82 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 83 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 84 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 85 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 86 #endif /* _KERNEL */ 87 88 struct cpu_info { 89 struct cpu_data ci_data; /* MI per-cpu data */ 90 #ifdef _KERNEL 91 device_t ci_dev; /* device of corresponding cpu */ 92 struct cpu_softc *ci_softc; /* private cpu info */ 93 struct lwp *ci_curlwp; /* current owner of the processor */ 94 struct lwp *ci_onproc; /* current user LWP / kthread */ 95 struct pcb *ci_curpcb; 96 struct pmap *ci_curpm; 97 #if defined(PPC_OEA) || defined(PPC_OEA601) || defined(PPC_OEA64) || \ 98 defined(PPC_OEA64_BRIDGE) || defined(MODULAR) || defined(_MODULE) 99 void *ci_battable; /* BAT table in use by this CPU */ 100 #endif 101 struct lwp *ci_softlwps[SOFTINT_COUNT]; 102 int ci_cpuid; /* from SPR_PIR */ 103 104 int ci_want_resched; 105 volatile uint64_t ci_lastintr; 106 volatile u_long ci_lasttb; 107 volatile int ci_tickspending; 108 volatile int ci_cpl; 109 volatile int ci_iactive; 110 volatile int ci_idepth; 111 union { 112 #if !defined(PPC_BOOKE) && !defined(_MODULE) 113 volatile imask_t un1_ipending; 114 #define ci_ipending ci_un1.un1_ipending 115 #endif 116 uint64_t un1_pad64; 117 } ci_un1; 118 volatile uint32_t ci_pending_ipis; 119 int ci_mtx_oldspl; 120 int ci_mtx_count; 121 #if defined(PPC_IBM4XX) || \ 122 ((defined(MODULAR) || defined(_MODULE)) && !defined(_LP64)) 123 char *ci_intstk; 124 #endif 125 126 register_t ci_savearea[CPUSAVE_SIZE]; 127 #if defined(PPC_BOOKE) || \ 128 ((defined(MODULAR) || defined(_MODULE)) && !defined(_LP64)) 129 uint32_t ci_pmap_asid_cur; 130 union pmap_segtab *ci_pmap_segtabs[2]; 131 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 132 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 133 struct pmap_tlb_info *ci_tlb_info; 134 #endif /* PPC_BOOKE || ((MODULAR || _MODULE) && !_LP64) */ 135 struct cache_info ci_ci; 136 void *ci_sysmon_cookie; 137 void (*ci_idlespin)(void); 138 uint32_t ci_khz; 139 struct evcnt ci_ev_clock; /* clock intrs */ 140 struct evcnt ci_ev_statclock; /* stat clock */ 141 struct evcnt ci_ev_traps; /* calls to trap() */ 142 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 143 struct evcnt ci_ev_udsi; /* user DSI traps */ 144 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 145 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 146 struct evcnt ci_ev_isi; /* user ISI traps */ 147 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 148 struct evcnt ci_ev_pgm; /* user PGM traps */ 149 struct evcnt ci_ev_debug; /* user debug traps */ 150 struct evcnt ci_ev_fpu; /* FPU traps */ 151 struct evcnt ci_ev_fpusw; /* FPU context switch */ 152 struct evcnt ci_ev_ali; /* Alignment traps */ 153 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 154 struct evcnt ci_ev_scalls; /* system call traps */ 155 struct evcnt ci_ev_vec; /* Altivec traps */ 156 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 157 struct evcnt ci_ev_umchk; /* user MCHK events */ 158 struct evcnt ci_ev_ipi; /* IPIs received */ 159 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 160 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 161 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 162 #endif /* _KERNEL */ 163 }; 164 #endif /* _KERNEL || _KMEMUSER */ 165 166 #ifdef _KERNEL 167 168 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 169 struct cpu_hatch_data { 170 int hatch_running; 171 device_t hatch_self; 172 struct cpu_info *hatch_ci; 173 uint32_t hatch_tbu; 174 uint32_t hatch_tbl; 175 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 176 uint64_t hatch_hid0; 177 uint64_t hatch_hid1; 178 uint64_t hatch_hid4; 179 uint64_t hatch_hid5; 180 #else 181 uint32_t hatch_hid0; 182 #endif 183 uint32_t hatch_pir; 184 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 185 uintptr_t hatch_asr; 186 uintptr_t hatch_sdr1; 187 uint32_t hatch_sr[16]; 188 uintptr_t hatch_ibatu[8], hatch_ibatl[8]; 189 uintptr_t hatch_dbatu[8], hatch_dbatl[8]; 190 #endif 191 #if defined(PPC_BOOKE) 192 vaddr_t hatch_sp; 193 u_int hatch_tlbidx; 194 #endif 195 }; 196 197 struct cpuset_info { 198 kcpuset_t *cpus_running; 199 kcpuset_t *cpus_hatched; 200 kcpuset_t *cpus_paused; 201 kcpuset_t *cpus_resumed; 202 kcpuset_t *cpus_halted; 203 }; 204 205 extern struct cpuset_info cpuset_info; 206 #endif /* MULTIPROCESSOR && !_MODULE */ 207 208 #if defined(MULTIPROCESSOR) || defined(_MODULE) 209 #define cpu_number() (curcpu()->ci_index + 0) 210 211 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 212 #define CPU_INFO_ITERATOR int 213 #define CPU_INFO_FOREACH(cii, ci) \ 214 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++ 215 216 #else 217 #define cpu_number() 0 218 219 #define CPU_IS_PRIMARY(ci) true 220 #define CPU_INFO_ITERATOR int 221 #define CPU_INFO_FOREACH(cii, ci) \ 222 (void)cii, ci = curcpu(); ci != NULL; ci = NULL 223 224 #endif /* MULTIPROCESSOR || _MODULE */ 225 226 extern struct cpu_info cpu_info[]; 227 228 static __inline struct cpu_info * curcpu(void) __pure; 229 static __inline struct cpu_info * 230 curcpu(void) 231 { 232 struct cpu_info *ci; 233 234 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 235 return ci; 236 } 237 238 #ifdef __clang__ 239 #define curlwp (curcpu()->ci_curlwp) 240 #else 241 register struct lwp *powerpc_curlwp __asm("r13"); 242 #define curlwp powerpc_curlwp 243 #endif 244 #define curpcb (curcpu()->ci_curpcb) 245 #define curpm (curcpu()->ci_curpm) 246 247 static __inline register_t 248 mfmsr(void) 249 { 250 register_t msr; 251 252 __asm volatile ("mfmsr %0" : "=r"(msr)); 253 return msr; 254 } 255 256 static __inline void 257 mtmsr(register_t msr) 258 { 259 //KASSERT(msr & PSL_CE); 260 //KASSERT(msr & PSL_DE); 261 __asm volatile ("mtmsr %0" : : "r"(msr)); 262 } 263 264 #if !defined(_MODULE) 265 static __inline uint32_t 266 mftbl(void) 267 { 268 uint32_t tbl; 269 270 __asm volatile ( 271 #ifdef PPC_IBM403 272 " mftblo %[tbl]" "\n" 273 #elif defined(PPC_BOOKE) 274 " mfspr %[tbl],268" "\n" 275 #else 276 " mftbl %[tbl]" "\n" 277 #endif 278 : [tbl] "=r" (tbl)); 279 280 return tbl; 281 } 282 283 static __inline uint64_t 284 mftb(void) 285 { 286 uint64_t tb; 287 288 #ifdef _ARCH_PPC64 289 __asm volatile ("mftb %0" : "=r"(tb)); 290 #else 291 int tmp; 292 293 __asm volatile ( 294 #ifdef PPC_IBM403 295 "1: mftbhi %[tb]" "\n" 296 " mftblo %L[tb]" "\n" 297 " mftbhi %[tmp]" "\n" 298 #elif defined(PPC_BOOKE) 299 "1: mfspr %[tb],269" "\n" 300 " mfspr %L[tb],268" "\n" 301 " mfspr %[tmp],269" "\n" 302 #else 303 "1: mftbu %[tb]" "\n" 304 " mftb %L[tb]" "\n" 305 " mftbu %[tmp]" "\n" 306 #endif 307 " cmplw %[tb],%[tmp]" "\n" 308 " bne- 1b" "\n" 309 : [tb] "=r" (tb), [tmp] "=r"(tmp) 310 :: "cr0"); 311 #endif 312 313 return tb; 314 } 315 316 static __inline uint32_t 317 mfrtcl(void) 318 { 319 uint32_t rtcl; 320 321 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 322 return rtcl; 323 } 324 325 static __inline void 326 mfrtc(uint32_t *rtcp) 327 { 328 uint32_t tmp; 329 330 __asm volatile ( 331 "1: mfrtcu %[rtcu]" "\n" 332 " mfrtcl %[rtcl]" "\n" 333 " mfrtcu %[tmp]" "\n" 334 " cmplw %[rtcu],%[tmp]" "\n" 335 " bne- 1b" 336 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 337 :: "cr0"); 338 } 339 340 static __inline uint64_t 341 rtc_nanosecs(void) 342 { 343 /* 344 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick. 345 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds. 346 * RTCU is seconds, 32 bits. 347 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns) 348 */ 349 uint64_t cycles; 350 uint32_t tmp[2]; 351 352 mfrtc(tmp); 353 354 cycles = tmp[0] * 1000000000; 355 cycles += (tmp[1] >> 7); 356 357 return cycles; 358 } 359 #endif /* !_MODULE */ 360 361 static __inline uint32_t 362 mfpvr(void) 363 { 364 uint32_t pvr; 365 366 __asm volatile ("mfpvr %0" : "=r"(pvr)); 367 return (pvr); 368 } 369 370 #ifdef _MODULE 371 extern const char __CPU_MAXNUM; 372 /* 373 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 374 * corresponding R_PPC_ADDR16_HI relocation. 375 */ 376 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 377 #endif /* _MODULE */ 378 379 #if !defined(_MODULE) 380 extern char *booted_kernel; 381 extern int powersave; 382 extern int cpu_timebase; 383 extern int cpu_printfataltraps; 384 385 struct cpu_info * 386 cpu_attach_common(device_t, int); 387 void cpu_setup(device_t, struct cpu_info *); 388 void cpu_identify(char *, size_t); 389 void cpu_probe_cache(void); 390 391 void dcache_wb_page(vaddr_t); 392 void dcache_wbinv_page(vaddr_t); 393 void dcache_inv_page(vaddr_t); 394 void dcache_zero_page(vaddr_t); 395 void icache_inv_page(vaddr_t); 396 void dcache_wb(vaddr_t, vsize_t); 397 void dcache_wbinv(vaddr_t, vsize_t); 398 void dcache_inv(vaddr_t, vsize_t); 399 void icache_inv(vaddr_t, vsize_t); 400 401 void * mapiodev(paddr_t, psize_t, bool); 402 void unmapiodev(vaddr_t, vsize_t); 403 404 int emulate_mxmsr(struct lwp *, struct trapframe *, uint32_t); 405 406 #ifdef MULTIPROCESSOR 407 int md_setup_trampoline(volatile struct cpu_hatch_data *, 408 struct cpu_info *); 409 void md_presync_timebase(volatile struct cpu_hatch_data *); 410 void md_start_timebase(volatile struct cpu_hatch_data *); 411 void md_sync_timebase(volatile struct cpu_hatch_data *); 412 void md_setup_interrupts(void); 413 int cpu_spinup(device_t, struct cpu_info *); 414 register_t 415 cpu_hatch(void); 416 void cpu_spinup_trampoline(void); 417 void cpu_boot_secondary_processors(void); 418 void cpu_halt(void); 419 void cpu_halt_others(void); 420 void cpu_pause(struct trapframe *); 421 void cpu_pause_others(void); 422 void cpu_resume(cpuid_t); 423 void cpu_resume_others(void); 424 int cpu_is_paused(int); 425 void cpu_debug_dump(void); 426 #endif /* MULTIPROCESSOR */ 427 #endif /* !_MODULE */ 428 429 #define cpu_proc_fork(p1, p2) 430 431 #ifndef __HIDE_DELAY 432 #define DELAY(n) delay(n) 433 void delay(unsigned int); 434 #endif /* __HIDE_DELAY */ 435 436 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 437 #define CLKF_PC(cf) cpu_clkf_pc(cf) 438 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 439 440 bool cpu_clkf_usermode(const struct clockframe *); 441 vaddr_t cpu_clkf_pc(const struct clockframe *); 442 bool cpu_clkf_intr(const struct clockframe *); 443 444 #define LWP_PC(l) cpu_lwp_pc(l) 445 446 vaddr_t cpu_lwp_pc(struct lwp *); 447 448 void cpu_ast(struct lwp *, struct cpu_info *); 449 void * cpu_uarea_alloc(bool); 450 bool cpu_uarea_free(void *); 451 void cpu_signotify(struct lwp *); 452 void cpu_need_proftick(struct lwp *); 453 454 void cpu_fixup_stubs(void); 455 456 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 457 int cpu_get_dfs(void); 458 void cpu_set_dfs(int); 459 460 void oea_init(void (*)(void)); 461 void oea_startup(const char *); 462 void oea_dumpsys(void); 463 void oea_install_extint(void (*)(void)); 464 paddr_t kvtop(void *); 465 466 extern paddr_t msgbuf_paddr; 467 extern int cpu_altivec; 468 #endif 469 470 #endif /* _KERNEL */ 471 472 /* XXX The below breaks unified pmap on ppc32 */ 473 474 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 475 && (defined(_KERNEL) || defined(_STANDALONE)) 476 #if defined(PPC_IBM403) 477 #define CACHELINESIZE 16 478 #define MAXCACHELINESIZE 16 479 #elif defined (PPC_OEA64_BRIDGE) 480 #define CACHELINESIZE 128 481 #define MAXCACHELINESIZE 128 482 #else 483 #define CACHELINESIZE 32 484 #define MAXCACHELINESIZE 32 485 #endif /* PPC_OEA64_BRIDGE */ 486 #endif 487 488 void __syncicache(void *, size_t); 489 490 /* 491 * CTL_MACHDEP definitions. 492 */ 493 #define CPU_CACHELINE 1 494 #define CPU_TIMEBASE 2 495 #define CPU_CPUTEMP 3 496 #define CPU_PRINTFATALTRAPS 4 497 #define CPU_CACHEINFO 5 498 #define CPU_ALTIVEC 6 499 #define CPU_MODEL 7 500 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 501 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 502 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 503 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 504 #define CPU_FPU 12 505 506 #endif /* _POWERPC_CPU_H_ */ 507
Indexes created Wed Sep 24 14:09:57 GMT 2025