cpu.h revision 1.119
1 /* $NetBSD: cpu.h,v 1.119 2021/08/14 17:51:19 ryo Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _POWERPC_CPU_H_ 37 #define _POWERPC_CPU_H_ 38 39 struct cache_info { 40 int dcache_size; 41 int dcache_line_size; 42 int icache_size; 43 int icache_line_size; 44 }; 45 46 #if defined(_KERNEL) || defined(_KMEMUSER) 47 #if defined(_KERNEL_OPT) 48 #include "opt_gprof.h" 49 #include "opt_modular.h" 50 #include "opt_multiprocessor.h" 51 #include "opt_ppcarch.h" 52 #endif 53 54 #ifdef _KERNEL 55 #include <sys/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #include <sys/param.h> 59 #include <sys/kernel.h> 60 #endif 61 62 #include <sys/cpu_data.h> 63 64 #ifdef _KERNEL 65 #define CI_SAVETEMP (0*CPUSAVE_LEN) 66 #define CI_SAVEDDB (1*CPUSAVE_LEN) 67 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) /* obsolete */ 68 #define CI_SAVEMMU (3*CPUSAVE_LEN) 69 #define CI_SAVEMAX (4*CPUSAVE_LEN) 70 #define CPUSAVE_LEN 8 71 #if defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 72 #define CPUSAVE_SIZE 128 73 #else 74 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 75 CTASSERT(CPUSAVE_SIZE >= 128); 76 #endif 77 #define CPUSAVE_R28 0 /* where r28 gets saved */ 78 #define CPUSAVE_R29 1 /* where r29 gets saved */ 79 #define CPUSAVE_R30 2 /* where r30 gets saved */ 80 #define CPUSAVE_R31 3 /* where r31 gets saved */ 81 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 82 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 83 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 84 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 85 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 86 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 87 #endif /* _KERNEL */ 88 89 struct cpu_info { 90 struct cpu_data ci_data; /* MI per-cpu data */ 91 #ifdef _KERNEL 92 device_t ci_dev; /* device of corresponding cpu */ 93 struct cpu_softc *ci_softc; /* private cpu info */ 94 struct lwp *ci_curlwp; /* current owner of the processor */ 95 struct lwp *ci_onproc; /* current user LWP / kthread */ 96 struct pcb *ci_curpcb; 97 struct pmap *ci_curpm; 98 #if defined(PPC_OEA) || defined(PPC_OEA601) || defined(PPC_OEA64) || \ 99 defined(PPC_OEA64_BRIDGE) || defined(MODULAR) || defined(_MODULE) 100 void *ci_battable; /* BAT table in use by this CPU */ 101 #endif 102 struct lwp *ci_softlwps[SOFTINT_COUNT]; 103 int ci_cpuid; /* from SPR_PIR */ 104 105 int ci_want_resched; 106 volatile uint64_t ci_lastintr; 107 volatile u_long ci_lasttb; 108 volatile int ci_tickspending; 109 volatile int ci_cpl; 110 volatile int ci_iactive; 111 volatile int ci_idepth; 112 union { 113 #if !defined(PPC_BOOKE) && !defined(_MODULE) 114 volatile imask_t un1_ipending; 115 #define ci_ipending ci_un1.un1_ipending 116 #endif 117 uint64_t un1_pad64; 118 } ci_un1; 119 volatile uint32_t ci_pending_ipis; 120 int ci_mtx_oldspl; 121 int ci_mtx_count; 122 #if defined(PPC_IBM4XX) || \ 123 ((defined(MODULAR) || defined(_MODULE)) && !defined(_LP64)) 124 char *ci_intstk; 125 #endif 126 127 register_t ci_savearea[CPUSAVE_SIZE]; 128 #if defined(PPC_BOOKE) || \ 129 ((defined(MODULAR) || defined(_MODULE)) && !defined(_LP64)) 130 uint32_t ci_pmap_asid_cur; 131 union pmap_segtab *ci_pmap_segtabs[2]; 132 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 133 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 134 struct pmap_tlb_info *ci_tlb_info; 135 #endif /* PPC_BOOKE || ((MODULAR || _MODULE) && !_LP64) */ 136 struct cache_info ci_ci; 137 void *ci_sysmon_cookie; 138 void (*ci_idlespin)(void); 139 uint32_t ci_khz; 140 struct evcnt ci_ev_clock; /* clock intrs */ 141 struct evcnt ci_ev_statclock; /* stat clock */ 142 struct evcnt ci_ev_traps; /* calls to trap() */ 143 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 144 struct evcnt ci_ev_udsi; /* user DSI traps */ 145 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 146 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 147 struct evcnt ci_ev_isi; /* user ISI traps */ 148 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 149 struct evcnt ci_ev_pgm; /* user PGM traps */ 150 struct evcnt ci_ev_debug; /* user debug traps */ 151 struct evcnt ci_ev_fpu; /* FPU traps */ 152 struct evcnt ci_ev_fpusw; /* FPU context switch */ 153 struct evcnt ci_ev_ali; /* Alignment traps */ 154 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 155 struct evcnt ci_ev_scalls; /* system call traps */ 156 struct evcnt ci_ev_vec; /* Altivec traps */ 157 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 158 struct evcnt ci_ev_umchk; /* user MCHK events */ 159 struct evcnt ci_ev_ipi; /* IPIs received */ 160 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 161 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 162 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 163 #if defined(GPROF) && defined(MULTIPROCESSOR) 164 struct gmonparam *ci_gmon; /* MI per-cpu GPROF */ 165 #endif 166 #endif /* _KERNEL */ 167 }; 168 #endif /* _KERNEL || _KMEMUSER */ 169 170 #ifdef _KERNEL 171 172 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 173 struct cpu_hatch_data { 174 int hatch_running; 175 device_t hatch_self; 176 struct cpu_info *hatch_ci; 177 uint32_t hatch_tbu; 178 uint32_t hatch_tbl; 179 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 180 uint64_t hatch_hid0; 181 uint64_t hatch_hid1; 182 uint64_t hatch_hid4; 183 uint64_t hatch_hid5; 184 #else 185 uint32_t hatch_hid0; 186 #endif 187 uint32_t hatch_pir; 188 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 189 uintptr_t hatch_asr; 190 uintptr_t hatch_sdr1; 191 uint32_t hatch_sr[16]; 192 uintptr_t hatch_ibatu[8], hatch_ibatl[8]; 193 uintptr_t hatch_dbatu[8], hatch_dbatl[8]; 194 #endif 195 #if defined(PPC_BOOKE) 196 vaddr_t hatch_sp; 197 u_int hatch_tlbidx; 198 #endif 199 }; 200 201 struct cpuset_info { 202 kcpuset_t *cpus_running; 203 kcpuset_t *cpus_hatched; 204 kcpuset_t *cpus_paused; 205 kcpuset_t *cpus_resumed; 206 kcpuset_t *cpus_halted; 207 }; 208 209 extern struct cpuset_info cpuset_info; 210 #endif /* MULTIPROCESSOR && !_MODULE */ 211 212 #if defined(MULTIPROCESSOR) || defined(_MODULE) 213 #define cpu_number() (curcpu()->ci_index + 0) 214 215 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 216 #define CPU_INFO_ITERATOR int 217 #define CPU_INFO_FOREACH(cii, ci) \ 218 cii = 0, ci = &cpu_info[0]; cii < (ncpu ? ncpu : 1); cii++, ci++ 219 220 #else 221 #define cpu_number() 0 222 223 #define CPU_IS_PRIMARY(ci) true 224 #define CPU_INFO_ITERATOR int 225 #define CPU_INFO_FOREACH(cii, ci) \ 226 (void)cii, ci = curcpu(); ci != NULL; ci = NULL 227 228 #endif /* MULTIPROCESSOR || _MODULE */ 229 230 extern struct cpu_info cpu_info[]; 231 232 static __inline struct cpu_info * curcpu(void) __pure; 233 static __inline struct cpu_info * 234 curcpu(void) 235 { 236 struct cpu_info *ci; 237 238 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 239 return ci; 240 } 241 242 #ifdef __clang__ 243 #define curlwp (curcpu()->ci_curlwp) 244 #else 245 register struct lwp *powerpc_curlwp __asm("r13"); 246 #define curlwp powerpc_curlwp 247 #endif 248 #define curpcb (curcpu()->ci_curpcb) 249 #define curpm (curcpu()->ci_curpm) 250 251 static __inline register_t 252 mfmsr(void) 253 { 254 register_t msr; 255 256 __asm volatile ("mfmsr %0" : "=r"(msr)); 257 return msr; 258 } 259 260 static __inline void 261 mtmsr(register_t msr) 262 { 263 //KASSERT(msr & PSL_CE); 264 //KASSERT(msr & PSL_DE); 265 __asm volatile ("mtmsr %0" : : "r"(msr)); 266 } 267 268 #if !defined(_MODULE) 269 static __inline uint32_t 270 mftbl(void) 271 { 272 uint32_t tbl; 273 274 __asm volatile ( 275 #ifdef PPC_IBM403 276 " mftblo %[tbl]" "\n" 277 #elif defined(PPC_BOOKE) 278 " mfspr %[tbl],268" "\n" 279 #else 280 " mftbl %[tbl]" "\n" 281 #endif 282 : [tbl] "=r" (tbl)); 283 284 return tbl; 285 } 286 287 static __inline uint64_t 288 mftb(void) 289 { 290 uint64_t tb; 291 292 #ifdef _ARCH_PPC64 293 __asm volatile ("mftb %0" : "=r"(tb)); 294 #else 295 int tmp; 296 297 __asm volatile ( 298 #ifdef PPC_IBM403 299 "1: mftbhi %[tb]" "\n" 300 " mftblo %L[tb]" "\n" 301 " mftbhi %[tmp]" "\n" 302 #elif defined(PPC_BOOKE) 303 "1: mfspr %[tb],269" "\n" 304 " mfspr %L[tb],268" "\n" 305 " mfspr %[tmp],269" "\n" 306 #else 307 "1: mftbu %[tb]" "\n" 308 " mftb %L[tb]" "\n" 309 " mftbu %[tmp]" "\n" 310 #endif 311 " cmplw %[tb],%[tmp]" "\n" 312 " bne- 1b" "\n" 313 : [tb] "=r" (tb), [tmp] "=r"(tmp) 314 :: "cr0"); 315 #endif 316 317 return tb; 318 } 319 320 static __inline uint32_t 321 mfrtcl(void) 322 { 323 uint32_t rtcl; 324 325 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 326 return rtcl; 327 } 328 329 static __inline void 330 mfrtc(uint32_t *rtcp) 331 { 332 uint32_t tmp; 333 334 __asm volatile ( 335 "1: mfrtcu %[rtcu]" "\n" 336 " mfrtcl %[rtcl]" "\n" 337 " mfrtcu %[tmp]" "\n" 338 " cmplw %[rtcu],%[tmp]" "\n" 339 " bne- 1b" 340 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 341 :: "cr0"); 342 } 343 344 static __inline uint64_t 345 rtc_nanosecs(void) 346 { 347 /* 348 * 601 RTC/DEC registers share clock of 7.8125 MHz, 128 ns per tick. 349 * DEC has max of 25 bits, FFFFFF => 2.14748352 seconds. 350 * RTCU is seconds, 32 bits. 351 * RTCL is nano-seconds, 23 bit counter from 0 - 999,999,872 (999,999,999 - 128 ns) 352 */ 353 uint64_t cycles; 354 uint32_t tmp[2]; 355 356 mfrtc(tmp); 357 358 cycles = tmp[0] * 1000000000; 359 cycles += (tmp[1] >> 7); 360 361 return cycles; 362 } 363 #endif /* !_MODULE */ 364 365 static __inline uint32_t 366 mfpvr(void) 367 { 368 uint32_t pvr; 369 370 __asm volatile ("mfpvr %0" : "=r"(pvr)); 371 return (pvr); 372 } 373 374 #ifdef _MODULE 375 extern const char __CPU_MAXNUM; 376 /* 377 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 378 * corresponding R_PPC_ADDR16_HI relocation. 379 */ 380 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 381 #endif /* _MODULE */ 382 383 #if !defined(_MODULE) 384 extern char *booted_kernel; 385 extern int powersave; 386 extern int cpu_timebase; 387 extern int cpu_printfataltraps; 388 389 struct cpu_info * 390 cpu_attach_common(device_t, int); 391 void cpu_setup(device_t, struct cpu_info *); 392 void cpu_identify(char *, size_t); 393 void cpu_probe_cache(void); 394 395 void dcache_wb_page(vaddr_t); 396 void dcache_wbinv_page(vaddr_t); 397 void dcache_inv_page(vaddr_t); 398 void dcache_zero_page(vaddr_t); 399 void icache_inv_page(vaddr_t); 400 void dcache_wb(vaddr_t, vsize_t); 401 void dcache_wbinv(vaddr_t, vsize_t); 402 void dcache_inv(vaddr_t, vsize_t); 403 void icache_inv(vaddr_t, vsize_t); 404 405 void * mapiodev(paddr_t, psize_t, bool); 406 void unmapiodev(vaddr_t, vsize_t); 407 408 int emulate_mxmsr(struct lwp *, struct trapframe *, uint32_t); 409 410 #ifdef MULTIPROCESSOR 411 int md_setup_trampoline(volatile struct cpu_hatch_data *, 412 struct cpu_info *); 413 void md_presync_timebase(volatile struct cpu_hatch_data *); 414 void md_start_timebase(volatile struct cpu_hatch_data *); 415 void md_sync_timebase(volatile struct cpu_hatch_data *); 416 void md_setup_interrupts(void); 417 int cpu_spinup(device_t, struct cpu_info *); 418 register_t 419 cpu_hatch(void); 420 void cpu_spinup_trampoline(void); 421 void cpu_boot_secondary_processors(void); 422 void cpu_halt(void); 423 void cpu_halt_others(void); 424 void cpu_pause(struct trapframe *); 425 void cpu_pause_others(void); 426 void cpu_resume(cpuid_t); 427 void cpu_resume_others(void); 428 int cpu_is_paused(int); 429 void cpu_debug_dump(void); 430 #endif /* MULTIPROCESSOR */ 431 #endif /* !_MODULE */ 432 433 #define cpu_proc_fork(p1, p2) 434 435 #ifndef __HIDE_DELAY 436 #define DELAY(n) delay(n) 437 void delay(unsigned int); 438 #endif /* __HIDE_DELAY */ 439 440 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 441 #define CLKF_PC(cf) cpu_clkf_pc(cf) 442 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 443 444 bool cpu_clkf_usermode(const struct clockframe *); 445 vaddr_t cpu_clkf_pc(const struct clockframe *); 446 bool cpu_clkf_intr(const struct clockframe *); 447 448 #define LWP_PC(l) cpu_lwp_pc(l) 449 450 vaddr_t cpu_lwp_pc(struct lwp *); 451 452 void cpu_ast(struct lwp *, struct cpu_info *); 453 void * cpu_uarea_alloc(bool); 454 bool cpu_uarea_free(void *); 455 void cpu_signotify(struct lwp *); 456 void cpu_need_proftick(struct lwp *); 457 458 void cpu_fixup_stubs(void); 459 460 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 461 int cpu_get_dfs(void); 462 void cpu_set_dfs(int); 463 464 void oea_init(void (*)(void)); 465 void oea_startup(const char *); 466 void oea_dumpsys(void); 467 void oea_install_extint(void (*)(void)); 468 paddr_t kvtop(void *); 469 470 extern paddr_t msgbuf_paddr; 471 extern int cpu_altivec; 472 #endif 473 474 #endif /* _KERNEL */ 475 476 /* XXX The below breaks unified pmap on ppc32 */ 477 478 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 479 && (defined(_KERNEL) || defined(_STANDALONE)) 480 #if defined(PPC_IBM403) 481 #define CACHELINESIZE 16 482 #define MAXCACHELINESIZE 16 483 #elif defined (PPC_OEA64_BRIDGE) 484 #define CACHELINESIZE 128 485 #define MAXCACHELINESIZE 128 486 #else 487 #define CACHELINESIZE 32 488 #define MAXCACHELINESIZE 32 489 #endif /* PPC_OEA64_BRIDGE */ 490 #endif 491 492 void __syncicache(void *, size_t); 493 494 /* 495 * CTL_MACHDEP definitions. 496 */ 497 #define CPU_CACHELINE 1 498 #define CPU_TIMEBASE 2 499 #define CPU_CPUTEMP 3 500 #define CPU_PRINTFATALTRAPS 4 501 #define CPU_CACHEINFO 5 502 #define CPU_ALTIVEC 6 503 #define CPU_MODEL 7 504 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 505 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 506 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 507 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 508 #define CPU_FPU 12 509 510 #endif /* _POWERPC_CPU_H_ */ 511
Indexes created Tue Sep 23 02:09:52 GMT 2025