cpu.h revision 1.40
1 /* $NetBSD: cpu.h,v 1.40 2004/02/17 22:03:52 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/sched.h> 58 59 struct cpu_info { 60 struct schedstate_percpu ci_schedstate; /* scheduler state */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 struct pcb *ci_idle_pcb; /* PA of our idle pcb */ 69 int ci_cpuid; 70 71 volatile int ci_astpending; 72 int ci_want_resched; 73 volatile u_long ci_lasttb; 74 volatile int ci_tickspending; 75 int ci_cpl; 76 int ci_iactive; 77 int ci_ipending; 78 int ci_intrdepth; 79 char *ci_intstk; 80 #define CPUSAVE_LEN 8 81 register_t ci_tempsave[CPUSAVE_LEN]; 82 register_t ci_ddbsave[CPUSAVE_LEN]; 83 register_t ci_ipkdbsave[CPUSAVE_LEN]; 84 #define CPUSAVE_R28 0 /* where r28 gets saved */ 85 #define CPUSAVE_R29 1 /* where r29 gets saved */ 86 #define CPUSAVE_R30 2 /* where r30 gets saved */ 87 #define CPUSAVE_R31 3 /* where r31 gets saved */ 88 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 89 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 90 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 91 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 92 #define DISISAVE_LEN 4 93 register_t ci_disisave[DISISAVE_LEN]; 94 struct cache_info ci_ci; 95 void *ci_sysmon_cookie; 96 struct evcnt ci_ev_clock; /* clock intrs */ 97 struct evcnt ci_ev_softclock; /* softclock intrs */ 98 struct evcnt ci_ev_softnet; /* softnet intrs */ 99 struct evcnt ci_ev_softserial; /* softserial intrs */ 100 struct evcnt ci_ev_traps; /* calls to trap() */ 101 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 102 struct evcnt ci_ev_udsi; /* user DSI traps */ 103 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 104 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 105 struct evcnt ci_ev_isi; /* user ISI traps */ 106 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 107 struct evcnt ci_ev_pgm; /* user PGM traps */ 108 struct evcnt ci_ev_fpu; /* FPU traps */ 109 struct evcnt ci_ev_fpusw; /* FPU context switch */ 110 struct evcnt ci_ev_ali; /* Alignment traps */ 111 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 112 struct evcnt ci_ev_scalls; /* system call traps */ 113 struct evcnt ci_ev_vec; /* Altivec traps */ 114 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 115 struct evcnt ci_ev_umchk; /* user MCHK events */ 116 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 117 u_long ci_spin_locks; /* # of spin locks held */ 118 u_long ci_simple_locks; /* # of simple locks held */ 119 #endif 120 }; 121 122 #ifdef MULTIPROCESSOR 123 static __inline int 124 cpu_number(void) 125 { 126 int pir; 127 128 __asm ("mfspr %0,1023" : "=r"(pir)); 129 return pir; 130 } 131 132 void cpu_boot_secondary_processors(void); 133 134 135 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 136 #define CPU_INFO_ITERATOR int 137 #define CPU_INFO_FOREACH(cii, ci) \ 138 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 139 140 #else 141 142 #define cpu_number() 0 143 144 #define CPU_INFO_ITERATOR int 145 #define CPU_INFO_FOREACH(cii, ci) \ 146 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 147 148 #endif /* MULTIPROCESSOR */ 149 150 extern struct cpu_info cpu_info[]; 151 152 static __inline struct cpu_info * 153 curcpu(void) 154 { 155 struct cpu_info *ci; 156 157 __asm __volatile ("mfsprg %0,0" : "=r"(ci)); 158 return ci; 159 } 160 161 #define curlwp (curcpu()->ci_curlwp) 162 #define curpcb (curcpu()->ci_curpcb) 163 #define curpm (curcpu()->ci_curpm) 164 165 static __inline register_t 166 mfmsr(void) 167 { 168 register_t msr; 169 170 __asm __volatile ("mfmsr %0" : "=r"(msr)); 171 return msr; 172 } 173 174 static __inline void 175 mtmsr(register_t msr) 176 { 177 178 __asm __volatile ("mtmsr %0" : : "r"(msr)); 179 } 180 181 static __inline uint32_t 182 mftbl(void) 183 { 184 uint32_t tbl; 185 186 __asm __volatile ( 187 #ifdef PPC_IBM403 188 " mftblo %0 \n" 189 #else 190 " mftbl %0 \n" 191 #endif 192 : "=r" (tbl)); 193 194 return tbl; 195 } 196 197 static __inline uint64_t 198 mftb(void) 199 { 200 uint64_t tb; 201 202 #ifdef _LP64 203 __asm __volatile ("mftb %0" : "=r"(tb)); 204 #else 205 int tmp; 206 207 __asm __volatile ( 208 #ifdef PPC_IBM403 209 "1: mftbhi %0 \n" 210 " mftblo %0+1 \n" 211 " mftbhi %1 \n" 212 #else 213 "1: mftbu %0 \n" 214 " mftb %0+1 \n" 215 " mftbu %1 \n" 216 #endif 217 " cmplw %0,%1 \n" 218 " bne- 1b \n" 219 : "=r" (tb), "=r"(tmp) :: "cr0"); 220 #endif 221 222 return tb; 223 } 224 225 static __inline uint32_t 226 mfrtcl(void) 227 { 228 uint32_t rtcl; 229 230 __asm __volatile ("mfrtcl %0" : "=r"(rtcl)); 231 return rtcl; 232 } 233 234 static __inline void 235 mfrtc(uint32_t *rtcp) 236 { 237 uint32_t tmp; 238 239 __asm __volatile ( 240 "1: mfrtcu %0 \n" 241 " mfrtcl %1 \n" 242 " mfrtcu %2 \n" 243 " cmplw %0,%2 \n" 244 " bne- 1b" 245 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp)); 246 } 247 248 static __inline uint32_t 249 mfpvr(void) 250 { 251 uint32_t pvr; 252 253 __asm __volatile ("mfpvr %0" : "=r"(pvr)); 254 return (pvr); 255 } 256 257 /* 258 * CLKF_BASEPRI is dependent on the underlying interrupt code 259 * and can not be defined here. It should be defined in 260 * <machine/intr.h> 261 */ 262 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 263 #define CLKF_PC(frame) ((frame)->srr0) 264 #define CLKF_INTR(frame) ((frame)->depth > 0) 265 266 #define LWP_PC(l) (trapframe(l)->srr0) 267 268 #define cpu_swapout(p) 269 #define cpu_proc_fork(p1, p2) 270 271 extern int powersave; 272 extern int cpu_timebase; 273 extern int cpu_printfataltraps; 274 extern char cpu_model[]; 275 276 struct cpu_info *cpu_attach_common(struct device *, int); 277 void cpu_setup(struct device *, struct cpu_info *); 278 void cpu_identify(char *, size_t); 279 void delay (unsigned int); 280 void cpu_probe_cache(void); 281 void dcache_flush_page(vaddr_t); 282 void icache_flush_page(vaddr_t); 283 void dcache_flush(vaddr_t, vsize_t); 284 void icache_flush(vaddr_t, vsize_t); 285 void *mapiodev(paddr_t, psize_t); 286 287 #define DELAY(n) delay(n) 288 289 #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1) 290 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1) 291 #define signotify(p) (curcpu()->ci_astpending = 1) 292 293 #ifdef PPC_OEA 294 void oea_init(void (*)(void)); 295 void oea_startup(const char *); 296 void oea_dumpsys(void); 297 void oea_install_extint(void (*)(void)); 298 paddr_t kvtop(caddr_t); 299 void softnet(int); 300 301 extern paddr_t msgbuf_paddr; 302 extern int cpu_altivec; 303 #endif 304 305 #endif /* _KERNEL */ 306 307 #if defined(_KERNEL) || defined(_STANDALONE) 308 #if !defined(CACHELINESIZE) 309 #ifdef PPC_IBM403 310 #define CACHELINESIZE 16 311 #else 312 #define CACHELINESIZE 32 313 #endif 314 #endif 315 #endif 316 317 void __syncicache(void *, size_t); 318 319 /* 320 * CTL_MACHDEP definitions. 321 */ 322 #define CPU_CACHELINE 1 323 #define CPU_TIMEBASE 2 324 #define CPU_CPUTEMP 3 325 #define CPU_PRINTFATALTRAPS 4 326 #define CPU_CACHEINFO 5 327 #define CPU_ALTIVEC 6 328 #define CPU_MODEL 7 329 #define CPU_POWERSAVE 8 330 #define CPU_MAXID 9 331 332 #define CTL_MACHDEP_NAMES { \ 333 { 0, 0 }, \ 334 { "cachelinesize", CTLTYPE_INT }, \ 335 { "timebase", CTLTYPE_INT }, \ 336 { "cputempature", CTLTYPE_INT }, \ 337 { "printfataltraps", CTLTYPE_INT }, \ 338 { "cacheinfo", CTLTYPE_STRUCT }, \ 339 { "altivec", CTLTYPE_INT }, \ 340 { "model", CTLTYPE_STRING }, \ 341 { "powersave", CTLTYPE_INT }, \ 342 } 343 344 #endif /* _POWERPC_CPU_H_ */ 345
Indexes created Wed Sep 24 15:09:51 GMT 2025