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cpu.h revision 1.43 
      1 /*	$NetBSD: cpu.h,v 1.43 2005/01/19 22:22:56 matt Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 1999 Wolfgang Solfrank.
      5  * Copyright (C) 1999 TooLs GmbH.
      6  * Copyright (C) 1995-1997 Wolfgang Solfrank.
      7  * Copyright (C) 1995-1997 TooLs GmbH.
      8  * All rights reserved.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by TooLs GmbH.
     21  * 4. The name of TooLs GmbH may not be used to endorse or promote products
     22  *    derived from this software without specific prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
     25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     27  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     30  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     34  */
     35 #ifndef	_POWERPC_CPU_H_
     36 #define	_POWERPC_CPU_H_
     37 
     38 struct cache_info {
     39 	int dcache_size;
     40 	int dcache_line_size;
     41 	int icache_size;
     42 	int icache_line_size;
     43 };
     44 
     45 #ifdef _KERNEL
     46 #if defined(_KERNEL_OPT)
     47 #include "opt_lockdebug.h"
     48 #include "opt_multiprocessor.h"
     49 #include "opt_ppcarch.h"
     50 #endif
     51 
     52 #include <machine/frame.h>
     53 #include <machine/psl.h>
     54 #include <machine/intr.h>
     55 #include <sys/device.h>
     56 
     57 #include <sys/cpu_data.h>
     58 
     59 struct cpu_info {
     60 	struct cpu_data ci_data;	/* MI per-cpu data */
     61 	struct device *ci_dev;		/* device of corresponding cpu */
     62 	struct lwp *ci_curlwp;		/* current owner of the processor */
     63 
     64 	struct pcb *ci_curpcb;
     65 	struct pmap *ci_curpm;
     66 	struct lwp *ci_fpulwp;
     67 	struct lwp *ci_veclwp;
     68 	struct pcb *ci_idle_pcb;	/* PA of our idle pcb */
     69 	int ci_cpuid;
     70 
     71 	volatile int ci_astpending;
     72 	int ci_want_resched;
     73 	volatile u_long ci_lasttb;
     74 	volatile int ci_tickspending;
     75 	int ci_cpl;
     76 	int ci_iactive;
     77 	int ci_ipending;
     78 	int ci_intrdepth;
     79 	char *ci_intstk;
     80 #define	CPUSAVE_LEN	8
     81 	register_t ci_tempsave[CPUSAVE_LEN];
     82 	register_t ci_ddbsave[CPUSAVE_LEN];
     83 	register_t ci_ipkdbsave[CPUSAVE_LEN];
     84 #define	CPUSAVE_R28	0		/* where r28 gets saved */
     85 #define	CPUSAVE_R29	1		/* where r29 gets saved */
     86 #define	CPUSAVE_R30	2		/* where r30 gets saved */
     87 #define	CPUSAVE_R31	3		/* where r31 gets saved */
     88 #define	CPUSAVE_DAR	4		/* where SPR_DAR gets saved */
     89 #define	CPUSAVE_DSISR	5		/* where SPR_DSISR gets saved */
     90 #define	CPUSAVE_SRR0	6		/* where SRR0 gets saved */
     91 #define	CPUSAVE_SRR1	7		/* where SRR1 gets saved */
     92 #define	DISISAVE_LEN	4
     93 	register_t ci_disisave[DISISAVE_LEN];
     94 	struct cache_info ci_ci;
     95 	void *ci_sysmon_cookie;
     96 	void (*ci_idlespin)(void);
     97 	struct evcnt ci_ev_clock;	/* clock intrs */
     98 	struct evcnt ci_ev_softclock;	/* softclock intrs */
     99 	struct evcnt ci_ev_softnet;	/* softnet intrs */
    100 	struct evcnt ci_ev_softserial;	/* softserial intrs */
    101 	struct evcnt ci_ev_traps;	/* calls to trap() */
    102 	struct evcnt ci_ev_kdsi;	/* kernel DSI traps */
    103 	struct evcnt ci_ev_udsi;	/* user DSI traps */
    104 	struct evcnt ci_ev_udsi_fatal;	/* user DSI trap failures */
    105 	struct evcnt ci_ev_kisi;	/* kernel ISI traps */
    106 	struct evcnt ci_ev_isi;		/* user ISI traps */
    107 	struct evcnt ci_ev_isi_fatal;	/* user ISI trap failures */
    108 	struct evcnt ci_ev_pgm;		/* user PGM traps */
    109 	struct evcnt ci_ev_fpu;		/* FPU traps */
    110 	struct evcnt ci_ev_fpusw;	/* FPU context switch */
    111 	struct evcnt ci_ev_ali;		/* Alignment traps */
    112 	struct evcnt ci_ev_ali_fatal;	/* Alignment fatal trap */
    113 	struct evcnt ci_ev_scalls;	/* system call traps */
    114 	struct evcnt ci_ev_vec;		/* Altivec traps */
    115 	struct evcnt ci_ev_vecsw;	/* Altivec context switches */
    116 	struct evcnt ci_ev_umchk;	/* user MCHK events */
    117 };
    118 
    119 #ifdef MULTIPROCESSOR
    120 static __inline int
    121 cpu_number(void)
    122 {
    123 	int pir;
    124 
    125 	__asm ("mfspr %0,1023" : "=r"(pir));
    126 	return pir;
    127 }
    128 
    129 void	cpu_boot_secondary_processors(void);
    130 
    131 
    132 #define CPU_IS_PRIMARY(ci)	((ci)->ci_cpuid == 0)
    133 #define CPU_INFO_ITERATOR		int
    134 #define CPU_INFO_FOREACH(cii, ci)					\
    135 	cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++
    136 
    137 #else
    138 
    139 #define cpu_number()		0
    140 
    141 #define CPU_INFO_ITERATOR		int
    142 #define CPU_INFO_FOREACH(cii, ci)					\
    143 	cii = 0, ci = curcpu(); ci != NULL; ci = NULL
    144 
    145 #endif /* MULTIPROCESSOR */
    146 
    147 extern struct cpu_info cpu_info[];
    148 
    149 static __inline struct cpu_info *
    150 curcpu(void)
    151 {
    152 	struct cpu_info *ci;
    153 
    154 	__asm __volatile ("mfsprg %0,0" : "=r"(ci));
    155 	return ci;
    156 }
    157 
    158 #define curlwp			(curcpu()->ci_curlwp)
    159 #define curpcb			(curcpu()->ci_curpcb)
    160 #define curpm			(curcpu()->ci_curpm)
    161 
    162 static __inline register_t
    163 mfmsr(void)
    164 {
    165 	register_t msr;
    166 
    167 	__asm __volatile ("mfmsr %0" : "=r"(msr));
    168 	return msr;
    169 }
    170 
    171 static __inline void
    172 mtmsr(register_t msr)
    173 {
    174 
    175 	__asm __volatile ("mtmsr %0" : : "r"(msr));
    176 }
    177 
    178 static __inline uint32_t
    179 mftbl(void)
    180 {
    181 	uint32_t tbl;
    182 
    183 	__asm __volatile (
    184 #ifdef PPC_IBM403
    185 "	mftblo %0	\n"
    186 #else
    187 "	mftbl %0	\n"
    188 #endif
    189 	: "=r" (tbl));
    190 
    191 	return tbl;
    192 }
    193 
    194 static __inline uint64_t
    195 mftb(void)
    196 {
    197 	uint64_t tb;
    198 
    199 #ifdef _LP64
    200 	__asm __volatile ("mftb %0" : "=r"(tb));
    201 #else
    202 	int tmp;
    203 
    204 	__asm __volatile (
    205 #ifdef PPC_IBM403
    206 "1:	mftbhi %0	\n"
    207 "	mftblo %0+1	\n"
    208 "	mftbhi %1	\n"
    209 #else
    210 "1:	mftbu %0	\n"
    211 "	mftb %0+1	\n"
    212 "	mftbu %1	\n"
    213 #endif
    214 "	cmplw %0,%1	\n"
    215 "	bne- 1b		\n"
    216 	: "=r" (tb), "=r"(tmp) :: "cr0");
    217 #endif
    218 
    219 	return tb;
    220 }
    221 
    222 static __inline uint32_t
    223 mfrtcl(void)
    224 {
    225 	uint32_t rtcl;
    226 
    227 	__asm __volatile ("mfrtcl %0" : "=r"(rtcl));
    228 	return rtcl;
    229 }
    230 
    231 static __inline void
    232 mfrtc(uint32_t *rtcp)
    233 {
    234 	uint32_t tmp;
    235 
    236 	__asm __volatile (
    237 "1:	mfrtcu	%0	\n"
    238 "	mfrtcl	%1	\n"
    239 "	mfrtcu	%2	\n"
    240 "	cmplw	%0,%2	\n"
    241 "	bne-	1b"
    242 	    : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0");
    243 }
    244 
    245 static __inline uint32_t
    246 mfpvr(void)
    247 {
    248 	uint32_t pvr;
    249 
    250 	__asm __volatile ("mfpvr %0" : "=r"(pvr));
    251 	return (pvr);
    252 }
    253 
    254 /*
    255  * CLKF_BASEPRI is dependent on the underlying interrupt code
    256  * and can not be defined here.  It should be defined in
    257  * <machine/intr.h>
    258  */
    259 #define	CLKF_USERMODE(frame)	(((frame)->srr1 & PSL_PR) != 0)
    260 #define	CLKF_PC(frame)		((frame)->srr0)
    261 #define	CLKF_INTR(frame)	((frame)->depth > 0)
    262 
    263 #define	LWP_PC(l)		(trapframe(l)->srr0)
    264 
    265 #define	cpu_swapout(p)
    266 #define	cpu_proc_fork(p1, p2)
    267 
    268 extern int powersave;
    269 extern int cpu_timebase;
    270 extern int cpu_printfataltraps;
    271 extern char cpu_model[];
    272 
    273 struct cpu_info *cpu_attach_common(struct device *, int);
    274 void cpu_setup(struct device *, struct cpu_info *);
    275 void cpu_identify(char *, size_t);
    276 void delay (unsigned int);
    277 void cpu_probe_cache(void);
    278 void dcache_flush_page(vaddr_t);
    279 void icache_flush_page(vaddr_t);
    280 void dcache_flush(vaddr_t, vsize_t);
    281 void icache_flush(vaddr_t, vsize_t);
    282 void *mapiodev(paddr_t, psize_t);
    283 
    284 #define	DELAY(n)		delay(n)
    285 
    286 #define	need_resched(ci)	(ci->ci_want_resched = 1, ci->ci_astpending = 1)
    287 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1)
    288 #define	signotify(p)		(curcpu()->ci_astpending = 1)
    289 
    290 #ifdef PPC_OEA
    291 void oea_init(void (*)(void));
    292 void oea_startup(const char *);
    293 void oea_dumpsys(void);
    294 void oea_install_extint(void (*)(void));
    295 paddr_t kvtop(caddr_t);
    296 void softnet(int);
    297 
    298 extern paddr_t msgbuf_paddr;
    299 extern int cpu_altivec;
    300 #endif
    301 
    302 #endif /* _KERNEL */
    303 
    304 #if defined(_KERNEL) || defined(_STANDALONE)
    305 #if !defined(CACHELINESIZE)
    306 #ifdef PPC_IBM403
    307 #define	CACHELINESIZE	16
    308 #else
    309 #define	CACHELINESIZE	32
    310 #endif
    311 #endif
    312 #endif
    313 
    314 void __syncicache(void *, size_t);
    315 
    316 /*
    317  * CTL_MACHDEP definitions.
    318  */
    319 #define	CPU_CACHELINE		1
    320 #define	CPU_TIMEBASE		2
    321 #define	CPU_CPUTEMP		3
    322 #define	CPU_PRINTFATALTRAPS	4
    323 #define	CPU_CACHEINFO		5
    324 #define	CPU_ALTIVEC		6
    325 #define	CPU_MODEL		7
    326 #define	CPU_POWERSAVE		8
    327 #define	CPU_MAXID		9
    328 
    329 #define	CTL_MACHDEP_NAMES { \
    330 	{ 0, 0 }, \
    331 	{ "cachelinesize", CTLTYPE_INT }, \
    332 	{ "timebase", CTLTYPE_INT }, \
    333 	{ "cputempature", CTLTYPE_INT }, \
    334 	{ "printfataltraps", CTLTYPE_INT }, \
    335 	{ "cacheinfo", CTLTYPE_STRUCT }, \
    336 	{ "altivec", CTLTYPE_INT }, \
    337 	{ "model", CTLTYPE_STRING }, \
    338 	{ "powersave", CTLTYPE_INT }, \
    339 }
    340 
    341 #endif	/* _POWERPC_CPU_H_ */
    342