cpu.h revision 1.46
1 /* $NetBSD: cpu.h,v 1.46 2005/12/24 20:07:28 perry Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 struct pcb *ci_idle_pcb; /* PA of our idle pcb */ 69 int ci_cpuid; 70 71 volatile int ci_astpending; 72 int ci_want_resched; 73 volatile u_long ci_lasttb; 74 volatile int ci_tickspending; 75 int ci_cpl; 76 int ci_iactive; 77 int ci_ipending; 78 int ci_intrdepth; 79 char *ci_intstk; 80 #define CPUSAVE_LEN 8 81 register_t ci_tempsave[CPUSAVE_LEN]; 82 register_t ci_ddbsave[CPUSAVE_LEN]; 83 register_t ci_ipkdbsave[CPUSAVE_LEN]; 84 #define CPUSAVE_R28 0 /* where r28 gets saved */ 85 #define CPUSAVE_R29 1 /* where r29 gets saved */ 86 #define CPUSAVE_R30 2 /* where r30 gets saved */ 87 #define CPUSAVE_R31 3 /* where r31 gets saved */ 88 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 89 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 90 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 91 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 92 #define DISISAVE_LEN 4 93 register_t ci_disisave[DISISAVE_LEN]; 94 struct cache_info ci_ci; 95 void *ci_sysmon_cookie; 96 void (*ci_idlespin)(void); 97 uint32_t ci_khz; 98 struct evcnt ci_ev_clock; /* clock intrs */ 99 struct evcnt ci_ev_softclock; /* softclock intrs */ 100 struct evcnt ci_ev_softnet; /* softnet intrs */ 101 struct evcnt ci_ev_softserial; /* softserial intrs */ 102 struct evcnt ci_ev_traps; /* calls to trap() */ 103 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 104 struct evcnt ci_ev_udsi; /* user DSI traps */ 105 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 106 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 107 struct evcnt ci_ev_isi; /* user ISI traps */ 108 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 109 struct evcnt ci_ev_pgm; /* user PGM traps */ 110 struct evcnt ci_ev_fpu; /* FPU traps */ 111 struct evcnt ci_ev_fpusw; /* FPU context switch */ 112 struct evcnt ci_ev_ali; /* Alignment traps */ 113 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 114 struct evcnt ci_ev_scalls; /* system call traps */ 115 struct evcnt ci_ev_vec; /* Altivec traps */ 116 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 117 struct evcnt ci_ev_umchk; /* user MCHK events */ 118 }; 119 120 #ifdef MULTIPROCESSOR 121 static inline int 122 cpu_number(void) 123 { 124 int pir; 125 126 __asm ("mfspr %0,1023" : "=r"(pir)); 127 return pir; 128 } 129 130 void cpu_boot_secondary_processors(void); 131 132 133 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 134 #define CPU_INFO_ITERATOR int 135 #define CPU_INFO_FOREACH(cii, ci) \ 136 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 137 138 #else 139 140 #define cpu_number() 0 141 142 #define CPU_INFO_ITERATOR int 143 #define CPU_INFO_FOREACH(cii, ci) \ 144 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 145 146 #endif /* MULTIPROCESSOR */ 147 148 extern struct cpu_info cpu_info[]; 149 150 static inline struct cpu_info * 151 curcpu(void) 152 { 153 struct cpu_info *ci; 154 155 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 156 return ci; 157 } 158 159 #define curlwp (curcpu()->ci_curlwp) 160 #define curpcb (curcpu()->ci_curpcb) 161 #define curpm (curcpu()->ci_curpm) 162 163 static inline register_t 164 mfmsr(void) 165 { 166 register_t msr; 167 168 __asm volatile ("mfmsr %0" : "=r"(msr)); 169 return msr; 170 } 171 172 static inline void 173 mtmsr(register_t msr) 174 { 175 176 __asm volatile ("mtmsr %0" : : "r"(msr)); 177 } 178 179 static inline uint32_t 180 mftbl(void) 181 { 182 uint32_t tbl; 183 184 __asm volatile ( 185 #ifdef PPC_IBM403 186 " mftblo %0 \n" 187 #else 188 " mftbl %0 \n" 189 #endif 190 : "=r" (tbl)); 191 192 return tbl; 193 } 194 195 static inline uint64_t 196 mftb(void) 197 { 198 uint64_t tb; 199 200 #ifdef _LP64 201 __asm volatile ("mftb %0" : "=r"(tb)); 202 #else 203 int tmp; 204 205 __asm volatile ( 206 #ifdef PPC_IBM403 207 "1: mftbhi %0 \n" 208 " mftblo %0+1 \n" 209 " mftbhi %1 \n" 210 #else 211 "1: mftbu %0 \n" 212 " mftb %0+1 \n" 213 " mftbu %1 \n" 214 #endif 215 " cmplw %0,%1 \n" 216 " bne- 1b \n" 217 : "=r" (tb), "=r"(tmp) :: "cr0"); 218 #endif 219 220 return tb; 221 } 222 223 static inline uint32_t 224 mfrtcl(void) 225 { 226 uint32_t rtcl; 227 228 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 229 return rtcl; 230 } 231 232 static inline void 233 mfrtc(uint32_t *rtcp) 234 { 235 uint32_t tmp; 236 237 __asm volatile ( 238 "1: mfrtcu %0 \n" 239 " mfrtcl %1 \n" 240 " mfrtcu %2 \n" 241 " cmplw %0,%2 \n" 242 " bne- 1b" 243 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 244 } 245 246 static inline uint32_t 247 mfpvr(void) 248 { 249 uint32_t pvr; 250 251 __asm volatile ("mfpvr %0" : "=r"(pvr)); 252 return (pvr); 253 } 254 255 /* 256 * CLKF_BASEPRI is dependent on the underlying interrupt code 257 * and can not be defined here. It should be defined in 258 * <machine/intr.h> 259 */ 260 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 261 #define CLKF_PC(frame) ((frame)->srr0) 262 #define CLKF_INTR(frame) ((frame)->depth > 0) 263 264 #define LWP_PC(l) (trapframe(l)->srr0) 265 266 #define cpu_swapout(p) 267 #define cpu_proc_fork(p1, p2) 268 269 extern int powersave; 270 extern int cpu_timebase; 271 extern int cpu_printfataltraps; 272 extern char cpu_model[]; 273 274 struct cpu_info *cpu_attach_common(struct device *, int); 275 void cpu_setup(struct device *, struct cpu_info *); 276 void cpu_identify(char *, size_t); 277 void delay (unsigned int); 278 void cpu_probe_cache(void); 279 void dcache_flush_page(vaddr_t); 280 void icache_flush_page(vaddr_t); 281 void dcache_flush(vaddr_t, vsize_t); 282 void icache_flush(vaddr_t, vsize_t); 283 void *mapiodev(paddr_t, psize_t); 284 285 #define DELAY(n) delay(n) 286 287 #define need_resched(ci) (ci->ci_want_resched = 1, ci->ci_astpending = 1) 288 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, curcpu()->ci_astpending = 1) 289 #define signotify(p) (curcpu()->ci_astpending = 1) 290 291 #ifdef PPC_OEA 292 void oea_init(void (*)(void)); 293 void oea_startup(const char *); 294 void oea_dumpsys(void); 295 void oea_install_extint(void (*)(void)); 296 paddr_t kvtop(caddr_t); 297 void softnet(int); 298 299 extern paddr_t msgbuf_paddr; 300 extern int cpu_altivec; 301 #endif 302 303 #endif /* _KERNEL */ 304 305 #if defined(_KERNEL) || defined(_STANDALONE) 306 #if !defined(CACHELINESIZE) 307 #ifdef PPC_IBM403 308 #define CACHELINESIZE 16 309 #else 310 #define CACHELINESIZE 32 311 #endif 312 #endif 313 #endif 314 315 void __syncicache(void *, size_t); 316 317 /* 318 * CTL_MACHDEP definitions. 319 */ 320 #define CPU_CACHELINE 1 321 #define CPU_TIMEBASE 2 322 #define CPU_CPUTEMP 3 323 #define CPU_PRINTFATALTRAPS 4 324 #define CPU_CACHEINFO 5 325 #define CPU_ALTIVEC 6 326 #define CPU_MODEL 7 327 #define CPU_POWERSAVE 8 328 #define CPU_MAXID 9 329 330 #define CTL_MACHDEP_NAMES { \ 331 { 0, 0 }, \ 332 { "cachelinesize", CTLTYPE_INT }, \ 333 { "timebase", CTLTYPE_INT }, \ 334 { "cputempature", CTLTYPE_INT }, \ 335 { "printfataltraps", CTLTYPE_INT }, \ 336 { "cacheinfo", CTLTYPE_STRUCT }, \ 337 { "altivec", CTLTYPE_INT }, \ 338 { "model", CTLTYPE_STRING }, \ 339 { "powersave", CTLTYPE_INT }, \ 340 } 341 342 #endif /* _POWERPC_CPU_H_ */ 343
Indexes created Mon Sep 22 13:09:51 GMT 2025