cpu.h revision 1.55.10.4
1 /* $NetBSD: cpu.h,v 1.55.10.4 2007/10/04 18:23:39 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 int ci_cpuid; 69 70 volatile int ci_astpending; 71 int ci_want_resched; 72 volatile u_long ci_lasttb; 73 volatile int ci_tickspending; 74 volatile int ci_cpl; 75 volatile int ci_iactive; 76 volatile int ci_ipending; 77 int ci_intrdepth; 78 int ci_mtx_oldspl; 79 int ci_mtx_count; 80 char *ci_intstk; 81 #define CPUSAVE_LEN 8 82 register_t ci_tempsave[CPUSAVE_LEN]; 83 register_t ci_ddbsave[CPUSAVE_LEN]; 84 register_t ci_ipkdbsave[CPUSAVE_LEN]; 85 #define CPUSAVE_R28 0 /* where r28 gets saved */ 86 #define CPUSAVE_R29 1 /* where r29 gets saved */ 87 #define CPUSAVE_R30 2 /* where r30 gets saved */ 88 #define CPUSAVE_R31 3 /* where r31 gets saved */ 89 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 90 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 91 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 92 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 93 #define DISISAVE_LEN 4 94 register_t ci_disisave[DISISAVE_LEN]; 95 struct cache_info ci_ci; 96 void *ci_sysmon_cookie; 97 void (*ci_idlespin)(void); 98 uint32_t ci_khz; 99 struct evcnt ci_ev_clock; /* clock intrs */ 100 struct evcnt ci_ev_statclock; /* stat clock */ 101 struct evcnt ci_ev_softclock; /* softclock intrs */ 102 struct evcnt ci_ev_softnet; /* softnet intrs */ 103 struct evcnt ci_ev_softserial; /* softserial intrs */ 104 struct evcnt ci_ev_traps; /* calls to trap() */ 105 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 106 struct evcnt ci_ev_udsi; /* user DSI traps */ 107 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 108 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 109 struct evcnt ci_ev_isi; /* user ISI traps */ 110 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 111 struct evcnt ci_ev_pgm; /* user PGM traps */ 112 struct evcnt ci_ev_fpu; /* FPU traps */ 113 struct evcnt ci_ev_fpusw; /* FPU context switch */ 114 struct evcnt ci_ev_ali; /* Alignment traps */ 115 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 116 struct evcnt ci_ev_scalls; /* system call traps */ 117 struct evcnt ci_ev_vec; /* Altivec traps */ 118 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 119 struct evcnt ci_ev_umchk; /* user MCHK events */ 120 struct evcnt ci_ev_ipi; /* IPIs received */ 121 }; 122 123 #ifdef MULTIPROCESSOR 124 static __inline int 125 cpu_number(void) 126 { 127 int pir; 128 129 __asm ("mfspr %0,1023" : "=r"(pir)); 130 return pir; 131 } 132 133 void cpu_boot_secondary_processors(void); 134 135 136 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 137 #define CPU_INFO_ITERATOR int 138 #define CPU_INFO_FOREACH(cii, ci) \ 139 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 140 141 #else 142 143 #define cpu_number() 0 144 145 #define CPU_INFO_ITERATOR int 146 #define CPU_INFO_FOREACH(cii, ci) \ 147 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 148 149 #endif /* MULTIPROCESSOR */ 150 151 extern struct cpu_info cpu_info[]; 152 153 static __inline struct cpu_info * 154 curcpu(void) 155 { 156 struct cpu_info *ci; 157 158 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 159 return ci; 160 } 161 162 #define curlwp (curcpu()->ci_curlwp) 163 #define curpcb (curcpu()->ci_curpcb) 164 #define curpm (curcpu()->ci_curpm) 165 166 static __inline register_t 167 mfmsr(void) 168 { 169 register_t msr; 170 171 __asm volatile ("mfmsr %0" : "=r"(msr)); 172 return msr; 173 } 174 175 static __inline void 176 mtmsr(register_t msr) 177 { 178 179 __asm volatile ("mtmsr %0" : : "r"(msr)); 180 } 181 182 static __inline uint32_t 183 mftbl(void) 184 { 185 uint32_t tbl; 186 187 __asm volatile ( 188 #ifdef PPC_IBM403 189 " mftblo %0 \n" 190 #else 191 " mftbl %0 \n" 192 #endif 193 : "=r" (tbl)); 194 195 return tbl; 196 } 197 198 static __inline uint64_t 199 mftb(void) 200 { 201 uint64_t tb; 202 203 #ifdef _LP64 204 __asm volatile ("mftb %0" : "=r"(tb)); 205 #else 206 int tmp; 207 208 __asm volatile ( 209 #ifdef PPC_IBM403 210 "1: mftbhi %0 \n" 211 " mftblo %0+1 \n" 212 " mftbhi %1 \n" 213 #else 214 "1: mftbu %0 \n" 215 " mftb %0+1 \n" 216 " mftbu %1 \n" 217 #endif 218 " cmplw %0,%1 \n" 219 " bne- 1b \n" 220 : "=r" (tb), "=r"(tmp) :: "cr0"); 221 #endif 222 223 return tb; 224 } 225 226 static __inline uint32_t 227 mfrtcl(void) 228 { 229 uint32_t rtcl; 230 231 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 232 return rtcl; 233 } 234 235 static __inline void 236 mfrtc(uint32_t *rtcp) 237 { 238 uint32_t tmp; 239 240 __asm volatile ( 241 "1: mfrtcu %0 \n" 242 " mfrtcl %1 \n" 243 " mfrtcu %2 \n" 244 " cmplw %0,%2 \n" 245 " bne- 1b" 246 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 247 } 248 249 static __inline uint32_t 250 mfpvr(void) 251 { 252 uint32_t pvr; 253 254 __asm volatile ("mfpvr %0" : "=r"(pvr)); 255 return (pvr); 256 } 257 258 static __inline int 259 cntlzw(uint32_t val) 260 { 261 int cnt; 262 263 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 264 return (cnt); 265 } 266 267 #if defined(PPC_IBM4XX) || defined(PPC_IBM403) 268 /* 269 * DCR (Device Control Register) access. These have to be 270 * macros because register address is encoded as immediate 271 * operand. 272 */ 273 #define mtdcr(reg, val) \ 274 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val)) 275 276 #define mfdcr(reg) \ 277 ({ \ 278 uint32_t __val; \ 279 \ 280 __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \ 281 __val; \ 282 }) 283 #endif /* PPC_IBM4XX || PPC_IBM403 */ 284 285 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 286 #define CLKF_PC(frame) ((frame)->srr0) 287 #define CLKF_INTR(frame) ((frame)->depth > 0) 288 289 #define LWP_PC(l) (trapframe(l)->srr0) 290 291 #define cpu_swapin(p) 292 #define cpu_swapout(p) 293 #define cpu_proc_fork(p1, p2) 294 #define cpu_idle() (curcpu()->ci_idlespin()) 295 #define cpu_lwp_free2(l) 296 297 extern int powersave; 298 extern int cpu_timebase; 299 extern int cpu_printfataltraps; 300 extern char cpu_model[]; 301 302 struct cpu_info *cpu_attach_common(struct device *, int); 303 void cpu_setup(struct device *, struct cpu_info *); 304 void cpu_identify(char *, size_t); 305 void delay (unsigned int); 306 void cpu_probe_cache(void); 307 void dcache_flush_page(vaddr_t); 308 void icache_flush_page(vaddr_t); 309 void dcache_flush(vaddr_t, vsize_t); 310 void icache_flush(vaddr_t, vsize_t); 311 void *mapiodev(paddr_t, psize_t); 312 void unmapiodev(vaddr_t, vsize_t); 313 314 #define DELAY(n) delay(n) 315 316 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1) 317 #define cpu_did_resched() ((void)(curcpu()->ci_want_resched = 0)) 318 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1) 319 #define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */ 320 321 #if defined(PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE) 322 void oea_init(void (*)(void)); 323 void oea_startup(const char *); 324 void oea_dumpsys(void); 325 void oea_install_extint(void (*)(void)); 326 paddr_t kvtop(void *); 327 void softnet(int); 328 329 extern paddr_t msgbuf_paddr; 330 extern int cpu_altivec; 331 #endif 332 333 #endif /* _KERNEL */ 334 335 #if defined(_KERNEL) || defined(_STANDALONE) 336 #if !defined(CACHELINESIZE) 337 #ifdef PPC_IBM403 338 #define CACHELINESIZE 16 339 #else 340 #if defined (PPC_OEA64_BRIDGE) 341 #define CACHELINESIZE 128 342 #else 343 #define CACHELINESIZE 32 344 #endif /* PPC_OEA64_BRIDGE */ 345 #endif 346 #endif 347 #endif 348 349 void __syncicache(void *, size_t); 350 351 /* 352 * CTL_MACHDEP definitions. 353 */ 354 #define CPU_CACHELINE 1 355 #define CPU_TIMEBASE 2 356 #define CPU_CPUTEMP 3 357 #define CPU_PRINTFATALTRAPS 4 358 #define CPU_CACHEINFO 5 359 #define CPU_ALTIVEC 6 360 #define CPU_MODEL 7 361 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 362 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 363 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 364 #define CPU_MAXID 11 /* number of valid machdep ids */ 365 366 #define CTL_MACHDEP_NAMES { \ 367 { 0, 0 }, \ 368 { "cachelinesize", CTLTYPE_INT }, \ 369 { "timebase", CTLTYPE_INT }, \ 370 { "cputempature", CTLTYPE_INT }, \ 371 { "printfataltraps", CTLTYPE_INT }, \ 372 { "cacheinfo", CTLTYPE_STRUCT }, \ 373 { "altivec", CTLTYPE_INT }, \ 374 { "model", CTLTYPE_STRING }, \ 375 { "powersave", CTLTYPE_INT }, \ 376 } 377 378 #endif /* _POWERPC_CPU_H_ */ 379
Indexes created Thu Oct 16 14:10:15 GMT 2025