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cpu.h revision 1.56 
      1 /*	$NetBSD: cpu.h,v 1.56 2007/05/17 14:51:26 yamt Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 1999 Wolfgang Solfrank.
      5  * Copyright (C) 1999 TooLs GmbH.
      6  * Copyright (C) 1995-1997 Wolfgang Solfrank.
      7  * Copyright (C) 1995-1997 TooLs GmbH.
      8  * All rights reserved.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by TooLs GmbH.
     21  * 4. The name of TooLs GmbH may not be used to endorse or promote products
     22  *    derived from this software without specific prior written permission.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
     25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     27  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     30  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     34  */
     35 #ifndef	_POWERPC_CPU_H_
     36 #define	_POWERPC_CPU_H_
     37 
     38 struct cache_info {
     39 	int dcache_size;
     40 	int dcache_line_size;
     41 	int icache_size;
     42 	int icache_line_size;
     43 };
     44 
     45 #ifdef _KERNEL
     46 #if defined(_KERNEL_OPT)
     47 #include "opt_lockdebug.h"
     48 #include "opt_multiprocessor.h"
     49 #include "opt_ppcarch.h"
     50 #endif
     51 
     52 #include <machine/frame.h>
     53 #include <machine/psl.h>
     54 #include <machine/intr.h>
     55 #include <sys/device.h>
     56 
     57 #include <sys/cpu_data.h>
     58 
     59 struct cpu_info {
     60 	struct cpu_data ci_data;	/* MI per-cpu data */
     61 	struct device *ci_dev;		/* device of corresponding cpu */
     62 	struct lwp *ci_curlwp;		/* current owner of the processor */
     63 
     64 	struct pcb *ci_curpcb;
     65 	struct pmap *ci_curpm;
     66 	struct lwp *ci_fpulwp;
     67 	struct lwp *ci_veclwp;
     68 	int ci_cpuid;
     69 
     70 	volatile int ci_astpending;
     71 	int ci_need_resched;
     72 	volatile u_long ci_lasttb;
     73 	volatile int ci_tickspending;
     74 	volatile int ci_cpl;
     75 	volatile int ci_iactive;
     76 	volatile int ci_ipending;
     77 	int ci_intrdepth;
     78 	int ci_mtx_oldspl;
     79 	int ci_mtx_count;
     80 	char *ci_intstk;
     81 #define	CPUSAVE_LEN	8
     82 	register_t ci_tempsave[CPUSAVE_LEN];
     83 	register_t ci_ddbsave[CPUSAVE_LEN];
     84 	register_t ci_ipkdbsave[CPUSAVE_LEN];
     85 #define	CPUSAVE_R28	0		/* where r28 gets saved */
     86 #define	CPUSAVE_R29	1		/* where r29 gets saved */
     87 #define	CPUSAVE_R30	2		/* where r30 gets saved */
     88 #define	CPUSAVE_R31	3		/* where r31 gets saved */
     89 #define	CPUSAVE_DAR	4		/* where SPR_DAR gets saved */
     90 #define	CPUSAVE_DSISR	5		/* where SPR_DSISR gets saved */
     91 #define	CPUSAVE_SRR0	6		/* where SRR0 gets saved */
     92 #define	CPUSAVE_SRR1	7		/* where SRR1 gets saved */
     93 #define	DISISAVE_LEN	4
     94 	register_t ci_disisave[DISISAVE_LEN];
     95 	struct cache_info ci_ci;
     96 	void *ci_sysmon_cookie;
     97 	void (*ci_idlespin)(void);
     98 	uint32_t ci_khz;
     99 	struct evcnt ci_ev_clock;	/* clock intrs */
    100 	struct evcnt ci_ev_statclock; 	/* stat clock */
    101 	struct evcnt ci_ev_softclock;	/* softclock intrs */
    102 	struct evcnt ci_ev_softnet;	/* softnet intrs */
    103 	struct evcnt ci_ev_softserial;	/* softserial intrs */
    104 	struct evcnt ci_ev_traps;	/* calls to trap() */
    105 	struct evcnt ci_ev_kdsi;	/* kernel DSI traps */
    106 	struct evcnt ci_ev_udsi;	/* user DSI traps */
    107 	struct evcnt ci_ev_udsi_fatal;	/* user DSI trap failures */
    108 	struct evcnt ci_ev_kisi;	/* kernel ISI traps */
    109 	struct evcnt ci_ev_isi;		/* user ISI traps */
    110 	struct evcnt ci_ev_isi_fatal;	/* user ISI trap failures */
    111 	struct evcnt ci_ev_pgm;		/* user PGM traps */
    112 	struct evcnt ci_ev_fpu;		/* FPU traps */
    113 	struct evcnt ci_ev_fpusw;	/* FPU context switch */
    114 	struct evcnt ci_ev_ali;		/* Alignment traps */
    115 	struct evcnt ci_ev_ali_fatal;	/* Alignment fatal trap */
    116 	struct evcnt ci_ev_scalls;	/* system call traps */
    117 	struct evcnt ci_ev_vec;		/* Altivec traps */
    118 	struct evcnt ci_ev_vecsw;	/* Altivec context switches */
    119 	struct evcnt ci_ev_umchk;	/* user MCHK events */
    120 };
    121 
    122 #ifdef MULTIPROCESSOR
    123 static __inline int
    124 cpu_number(void)
    125 {
    126 	int pir;
    127 
    128 	__asm ("mfspr %0,1023" : "=r"(pir));
    129 	return pir;
    130 }
    131 
    132 void	cpu_boot_secondary_processors(void);
    133 
    134 
    135 #define CPU_IS_PRIMARY(ci)	((ci)->ci_cpuid == 0)
    136 #define CPU_INFO_ITERATOR		int
    137 #define CPU_INFO_FOREACH(cii, ci)					\
    138 	cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++
    139 
    140 #else
    141 
    142 #define cpu_number()		0
    143 
    144 #define CPU_INFO_ITERATOR		int
    145 #define CPU_INFO_FOREACH(cii, ci)					\
    146 	cii = 0, ci = curcpu(); ci != NULL; ci = NULL
    147 
    148 #endif /* MULTIPROCESSOR */
    149 
    150 extern struct cpu_info cpu_info[];
    151 
    152 static __inline struct cpu_info *
    153 curcpu(void)
    154 {
    155 	struct cpu_info *ci;
    156 
    157 	__asm volatile ("mfsprg %0,0" : "=r"(ci));
    158 	return ci;
    159 }
    160 
    161 #define curlwp			(curcpu()->ci_curlwp)
    162 #define curpcb			(curcpu()->ci_curpcb)
    163 #define curpm			(curcpu()->ci_curpm)
    164 
    165 static __inline register_t
    166 mfmsr(void)
    167 {
    168 	register_t msr;
    169 
    170 	__asm volatile ("mfmsr %0" : "=r"(msr));
    171 	return msr;
    172 }
    173 
    174 static __inline void
    175 mtmsr(register_t msr)
    176 {
    177 
    178 	__asm volatile ("mtmsr %0" : : "r"(msr));
    179 }
    180 
    181 static __inline uint32_t
    182 mftbl(void)
    183 {
    184 	uint32_t tbl;
    185 
    186 	__asm volatile (
    187 #ifdef PPC_IBM403
    188 "	mftblo %0	\n"
    189 #else
    190 "	mftbl %0	\n"
    191 #endif
    192 	: "=r" (tbl));
    193 
    194 	return tbl;
    195 }
    196 
    197 static __inline uint64_t
    198 mftb(void)
    199 {
    200 	uint64_t tb;
    201 
    202 #ifdef _LP64
    203 	__asm volatile ("mftb %0" : "=r"(tb));
    204 #else
    205 	int tmp;
    206 
    207 	__asm volatile (
    208 #ifdef PPC_IBM403
    209 "1:	mftbhi %0	\n"
    210 "	mftblo %0+1	\n"
    211 "	mftbhi %1	\n"
    212 #else
    213 "1:	mftbu %0	\n"
    214 "	mftb %0+1	\n"
    215 "	mftbu %1	\n"
    216 #endif
    217 "	cmplw %0,%1	\n"
    218 "	bne- 1b		\n"
    219 	: "=r" (tb), "=r"(tmp) :: "cr0");
    220 #endif
    221 
    222 	return tb;
    223 }
    224 
    225 static __inline uint32_t
    226 mfrtcl(void)
    227 {
    228 	uint32_t rtcl;
    229 
    230 	__asm volatile ("mfrtcl %0" : "=r"(rtcl));
    231 	return rtcl;
    232 }
    233 
    234 static __inline void
    235 mfrtc(uint32_t *rtcp)
    236 {
    237 	uint32_t tmp;
    238 
    239 	__asm volatile (
    240 "1:	mfrtcu	%0	\n"
    241 "	mfrtcl	%1	\n"
    242 "	mfrtcu	%2	\n"
    243 "	cmplw	%0,%2	\n"
    244 "	bne-	1b"
    245 	    : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0");
    246 }
    247 
    248 static __inline uint32_t
    249 mfpvr(void)
    250 {
    251 	uint32_t pvr;
    252 
    253 	__asm volatile ("mfpvr %0" : "=r"(pvr));
    254 	return (pvr);
    255 }
    256 
    257 static __inline int
    258 cntlzw(uint32_t val)
    259 {
    260 	int 			cnt;
    261 
    262 	__asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val));
    263 	return (cnt);
    264 }
    265 
    266 #if defined(PPC_IBM4XX) || defined(PPC_IBM403)
    267 /*
    268  * DCR (Device Control Register) access. These have to be
    269  * macros because register address is encoded as immediate
    270  * operand.
    271  */
    272 #define mtdcr(reg, val) 					\
    273 	__asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val))
    274 
    275 #define mfdcr(reg)						\
    276 ({								\
    277 	uint32_t __val;						\
    278 								\
    279 	__asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \
    280 	__val;							\
    281 })
    282 #endif /* PPC_IBM4XX || PPC_IBM403 */
    283 
    284 #define	CLKF_USERMODE(frame)	(((frame)->srr1 & PSL_PR) != 0)
    285 #define	CLKF_PC(frame)		((frame)->srr0)
    286 #define	CLKF_INTR(frame)	((frame)->depth > 0)
    287 
    288 #define	LWP_PC(l)		(trapframe(l)->srr0)
    289 
    290 #define	cpu_swapin(p)
    291 #define	cpu_swapout(p)
    292 #define	cpu_proc_fork(p1, p2)
    293 #define	cpu_idle()		(curcpu()->ci_idlespin())
    294 #define cpu_lwp_free2(l)
    295 
    296 extern int powersave;
    297 extern int cpu_timebase;
    298 extern int cpu_printfataltraps;
    299 extern char cpu_model[];
    300 
    301 struct cpu_info *cpu_attach_common(struct device *, int);
    302 void cpu_setup(struct device *, struct cpu_info *);
    303 void cpu_identify(char *, size_t);
    304 void delay (unsigned int);
    305 void cpu_probe_cache(void);
    306 void dcache_flush_page(vaddr_t);
    307 void icache_flush_page(vaddr_t);
    308 void dcache_flush(vaddr_t, vsize_t);
    309 void icache_flush(vaddr_t, vsize_t);
    310 void *mapiodev(paddr_t, psize_t);
    311 void unmapiodev(vaddr_t, vsize_t);
    312 
    313 #define	DELAY(n)		delay(n)
    314 
    315 #define	cpu_need_resched(ci, v)	(ci->ci_need_resched = ci->ci_astpending = 1)
    316 #define	cpu_did_resched()	((void)(curcpu()->ci_need_resched = 0))
    317 #define	cpu_need_proftick(l)	((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1)
    318 #define	cpu_signotify(l)	(curcpu()->ci_astpending = 1)	/* XXXSMP */
    319 
    320 #if defined(PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE)
    321 void oea_init(void (*)(void));
    322 void oea_startup(const char *);
    323 void oea_dumpsys(void);
    324 void oea_install_extint(void (*)(void));
    325 paddr_t kvtop(void *);
    326 void softnet(int);
    327 
    328 extern paddr_t msgbuf_paddr;
    329 extern int cpu_altivec;
    330 #endif
    331 
    332 #endif /* _KERNEL */
    333 
    334 #if defined(_KERNEL) || defined(_STANDALONE)
    335 #if !defined(CACHELINESIZE)
    336 #ifdef PPC_IBM403
    337 #define	CACHELINESIZE	16
    338 #else
    339 #if defined (PPC_OEA64_BRIDGE)
    340 #define	CACHELINESIZE	128
    341 #else
    342 #define	CACHELINESIZE	32
    343 #endif /* PPC_OEA64_BRIDGE */
    344 #endif
    345 #endif
    346 #endif
    347 
    348 void __syncicache(void *, size_t);
    349 
    350 /*
    351  * CTL_MACHDEP definitions.
    352  */
    353 #define	CPU_CACHELINE		1
    354 #define	CPU_TIMEBASE		2
    355 #define	CPU_CPUTEMP		3
    356 #define	CPU_PRINTFATALTRAPS	4
    357 #define	CPU_CACHEINFO		5
    358 #define	CPU_ALTIVEC		6
    359 #define	CPU_MODEL		7
    360 #define	CPU_POWERSAVE		8
    361 #define	CPU_MAXID		9
    362 
    363 #define	CTL_MACHDEP_NAMES { \
    364 	{ 0, 0 }, \
    365 	{ "cachelinesize", CTLTYPE_INT }, \
    366 	{ "timebase", CTLTYPE_INT }, \
    367 	{ "cputempature", CTLTYPE_INT }, \
    368 	{ "printfataltraps", CTLTYPE_INT }, \
    369 	{ "cacheinfo", CTLTYPE_STRUCT }, \
    370 	{ "altivec", CTLTYPE_INT }, \
    371 	{ "model", CTLTYPE_STRING }, \
    372 	{ "powersave", CTLTYPE_INT }, \
    373 }
    374 
    375 #endif	/* _POWERPC_CPU_H_ */
    376