cpu.h revision 1.59
1 /* $NetBSD: cpu.h,v 1.59 2007/10/17 19:56:40 garbled Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 int ci_cpuid; 69 70 volatile int ci_astpending; 71 int ci_want_resched; 72 volatile u_long ci_lasttb; 73 volatile int ci_tickspending; 74 volatile int ci_cpl; 75 volatile int ci_iactive; 76 volatile int ci_ipending; 77 int ci_intrdepth; 78 int ci_mtx_oldspl; 79 int ci_mtx_count; 80 char *ci_intstk; 81 #define CPUSAVE_LEN 8 82 register_t ci_tempsave[CPUSAVE_LEN]; 83 register_t ci_ddbsave[CPUSAVE_LEN]; 84 register_t ci_ipkdbsave[CPUSAVE_LEN]; 85 #define CPUSAVE_R28 0 /* where r28 gets saved */ 86 #define CPUSAVE_R29 1 /* where r29 gets saved */ 87 #define CPUSAVE_R30 2 /* where r30 gets saved */ 88 #define CPUSAVE_R31 3 /* where r31 gets saved */ 89 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 90 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 91 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 92 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 93 #define DISISAVE_LEN 4 94 register_t ci_disisave[DISISAVE_LEN]; 95 struct cache_info ci_ci; 96 void *ci_sysmon_cookie; 97 void (*ci_idlespin)(void); 98 uint32_t ci_khz; 99 struct evcnt ci_ev_clock; /* clock intrs */ 100 struct evcnt ci_ev_statclock; /* stat clock */ 101 struct evcnt ci_ev_softclock; /* softclock intrs */ 102 struct evcnt ci_ev_softnet; /* softnet intrs */ 103 struct evcnt ci_ev_softserial; /* softserial intrs */ 104 struct evcnt ci_ev_traps; /* calls to trap() */ 105 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 106 struct evcnt ci_ev_udsi; /* user DSI traps */ 107 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 108 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 109 struct evcnt ci_ev_isi; /* user ISI traps */ 110 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 111 struct evcnt ci_ev_pgm; /* user PGM traps */ 112 struct evcnt ci_ev_fpu; /* FPU traps */ 113 struct evcnt ci_ev_fpusw; /* FPU context switch */ 114 struct evcnt ci_ev_ali; /* Alignment traps */ 115 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 116 struct evcnt ci_ev_scalls; /* system call traps */ 117 struct evcnt ci_ev_vec; /* Altivec traps */ 118 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 119 struct evcnt ci_ev_umchk; /* user MCHK events */ 120 struct evcnt ci_ev_ipi; /* IPIs received */ 121 }; 122 123 #ifdef MULTIPROCESSOR 124 125 struct cpu_hatch_data { 126 struct device *self; 127 struct cpu_info *ci; 128 int running; 129 int pir; 130 int hid0; 131 int sdr1; 132 int sr[16]; 133 int batu[4], batl[4]; 134 int tbu, tbl; 135 }; 136 137 static __inline int 138 cpu_number(void) 139 { 140 int pir; 141 142 __asm ("mfspr %0,1023" : "=r"(pir)); 143 return pir; 144 } 145 146 void cpu_boot_secondary_processors(void); 147 148 149 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 150 #define CPU_INFO_ITERATOR int 151 #define CPU_INFO_FOREACH(cii, ci) \ 152 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 153 154 #else 155 156 #define cpu_number() 0 157 158 #define CPU_INFO_ITERATOR int 159 #define CPU_INFO_FOREACH(cii, ci) \ 160 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 161 162 #endif /* MULTIPROCESSOR */ 163 164 extern struct cpu_info cpu_info[]; 165 166 static __inline struct cpu_info * 167 curcpu(void) 168 { 169 struct cpu_info *ci; 170 171 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 172 return ci; 173 } 174 175 #define curlwp (curcpu()->ci_curlwp) 176 #define curpcb (curcpu()->ci_curpcb) 177 #define curpm (curcpu()->ci_curpm) 178 179 static __inline register_t 180 mfmsr(void) 181 { 182 register_t msr; 183 184 __asm volatile ("mfmsr %0" : "=r"(msr)); 185 return msr; 186 } 187 188 static __inline void 189 mtmsr(register_t msr) 190 { 191 192 __asm volatile ("mtmsr %0" : : "r"(msr)); 193 } 194 195 static __inline uint32_t 196 mftbl(void) 197 { 198 uint32_t tbl; 199 200 __asm volatile ( 201 #ifdef PPC_IBM403 202 " mftblo %0 \n" 203 #else 204 " mftbl %0 \n" 205 #endif 206 : "=r" (tbl)); 207 208 return tbl; 209 } 210 211 static __inline uint64_t 212 mftb(void) 213 { 214 uint64_t tb; 215 216 #ifdef _LP64 217 __asm volatile ("mftb %0" : "=r"(tb)); 218 #else 219 int tmp; 220 221 __asm volatile ( 222 #ifdef PPC_IBM403 223 "1: mftbhi %0 \n" 224 " mftblo %0+1 \n" 225 " mftbhi %1 \n" 226 #else 227 "1: mftbu %0 \n" 228 " mftb %0+1 \n" 229 " mftbu %1 \n" 230 #endif 231 " cmplw %0,%1 \n" 232 " bne- 1b \n" 233 : "=r" (tb), "=r"(tmp) :: "cr0"); 234 #endif 235 236 return tb; 237 } 238 239 static __inline uint32_t 240 mfrtcl(void) 241 { 242 uint32_t rtcl; 243 244 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 245 return rtcl; 246 } 247 248 static __inline void 249 mfrtc(uint32_t *rtcp) 250 { 251 uint32_t tmp; 252 253 __asm volatile ( 254 "1: mfrtcu %0 \n" 255 " mfrtcl %1 \n" 256 " mfrtcu %2 \n" 257 " cmplw %0,%2 \n" 258 " bne- 1b" 259 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 260 } 261 262 static __inline uint32_t 263 mfpvr(void) 264 { 265 uint32_t pvr; 266 267 __asm volatile ("mfpvr %0" : "=r"(pvr)); 268 return (pvr); 269 } 270 271 static __inline int 272 cntlzw(uint32_t val) 273 { 274 int cnt; 275 276 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 277 return (cnt); 278 } 279 280 #if defined(PPC_IBM4XX) || defined(PPC_IBM403) 281 /* 282 * DCR (Device Control Register) access. These have to be 283 * macros because register address is encoded as immediate 284 * operand. 285 */ 286 #define mtdcr(reg, val) \ 287 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val)) 288 289 #define mfdcr(reg) \ 290 ({ \ 291 uint32_t __val; \ 292 \ 293 __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \ 294 __val; \ 295 }) 296 #endif /* PPC_IBM4XX || PPC_IBM403 */ 297 298 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 299 #define CLKF_PC(frame) ((frame)->srr0) 300 #define CLKF_INTR(frame) ((frame)->depth > 0) 301 302 #define LWP_PC(l) (trapframe(l)->srr0) 303 304 #define cpu_swapin(p) 305 #define cpu_swapout(p) 306 #define cpu_proc_fork(p1, p2) 307 #define cpu_idle() (curcpu()->ci_idlespin()) 308 #define cpu_lwp_free2(l) 309 310 extern int powersave; 311 extern int cpu_timebase; 312 extern int cpu_printfataltraps; 313 extern char cpu_model[]; 314 315 struct cpu_info *cpu_attach_common(struct device *, int); 316 void cpu_setup(struct device *, struct cpu_info *); 317 void cpu_identify(char *, size_t); 318 void delay (unsigned int); 319 void cpu_probe_cache(void); 320 void dcache_flush_page(vaddr_t); 321 void icache_flush_page(vaddr_t); 322 void dcache_flush(vaddr_t, vsize_t); 323 void icache_flush(vaddr_t, vsize_t); 324 void *mapiodev(paddr_t, psize_t); 325 void unmapiodev(vaddr_t, vsize_t); 326 327 #ifdef MULTIPROCESSOR 328 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 329 void md_presync_timebase(volatile struct cpu_hatch_data *); 330 void md_start_timebase(volatile struct cpu_hatch_data *); 331 void md_sync_timebase(volatile struct cpu_hatch_data *); 332 void md_setup_interrupts(void); 333 int cpu_spinup(struct device *, struct cpu_info *); 334 void cpu_hatch(void); 335 void cpu_spinup_trampoline(void); 336 #endif 337 338 #define DELAY(n) delay(n) 339 340 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1) 341 #define cpu_did_resched() ((void)(curcpu()->ci_want_resched = 0)) 342 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1) 343 #define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */ 344 345 #if defined(PPC_OEA) || defined(PPC_OEA64) || defined (PPC_OEA64_BRIDGE) 346 void oea_init(void (*)(void)); 347 void oea_startup(const char *); 348 void oea_dumpsys(void); 349 void oea_install_extint(void (*)(void)); 350 paddr_t kvtop(void *); 351 void softnet(int); 352 353 extern paddr_t msgbuf_paddr; 354 extern int cpu_altivec; 355 #endif 356 357 #endif /* _KERNEL */ 358 359 #if defined(_KERNEL) || defined(_STANDALONE) 360 #if !defined(CACHELINESIZE) 361 #ifdef PPC_IBM403 362 #define CACHELINESIZE 16 363 #else 364 #if defined (PPC_OEA64_BRIDGE) 365 #define CACHELINESIZE 128 366 #else 367 #define CACHELINESIZE 32 368 #endif /* PPC_OEA64_BRIDGE */ 369 #endif 370 #endif 371 #endif 372 373 void __syncicache(void *, size_t); 374 375 /* 376 * CTL_MACHDEP definitions. 377 */ 378 #define CPU_CACHELINE 1 379 #define CPU_TIMEBASE 2 380 #define CPU_CPUTEMP 3 381 #define CPU_PRINTFATALTRAPS 4 382 #define CPU_CACHEINFO 5 383 #define CPU_ALTIVEC 6 384 #define CPU_MODEL 7 385 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 386 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 387 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 388 #define CPU_MAXID 11 /* number of valid machdep ids */ 389 390 #define CTL_MACHDEP_NAMES { \ 391 { 0, 0 }, \ 392 { "cachelinesize", CTLTYPE_INT }, \ 393 { "timebase", CTLTYPE_INT }, \ 394 { "cputempature", CTLTYPE_INT }, \ 395 { "printfataltraps", CTLTYPE_INT }, \ 396 { "cacheinfo", CTLTYPE_STRUCT }, \ 397 { "altivec", CTLTYPE_INT }, \ 398 { "model", CTLTYPE_STRING }, \ 399 { "powersave", CTLTYPE_INT }, \ 400 } 401 402 #endif /* _POWERPC_CPU_H_ */ 403
Indexes created Sun Sep 28 07:09:56 GMT 2025