cpu.h revision 1.62
1 /* $NetBSD: cpu.h,v 1.62 2008/02/05 18:52:55 garbled Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 int ci_cpuid; 69 70 volatile int ci_astpending; 71 int ci_want_resched; 72 volatile u_long ci_lasttb; 73 volatile int ci_tickspending; 74 volatile int ci_cpl; 75 volatile int ci_iactive; 76 volatile int ci_idepth; 77 volatile int ci_ipending; 78 int ci_intrdepth; 79 int ci_mtx_oldspl; 80 int ci_mtx_count; 81 char *ci_intstk; 82 #define CPUSAVE_LEN 8 83 register_t ci_tempsave[CPUSAVE_LEN]; 84 register_t ci_ddbsave[CPUSAVE_LEN]; 85 register_t ci_ipkdbsave[CPUSAVE_LEN]; 86 #define CPUSAVE_R28 0 /* where r28 gets saved */ 87 #define CPUSAVE_R29 1 /* where r29 gets saved */ 88 #define CPUSAVE_R30 2 /* where r30 gets saved */ 89 #define CPUSAVE_R31 3 /* where r31 gets saved */ 90 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 91 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 92 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 93 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 94 #define DISISAVE_LEN 4 95 register_t ci_disisave[DISISAVE_LEN]; 96 struct cache_info ci_ci; 97 void *ci_sysmon_cookie; 98 void (*ci_idlespin)(void); 99 uint32_t ci_khz; 100 struct evcnt ci_ev_clock; /* clock intrs */ 101 struct evcnt ci_ev_statclock; /* stat clock */ 102 struct evcnt ci_ev_softclock; /* softclock intrs */ 103 struct evcnt ci_ev_softnet; /* softnet intrs */ 104 struct evcnt ci_ev_softserial; /* softserial intrs */ 105 struct evcnt ci_ev_traps; /* calls to trap() */ 106 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 107 struct evcnt ci_ev_udsi; /* user DSI traps */ 108 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 109 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 110 struct evcnt ci_ev_isi; /* user ISI traps */ 111 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 112 struct evcnt ci_ev_pgm; /* user PGM traps */ 113 struct evcnt ci_ev_fpu; /* FPU traps */ 114 struct evcnt ci_ev_fpusw; /* FPU context switch */ 115 struct evcnt ci_ev_ali; /* Alignment traps */ 116 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 117 struct evcnt ci_ev_scalls; /* system call traps */ 118 struct evcnt ci_ev_vec; /* Altivec traps */ 119 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 120 struct evcnt ci_ev_umchk; /* user MCHK events */ 121 struct evcnt ci_ev_ipi; /* IPIs received */ 122 }; 123 124 #ifdef MULTIPROCESSOR 125 126 struct cpu_hatch_data { 127 struct device *self; 128 struct cpu_info *ci; 129 int running; 130 int pir; 131 int hid0; 132 int sdr1; 133 int sr[16]; 134 int batu[4], batl[4]; 135 int tbu, tbl; 136 }; 137 138 static __inline int 139 cpu_number(void) 140 { 141 int pir; 142 143 __asm ("mfspr %0,1023" : "=r"(pir)); 144 return pir; 145 } 146 147 void cpu_boot_secondary_processors(void); 148 149 150 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 151 #define CPU_INFO_ITERATOR int 152 #define CPU_INFO_FOREACH(cii, ci) \ 153 cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++ 154 155 #else 156 157 #define cpu_number() 0 158 159 #define CPU_INFO_ITERATOR int 160 #define CPU_INFO_FOREACH(cii, ci) \ 161 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 162 163 #endif /* MULTIPROCESSOR */ 164 165 extern struct cpu_info cpu_info[]; 166 167 static __inline struct cpu_info * 168 curcpu(void) 169 { 170 struct cpu_info *ci; 171 172 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 173 return ci; 174 } 175 176 #define curlwp (curcpu()->ci_curlwp) 177 #define curpcb (curcpu()->ci_curpcb) 178 #define curpm (curcpu()->ci_curpm) 179 180 static __inline register_t 181 mfmsr(void) 182 { 183 register_t msr; 184 185 __asm volatile ("mfmsr %0" : "=r"(msr)); 186 return msr; 187 } 188 189 static __inline void 190 mtmsr(register_t msr) 191 { 192 193 __asm volatile ("mtmsr %0" : : "r"(msr)); 194 } 195 196 static __inline uint32_t 197 mftbl(void) 198 { 199 uint32_t tbl; 200 201 __asm volatile ( 202 #ifdef PPC_IBM403 203 " mftblo %0 \n" 204 #else 205 " mftbl %0 \n" 206 #endif 207 : "=r" (tbl)); 208 209 return tbl; 210 } 211 212 static __inline uint64_t 213 mftb(void) 214 { 215 uint64_t tb; 216 217 #ifdef _LP64 218 __asm volatile ("mftb %0" : "=r"(tb)); 219 #else 220 int tmp; 221 222 __asm volatile ( 223 #ifdef PPC_IBM403 224 "1: mftbhi %0 \n" 225 " mftblo %0+1 \n" 226 " mftbhi %1 \n" 227 #else 228 "1: mftbu %0 \n" 229 " mftb %0+1 \n" 230 " mftbu %1 \n" 231 #endif 232 " cmplw %0,%1 \n" 233 " bne- 1b \n" 234 : "=r" (tb), "=r"(tmp) :: "cr0"); 235 #endif 236 237 return tb; 238 } 239 240 static __inline uint32_t 241 mfrtcl(void) 242 { 243 uint32_t rtcl; 244 245 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 246 return rtcl; 247 } 248 249 static __inline void 250 mfrtc(uint32_t *rtcp) 251 { 252 uint32_t tmp; 253 254 __asm volatile ( 255 "1: mfrtcu %0 \n" 256 " mfrtcl %1 \n" 257 " mfrtcu %2 \n" 258 " cmplw %0,%2 \n" 259 " bne- 1b" 260 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 261 } 262 263 static __inline uint32_t 264 mfpvr(void) 265 { 266 uint32_t pvr; 267 268 __asm volatile ("mfpvr %0" : "=r"(pvr)); 269 return (pvr); 270 } 271 272 static __inline int 273 cntlzw(uint32_t val) 274 { 275 int cnt; 276 277 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 278 return (cnt); 279 } 280 281 #if defined(PPC_IBM4XX) || defined(PPC_IBM403) 282 /* 283 * DCR (Device Control Register) access. These have to be 284 * macros because register address is encoded as immediate 285 * operand. 286 */ 287 #define mtdcr(reg, val) \ 288 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val)) 289 290 #define mfdcr(reg) \ 291 ({ \ 292 uint32_t __val; \ 293 \ 294 __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \ 295 __val; \ 296 }) 297 #endif /* PPC_IBM4XX || PPC_IBM403 */ 298 299 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 300 #define CLKF_PC(frame) ((frame)->srr0) 301 #define CLKF_INTR(frame) ((frame)->depth > 0) 302 303 #define LWP_PC(l) (trapframe(l)->srr0) 304 305 #define cpu_swapin(p) 306 #define cpu_swapout(p) 307 #define cpu_proc_fork(p1, p2) 308 #define cpu_idle() (curcpu()->ci_idlespin()) 309 #define cpu_lwp_free2(l) 310 311 extern int powersave; 312 extern int cpu_timebase; 313 extern int cpu_printfataltraps; 314 extern char cpu_model[]; 315 316 struct cpu_info *cpu_attach_common(struct device *, int); 317 void cpu_setup(struct device *, struct cpu_info *); 318 void cpu_identify(char *, size_t); 319 void delay (unsigned int); 320 void cpu_probe_cache(void); 321 void dcache_flush_page(vaddr_t); 322 void icache_flush_page(vaddr_t); 323 void dcache_flush(vaddr_t, vsize_t); 324 void icache_flush(vaddr_t, vsize_t); 325 void *mapiodev(paddr_t, psize_t); 326 void unmapiodev(vaddr_t, vsize_t); 327 328 #ifdef MULTIPROCESSOR 329 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 330 void md_presync_timebase(volatile struct cpu_hatch_data *); 331 void md_start_timebase(volatile struct cpu_hatch_data *); 332 void md_sync_timebase(volatile struct cpu_hatch_data *); 333 void md_setup_interrupts(void); 334 int cpu_spinup(struct device *, struct cpu_info *); 335 void cpu_hatch(void); 336 void cpu_spinup_trampoline(void); 337 #endif 338 339 #define DELAY(n) delay(n) 340 341 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1) 342 #define cpu_did_resched() ((void)(curcpu()->ci_want_resched = 0)) 343 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1) 344 #define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */ 345 346 #if !defined(PPC_IBM4XX) 347 void oea_init(void (*)(void)); 348 void oea_startup(const char *); 349 void oea_dumpsys(void); 350 void oea_install_extint(void (*)(void)); 351 paddr_t kvtop(void *); 352 void softnet(int); 353 354 extern paddr_t msgbuf_paddr; 355 extern int cpu_altivec; 356 #endif 357 358 #endif /* _KERNEL */ 359 360 /* XXX The below breaks unified pmap on ppc32 */ 361 362 #if defined(_KERNEL) || defined(_STANDALONE) 363 #if !defined(CACHELINESIZE) 364 #ifdef PPC_IBM403 365 #define CACHELINESIZE 16 366 #define MAXCACHELINESIZE 16 367 #else 368 #if defined (PPC_OEA64_BRIDGE) 369 #define CACHELINESIZE 128 370 #define MAXCACHELINESIZE 128 371 #else 372 #define CACHELINESIZE 32 373 #define MAXCACHELINESIZE 32 374 #endif /* PPC_OEA64_BRIDGE */ 375 #endif 376 #endif 377 #endif 378 379 void __syncicache(void *, size_t); 380 381 /* 382 * CTL_MACHDEP definitions. 383 */ 384 #define CPU_CACHELINE 1 385 #define CPU_TIMEBASE 2 386 #define CPU_CPUTEMP 3 387 #define CPU_PRINTFATALTRAPS 4 388 #define CPU_CACHEINFO 5 389 #define CPU_ALTIVEC 6 390 #define CPU_MODEL 7 391 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 392 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 393 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 394 #define CPU_MAXID 11 /* number of valid machdep ids */ 395 396 #define CTL_MACHDEP_NAMES { \ 397 { 0, 0 }, \ 398 { "cachelinesize", CTLTYPE_INT }, \ 399 { "timebase", CTLTYPE_INT }, \ 400 { "cputempature", CTLTYPE_INT }, \ 401 { "printfataltraps", CTLTYPE_INT }, \ 402 { "cacheinfo", CTLTYPE_STRUCT }, \ 403 { "altivec", CTLTYPE_INT }, \ 404 { "model", CTLTYPE_STRING }, \ 405 { "powersave", CTLTYPE_INT }, \ 406 } 407 408 #endif /* _POWERPC_CPU_H_ */ 409
Indexes created Mon Sep 22 05:09:51 GMT 2025