cpu.h revision 1.68.2.4
1 /* $NetBSD: cpu.h,v 1.68.2.4 2011/06/12 00:24:04 rmind Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #ifdef _KERNEL 53 #include <machine/frame.h> 54 #include <machine/psl.h> 55 #include <machine/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #endif 59 60 #include <sys/cpu_data.h> 61 62 struct cpu_info { 63 struct cpu_data ci_data; /* MI per-cpu data */ 64 #ifdef _KERNEL 65 device_t ci_dev; /* device of corresponding cpu */ 66 struct cpu_softc *ci_softc; /* private cpu info */ 67 struct lwp *ci_curlwp; /* current owner of the processor */ 68 69 struct pcb *ci_curpcb; 70 struct pmap *ci_curpm; 71 int ci_cpuid; /* from SPR_PIR */ 72 73 int ci_want_resched; 74 volatile uint64_t ci_lastintr; 75 volatile u_long ci_lasttb; 76 volatile int ci_tickspending; 77 volatile int ci_cpl; 78 volatile int ci_iactive; 79 volatile int ci_idepth; 80 #ifndef PPC_BOOKE 81 volatile imask_t ci_ipending; 82 #endif 83 volatile uint32_t ci_pending_ipis; 84 int ci_mtx_oldspl; 85 int ci_mtx_count; 86 #ifdef PPC_IBM4XX 87 char *ci_intstk; 88 #endif 89 #ifndef PPC_BOOKE 90 #define CPUSAVE_LEN 8 91 register_t ci_tempsave[CPUSAVE_LEN]; 92 register_t ci_ddbsave[CPUSAVE_LEN]; 93 register_t ci_ipkdbsave[CPUSAVE_LEN]; 94 #define CPUSAVE_R28 0 /* where r28 gets saved */ 95 #define CPUSAVE_R29 1 /* where r29 gets saved */ 96 #define CPUSAVE_R30 2 /* where r30 gets saved */ 97 #define CPUSAVE_R31 3 /* where r31 gets saved */ 98 #if defined(PPC_IBM4XX) 99 #define CPUSAVE_DEAR 4 /* where SPR_DEAR gets saved */ 100 #define CPUSAVE_ESR 5 /* where SPR_ESR gets saved */ 101 register_t ci_tlbmisssave[CPUSAVE_LEN]; 102 #else 103 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 104 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 105 #define DISISAVE_LEN 4 106 register_t ci_disisave[DISISAVE_LEN]; 107 #endif 108 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 109 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 110 #else /* PPC_BOOKE */ 111 #define CPUSAVE_LEN 128 112 register_t ci_savelifo[CPUSAVE_LEN]; 113 struct pmap_segtab *ci_pmap_segtabs[2]; 114 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 115 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 116 struct pmap_tlb_info *ci_tlb_info; 117 #endif /* PPC_BOOKE */ 118 struct cache_info ci_ci; 119 void *ci_sysmon_cookie; 120 void (*ci_idlespin)(void); 121 uint32_t ci_khz; 122 struct evcnt ci_ev_clock; /* clock intrs */ 123 struct evcnt ci_ev_statclock; /* stat clock */ 124 #ifndef PPC_BOOKE 125 struct evcnt ci_ev_softclock; /* softclock intrs */ 126 struct evcnt ci_ev_softnet; /* softnet intrs */ 127 struct evcnt ci_ev_softserial; /* softserial intrs */ 128 #endif 129 struct evcnt ci_ev_traps; /* calls to trap() */ 130 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 131 struct evcnt ci_ev_udsi; /* user DSI traps */ 132 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 133 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 134 struct evcnt ci_ev_isi; /* user ISI traps */ 135 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 136 struct evcnt ci_ev_pgm; /* user PGM traps */ 137 struct evcnt ci_ev_debug; /* user debug traps */ 138 struct evcnt ci_ev_fpu; /* FPU traps */ 139 struct evcnt ci_ev_fpusw; /* FPU context switch */ 140 struct evcnt ci_ev_ali; /* Alignment traps */ 141 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 142 struct evcnt ci_ev_scalls; /* system call traps */ 143 struct evcnt ci_ev_vec; /* Altivec traps */ 144 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 145 struct evcnt ci_ev_umchk; /* user MCHK events */ 146 struct evcnt ci_ev_ipi; /* IPIs received */ 147 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 148 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 149 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 150 #endif /* _KERNEL */ 151 }; 152 #endif /* _KERNEL || _KMEMUSER */ 153 154 #ifdef _KERNEL 155 156 #ifdef MULTIPROCESSOR 157 158 struct cpu_hatch_data { 159 struct device *self; 160 struct cpu_info *ci; 161 int running; 162 int pir; 163 int asr; 164 int hid0; 165 int sdr1; 166 int sr[16]; 167 int batu[4], batl[4]; 168 int tbu, tbl; 169 }; 170 171 static __inline int 172 cpu_number(void) 173 { 174 int pir; 175 176 __asm ("mfspr %0,1023" : "=r"(pir)); 177 return pir; 178 } 179 180 void cpu_boot_secondary_processors(void); 181 182 183 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 184 #define CPU_INFO_ITERATOR int 185 #define CPU_INFO_FOREACH(cii, ci) \ 186 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 187 188 #else 189 190 #define cpu_number() 0 191 192 #define CPU_INFO_ITERATOR int 193 #define CPU_INFO_FOREACH(cii, ci) \ 194 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 195 196 #endif /* MULTIPROCESSOR */ 197 198 extern struct cpu_info cpu_info[]; 199 200 static __inline struct cpu_info * curcpu(void) __pure; 201 static __inline struct cpu_info * 202 curcpu(void) 203 { 204 struct cpu_info *ci; 205 206 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 207 return ci; 208 } 209 210 register struct lwp *powerpc_curlwp __asm("r13"); 211 #define curlwp powerpc_curlwp 212 #define curpcb (curcpu()->ci_curpcb) 213 #define curpm (curcpu()->ci_curpm) 214 215 static __inline register_t 216 mfmsr(void) 217 { 218 register_t msr; 219 220 __asm volatile ("mfmsr %0" : "=r"(msr)); 221 return msr; 222 } 223 224 static __inline void 225 mtmsr(register_t msr) 226 { 227 //KASSERT(msr & PSL_CE); 228 //KASSERT(msr & PSL_DE); 229 __asm volatile ("mtmsr %0" : : "r"(msr)); 230 } 231 232 static __inline uint32_t 233 mftbl(void) 234 { 235 uint32_t tbl; 236 237 __asm volatile ( 238 #ifdef PPC_IBM403 239 " mftblo %[tbl]" "\n" 240 #elif defined(PPC_BOOKE) 241 " mfspr %[tbl],268" "\n" 242 #else 243 " mftbl %[tbl]" "\n" 244 #endif 245 : [tbl] "=r" (tbl)); 246 247 return tbl; 248 } 249 250 static __inline uint64_t 251 mftb(void) 252 { 253 uint64_t tb; 254 255 #ifdef _LP64 256 __asm volatile ("mftb %0" : "=r"(tb)); 257 #else 258 int tmp; 259 260 __asm volatile ( 261 #ifdef PPC_IBM403 262 "1: mftbhi %[tb]" "\n" 263 " mftblo %L[tb]" "\n" 264 " mftbhi %[tmp]" "\n" 265 #elif defined(PPC_BOOKE) 266 "1: mfspr %[tb],269" "\n" 267 " mfspr %L[tb],268" "\n" 268 " mfspr %[tmp],269" "\n" 269 #else 270 "1: mftbu %[tb]" "\n" 271 " mftb %L[tb]" "\n" 272 " mftbu %[tmp]" "\n" 273 #endif 274 " cmplw %[tb],%[tmp]" "\n" 275 " bne- 1b" "\n" 276 : [tb] "=r" (tb), [tmp] "=r"(tmp) 277 :: "cr0"); 278 #endif 279 280 return tb; 281 } 282 283 static __inline uint32_t 284 mfrtcl(void) 285 { 286 uint32_t rtcl; 287 288 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 289 return rtcl; 290 } 291 292 static __inline void 293 mfrtc(uint32_t *rtcp) 294 { 295 uint32_t tmp; 296 297 __asm volatile ( 298 "1: mfrtcu %[rtcu]" "\n" 299 " mfrtcl %[rtcl]" "\n" 300 " mfrtcu %[tmp]" "\n" 301 " cmplw %[rtcu],%[tmp]" "\n" 302 " bne- 1b" 303 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 304 :: "cr0"); 305 } 306 307 static __inline uint32_t 308 mfpvr(void) 309 { 310 uint32_t pvr; 311 312 __asm volatile ("mfpvr %0" : "=r"(pvr)); 313 return (pvr); 314 } 315 316 static __inline int 317 cntlzw(uint32_t val) 318 { 319 int cnt; 320 321 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 322 return (cnt); 323 } 324 325 /* 326 * functions to access the G3's cache throttling register 327 * bits 1 - 9 specify additional waits on cache acess 328 * bit 0 enables cache throttling 329 */ 330 331 static __inline int 332 mfictc(void) 333 { 334 int reg; 335 336 __asm ("mfspr %0,1019" : "=r"(reg)); 337 return reg; 338 } 339 340 static __inline void 341 mtictc(uint32_t reg) 342 { 343 344 __asm ("mtspr 1019,%0" :: "r"(reg)); 345 } 346 347 #define CLKF_USERMODE(frame) (((frame)->cf_srr1 & PSL_PR) != 0) 348 #define CLKF_PC(frame) ((frame)->cf_srr0) 349 #define CLKF_INTR(frame) ((frame)->cf_idepth > 0) 350 351 #define LWP_PC(l) (trapframe(l)->tf_srr0) 352 353 #define cpu_proc_fork(p1, p2) 354 355 extern int powersave; 356 extern int cpu_timebase; 357 extern int cpu_printfataltraps; 358 extern char cpu_model[]; 359 360 void cpu_uarea_remap(struct lwp *); 361 struct cpu_info *cpu_attach_common(struct device *, int); 362 void cpu_setup(struct device *, struct cpu_info *); 363 void cpu_identify(char *, size_t); 364 int cpu_get_dfs(void); 365 void cpu_set_dfs(int); 366 void delay (unsigned int); 367 void cpu_probe_cache(void); 368 #ifndef PPC_BOOKE 369 void dcache_flush_page(vaddr_t); 370 void icache_flush_page(vaddr_t); 371 void dcache_flush(vaddr_t, vsize_t); 372 void icache_flush(vaddr_t, vsize_t); 373 #else 374 void dcache_wb_page(vaddr_t); 375 void dcache_wbinv_page(vaddr_t); 376 void dcache_inv_page(vaddr_t); 377 void dcache_zero_page(vaddr_t); 378 void icache_inv_page(vaddr_t); 379 void dcache_wb(vaddr_t, vsize_t); 380 void dcache_wbinv(vaddr_t, vsize_t); 381 void dcache_inv(vaddr_t, vsize_t); 382 void icache_inv(vaddr_t, vsize_t); 383 #endif 384 void *mapiodev(paddr_t, psize_t); 385 void unmapiodev(vaddr_t, vsize_t); 386 387 #ifdef MULTIPROCESSOR 388 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 389 void md_presync_timebase(volatile struct cpu_hatch_data *); 390 void md_start_timebase(volatile struct cpu_hatch_data *); 391 void md_sync_timebase(volatile struct cpu_hatch_data *); 392 void md_setup_interrupts(void); 393 int cpu_spinup(struct device *, struct cpu_info *); 394 register_t cpu_hatch(void); 395 void cpu_spinup_trampoline(void); 396 #endif 397 398 #define DELAY(n) delay(n) 399 400 void cpu_need_resched(struct cpu_info *, int); 401 void cpu_signotify(struct lwp *); 402 void cpu_need_proftick(struct lwp *); 403 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 404 405 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) 406 void oea_init(void (*)(void)); 407 void oea_startup(const char *); 408 void oea_dumpsys(void); 409 void oea_install_extint(void (*)(void)); 410 paddr_t kvtop(void *); 411 void softnet(int); 412 413 extern paddr_t msgbuf_paddr; 414 extern int cpu_altivec; 415 #endif 416 417 #endif /* _KERNEL */ 418 419 /* XXX The below breaks unified pmap on ppc32 */ 420 421 #if defined(_KERNEL) || defined(_STANDALONE) 422 #if !defined(CACHELINESIZE) 423 #ifdef PPC_IBM403 424 #define CACHELINESIZE 16 425 #define MAXCACHELINESIZE 16 426 #else 427 #if defined (PPC_OEA64_BRIDGE) 428 #define CACHELINESIZE 128 429 #define MAXCACHELINESIZE 128 430 #else 431 #define CACHELINESIZE 32 432 #define MAXCACHELINESIZE 32 433 #endif /* PPC_OEA64_BRIDGE */ 434 #endif 435 #endif 436 #endif 437 438 void __syncicache(void *, size_t); 439 440 /* 441 * CTL_MACHDEP definitions. 442 */ 443 #define CPU_CACHELINE 1 444 #define CPU_TIMEBASE 2 445 #define CPU_CPUTEMP 3 446 #define CPU_PRINTFATALTRAPS 4 447 #define CPU_CACHEINFO 5 448 #define CPU_ALTIVEC 6 449 #define CPU_MODEL 7 450 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 451 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 452 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 453 #define CPU_MAXID 11 /* number of valid machdep ids */ 454 455 #endif /* _POWERPC_CPU_H_ */ 456
Indexes created Sun Oct 19 02:09:48 GMT 2025