cpu.h revision 1.69
1 /* $NetBSD: cpu.h,v 1.69 2010/03/18 13:47:05 kiyohara Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #ifdef _KERNEL 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #include <machine/frame.h> 53 #include <machine/psl.h> 54 #include <machine/intr.h> 55 #include <sys/device.h> 56 57 #include <sys/cpu_data.h> 58 59 struct cpu_info { 60 struct cpu_data ci_data; /* MI per-cpu data */ 61 struct device *ci_dev; /* device of corresponding cpu */ 62 struct lwp *ci_curlwp; /* current owner of the processor */ 63 64 struct pcb *ci_curpcb; 65 struct pmap *ci_curpm; 66 struct lwp *ci_fpulwp; 67 struct lwp *ci_veclwp; 68 int ci_cpuid; 69 70 volatile int ci_astpending; 71 int ci_want_resched; 72 volatile u_long ci_lasttb; 73 volatile int ci_tickspending; 74 volatile int ci_cpl; 75 volatile int ci_iactive; 76 volatile int ci_idepth; 77 volatile int ci_ipending; 78 int ci_intrdepth; 79 int ci_mtx_oldspl; 80 int ci_mtx_count; 81 #ifndef PPC_BOOKE 82 char *ci_intstk; 83 #endif 84 #define CPUSAVE_LEN 8 85 register_t ci_tempsave[CPUSAVE_LEN]; 86 register_t ci_ddbsave[CPUSAVE_LEN]; 87 register_t ci_ipkdbsave[CPUSAVE_LEN]; 88 #ifndef PPC_BOOKE 89 #define CPUSAVE_R28 0 /* where r28 gets saved */ 90 #define CPUSAVE_R29 1 /* where r29 gets saved */ 91 #define CPUSAVE_R30 2 /* where r30 gets saved */ 92 #define CPUSAVE_R31 3 /* where r31 gets saved */ 93 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 94 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 95 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 96 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 97 #define DISISAVE_LEN 4 98 register_t ci_disisave[DISISAVE_LEN]; 99 #else 100 #define CPUSAVE_R26 0 /* where r26 gets saved */ 101 #define CPUSAVE_R27 1 /* where r27 gets saved */ 102 #define CPUSAVE_R28 2 /* where r28 gets saved */ 103 #define CPUSAVE_R29 3 /* where r29 gets saved */ 104 #define CPUSAVE_R30 4 /* where r30 gets saved */ 105 #define CPUSAVE_R31 5 /* where r31 gets saved */ 106 register_t ci_critsave[CPUSAVE_LEN]; 107 register_t ci_mchksave[CPUSAVE_LEN]; 108 struct pmap_segtab *ci_pmap_kern_segtab; 109 struct pmap_segtab *ci_pmap_user_segtab; 110 #endif 111 struct cache_info ci_ci; 112 void *ci_sysmon_cookie; 113 void (*ci_idlespin)(void); 114 uint32_t ci_khz; 115 struct evcnt ci_ev_clock; /* clock intrs */ 116 struct evcnt ci_ev_statclock; /* stat clock */ 117 struct evcnt ci_ev_softclock; /* softclock intrs */ 118 struct evcnt ci_ev_softnet; /* softnet intrs */ 119 struct evcnt ci_ev_softserial; /* softserial intrs */ 120 struct evcnt ci_ev_traps; /* calls to trap() */ 121 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 122 struct evcnt ci_ev_udsi; /* user DSI traps */ 123 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 124 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 125 struct evcnt ci_ev_isi; /* user ISI traps */ 126 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 127 struct evcnt ci_ev_pgm; /* user PGM traps */ 128 struct evcnt ci_ev_fpu; /* FPU traps */ 129 struct evcnt ci_ev_fpusw; /* FPU context switch */ 130 struct evcnt ci_ev_ali; /* Alignment traps */ 131 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 132 struct evcnt ci_ev_scalls; /* system call traps */ 133 struct evcnt ci_ev_vec; /* Altivec traps */ 134 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 135 struct evcnt ci_ev_umchk; /* user MCHK events */ 136 struct evcnt ci_ev_ipi; /* IPIs received */ 137 }; 138 139 #ifdef MULTIPROCESSOR 140 141 struct cpu_hatch_data { 142 struct device *self; 143 struct cpu_info *ci; 144 int running; 145 int pir; 146 int asr; 147 int hid0; 148 int sdr1; 149 int sr[16]; 150 int batu[4], batl[4]; 151 int tbu, tbl; 152 }; 153 154 static __inline int 155 cpu_number(void) 156 { 157 int pir; 158 159 __asm ("mfspr %0,1023" : "=r"(pir)); 160 return pir; 161 } 162 163 void cpu_boot_secondary_processors(void); 164 165 166 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 167 #define CPU_INFO_ITERATOR int 168 #define CPU_INFO_FOREACH(cii, ci) \ 169 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 170 171 #else 172 173 #define cpu_number() 0 174 175 #define CPU_INFO_ITERATOR int 176 #define CPU_INFO_FOREACH(cii, ci) \ 177 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 178 179 #endif /* MULTIPROCESSOR */ 180 181 extern struct cpu_info cpu_info[]; 182 183 static __inline struct cpu_info * 184 curcpu(void) 185 { 186 struct cpu_info *ci; 187 188 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 189 return ci; 190 } 191 192 #define curlwp (curcpu()->ci_curlwp) 193 #define curpcb (curcpu()->ci_curpcb) 194 #define curpm (curcpu()->ci_curpm) 195 196 static __inline register_t 197 mfmsr(void) 198 { 199 register_t msr; 200 201 __asm volatile ("mfmsr %0" : "=r"(msr)); 202 return msr; 203 } 204 205 static __inline void 206 mtmsr(register_t msr) 207 { 208 209 __asm volatile ("mtmsr %0" : : "r"(msr)); 210 } 211 212 static __inline uint32_t 213 mftbl(void) 214 { 215 uint32_t tbl; 216 217 __asm volatile ( 218 #ifdef PPC_IBM403 219 " mftblo %0 \n" 220 #else 221 " mftbl %0 \n" 222 #endif 223 : "=r" (tbl)); 224 225 return tbl; 226 } 227 228 static __inline uint64_t 229 mftb(void) 230 { 231 uint64_t tb; 232 233 #ifdef _LP64 234 __asm volatile ("mftb %0" : "=r"(tb)); 235 #else 236 int tmp; 237 238 __asm volatile ( 239 #ifdef PPC_IBM403 240 "1: mftbhi %0 \n" 241 " mftblo %0+1 \n" 242 " mftbhi %1 \n" 243 #else 244 "1: mftbu %0 \n" 245 " mftb %0+1 \n" 246 " mftbu %1 \n" 247 #endif 248 " cmplw %0,%1 \n" 249 " bne- 1b \n" 250 : "=r" (tb), "=r"(tmp) :: "cr0"); 251 #endif 252 253 return tb; 254 } 255 256 static __inline uint32_t 257 mfrtcl(void) 258 { 259 uint32_t rtcl; 260 261 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 262 return rtcl; 263 } 264 265 static __inline void 266 mfrtc(uint32_t *rtcp) 267 { 268 uint32_t tmp; 269 270 __asm volatile ( 271 "1: mfrtcu %0 \n" 272 " mfrtcl %1 \n" 273 " mfrtcu %2 \n" 274 " cmplw %0,%2 \n" 275 " bne- 1b" 276 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 277 } 278 279 static __inline uint32_t 280 mfpvr(void) 281 { 282 uint32_t pvr; 283 284 __asm volatile ("mfpvr %0" : "=r"(pvr)); 285 return (pvr); 286 } 287 288 static __inline int 289 cntlzw(uint32_t val) 290 { 291 int cnt; 292 293 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 294 return (cnt); 295 } 296 297 #if defined(PPC_IBM4XX) || defined(PPC_IBM403) 298 /* 299 * DCR (Device Control Register) access. These have to be 300 * macros because register address is encoded as immediate 301 * operand. 302 */ 303 #define mtdcr(reg, val) \ 304 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val)) 305 306 #define mfdcr(reg) \ 307 ({ \ 308 uint32_t __val; \ 309 \ 310 __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \ 311 __val; \ 312 }) 313 314 #define mtcpr(reg, val) \ 315 do { \ 316 mtdcr(DCR_CPR0_CFGADDR, reg); \ 317 mtdcr(DCR_CPR0_CFGDATA, val); \ 318 } while (0/*CONSTCOND*/) 319 320 #define mfcpr(reg) \ 321 ({ \ 322 mtdcr(DCR_CPR0_CFGADDR, reg); \ 323 mfdcr(DCR_CPR0_CFGDATA); \ 324 }) 325 326 #define mtsdr(reg, val) \ 327 do { \ 328 mtdcr(DCR_SDR0_CFGADDR, reg); \ 329 mtdcr(DCR_SDR0_CFGDATA, val); \ 330 } while (0/*CONSTCOND*/) 331 332 #define mfsdr(reg) \ 333 ({ \ 334 mtdcr(DCR_SDR0_CFGADDR, reg); \ 335 mfdcr(DCR_SDR0_CFGDATA); \ 336 }) 337 #endif /* PPC_IBM4XX || PPC_IBM403 */ 338 339 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 340 #define CLKF_PC(frame) ((frame)->srr0) 341 #define CLKF_INTR(frame) ((frame)->depth > 0) 342 343 #define LWP_PC(l) (trapframe(l)->srr0) 344 345 #define cpu_proc_fork(p1, p2) 346 #define cpu_idle() (curcpu()->ci_idlespin()) 347 348 extern int powersave; 349 extern int cpu_timebase; 350 extern int cpu_printfataltraps; 351 extern char cpu_model[]; 352 353 struct cpu_info *cpu_attach_common(struct device *, int); 354 void cpu_setup(struct device *, struct cpu_info *); 355 void cpu_identify(char *, size_t); 356 void delay (unsigned int); 357 void cpu_probe_cache(void); 358 void dcache_flush_page(vaddr_t); 359 void icache_flush_page(vaddr_t); 360 void dcache_flush(vaddr_t, vsize_t); 361 void icache_flush(vaddr_t, vsize_t); 362 void *mapiodev(paddr_t, psize_t); 363 void unmapiodev(vaddr_t, vsize_t); 364 365 #ifdef MULTIPROCESSOR 366 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 367 void md_presync_timebase(volatile struct cpu_hatch_data *); 368 void md_start_timebase(volatile struct cpu_hatch_data *); 369 void md_sync_timebase(volatile struct cpu_hatch_data *); 370 void md_setup_interrupts(void); 371 int cpu_spinup(struct device *, struct cpu_info *); 372 register_t cpu_hatch(void); 373 void cpu_spinup_trampoline(void); 374 #endif 375 376 #define DELAY(n) delay(n) 377 378 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1) 379 #define cpu_did_resched(l) ((void)(curcpu()->ci_want_resched = 0)) 380 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1) 381 #define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */ 382 383 #if !defined(PPC_IBM4XX) 384 void oea_init(void (*)(void)); 385 void oea_startup(const char *); 386 void oea_dumpsys(void); 387 void oea_install_extint(void (*)(void)); 388 paddr_t kvtop(void *); 389 void softnet(int); 390 391 extern paddr_t msgbuf_paddr; 392 extern int cpu_altivec; 393 #endif 394 395 #endif /* _KERNEL */ 396 397 /* XXX The below breaks unified pmap on ppc32 */ 398 399 #if defined(_KERNEL) || defined(_STANDALONE) 400 #if !defined(CACHELINESIZE) 401 #ifdef PPC_IBM403 402 #define CACHELINESIZE 16 403 #define MAXCACHELINESIZE 16 404 #else 405 #if defined (PPC_OEA64_BRIDGE) 406 #define CACHELINESIZE 128 407 #define MAXCACHELINESIZE 128 408 #else 409 #define CACHELINESIZE 32 410 #define MAXCACHELINESIZE 32 411 #endif /* PPC_OEA64_BRIDGE */ 412 #endif 413 #endif 414 #endif 415 416 void __syncicache(void *, size_t); 417 418 /* 419 * CTL_MACHDEP definitions. 420 */ 421 #define CPU_CACHELINE 1 422 #define CPU_TIMEBASE 2 423 #define CPU_CPUTEMP 3 424 #define CPU_PRINTFATALTRAPS 4 425 #define CPU_CACHEINFO 5 426 #define CPU_ALTIVEC 6 427 #define CPU_MODEL 7 428 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 429 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 430 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 431 #define CPU_MAXID 11 /* number of valid machdep ids */ 432 433 #endif /* _POWERPC_CPU_H_ */ 434
Indexes created Thu Sep 25 06:09:39 GMT 2025