cpu.h revision 1.73
1 /* $NetBSD: cpu.h,v 1.73 2010/12/21 20:39:53 phx Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #ifdef _KERNEL 53 #include <machine/frame.h> 54 #include <machine/psl.h> 55 #include <machine/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #endif 59 60 #include <sys/cpu_data.h> 61 62 struct cpu_info { 63 struct cpu_data ci_data; /* MI per-cpu data */ 64 #ifdef _KERNEL 65 struct device *ci_dev; /* device of corresponding cpu */ 66 struct lwp *ci_curlwp; /* current owner of the processor */ 67 68 struct pcb *ci_curpcb; 69 struct pmap *ci_curpm; 70 struct lwp *ci_fpulwp; 71 struct lwp *ci_veclwp; 72 int ci_cpuid; 73 74 volatile int ci_astpending; 75 int ci_want_resched; 76 volatile u_long ci_lasttb; 77 volatile int ci_tickspending; 78 volatile int ci_cpl; 79 volatile int ci_iactive; 80 volatile int ci_idepth; 81 volatile imask_t ci_ipending; 82 int ci_intrdepth; 83 int ci_mtx_oldspl; 84 int ci_mtx_count; 85 #ifndef PPC_BOOKE 86 char *ci_intstk; 87 #endif 88 #define CPUSAVE_LEN 8 89 register_t ci_tempsave[CPUSAVE_LEN]; 90 register_t ci_ddbsave[CPUSAVE_LEN]; 91 register_t ci_ipkdbsave[CPUSAVE_LEN]; 92 #ifndef PPC_BOOKE 93 #define CPUSAVE_R28 0 /* where r28 gets saved */ 94 #define CPUSAVE_R29 1 /* where r29 gets saved */ 95 #define CPUSAVE_R30 2 /* where r30 gets saved */ 96 #define CPUSAVE_R31 3 /* where r31 gets saved */ 97 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 98 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 99 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 100 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 101 #define DISISAVE_LEN 4 102 register_t ci_disisave[DISISAVE_LEN]; 103 #else 104 #define CPUSAVE_R26 0 /* where r26 gets saved */ 105 #define CPUSAVE_R27 1 /* where r27 gets saved */ 106 #define CPUSAVE_R28 2 /* where r28 gets saved */ 107 #define CPUSAVE_R29 3 /* where r29 gets saved */ 108 #define CPUSAVE_R30 4 /* where r30 gets saved */ 109 #define CPUSAVE_R31 5 /* where r31 gets saved */ 110 register_t ci_critsave[CPUSAVE_LEN]; 111 register_t ci_mchksave[CPUSAVE_LEN]; 112 struct pmap_segtab *ci_pmap_kern_segtab; 113 struct pmap_segtab *ci_pmap_user_segtab; 114 #endif 115 struct cache_info ci_ci; 116 void *ci_sysmon_cookie; 117 void (*ci_idlespin)(void); 118 uint32_t ci_khz; 119 struct evcnt ci_ev_clock; /* clock intrs */ 120 struct evcnt ci_ev_statclock; /* stat clock */ 121 struct evcnt ci_ev_softclock; /* softclock intrs */ 122 struct evcnt ci_ev_softnet; /* softnet intrs */ 123 struct evcnt ci_ev_softserial; /* softserial intrs */ 124 struct evcnt ci_ev_traps; /* calls to trap() */ 125 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 126 struct evcnt ci_ev_udsi; /* user DSI traps */ 127 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 128 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 129 struct evcnt ci_ev_isi; /* user ISI traps */ 130 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 131 struct evcnt ci_ev_pgm; /* user PGM traps */ 132 struct evcnt ci_ev_fpu; /* FPU traps */ 133 struct evcnt ci_ev_fpusw; /* FPU context switch */ 134 struct evcnt ci_ev_ali; /* Alignment traps */ 135 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 136 struct evcnt ci_ev_scalls; /* system call traps */ 137 struct evcnt ci_ev_vec; /* Altivec traps */ 138 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 139 struct evcnt ci_ev_umchk; /* user MCHK events */ 140 struct evcnt ci_ev_ipi; /* IPIs received */ 141 #endif /* _KERNEL */ 142 }; 143 #endif /* _KERNEL || _KMEMUSER */ 144 145 #ifdef _KERNEL 146 147 #ifdef MULTIPROCESSOR 148 149 struct cpu_hatch_data { 150 struct device *self; 151 struct cpu_info *ci; 152 int running; 153 int pir; 154 int asr; 155 int hid0; 156 int sdr1; 157 int sr[16]; 158 int batu[4], batl[4]; 159 int tbu, tbl; 160 }; 161 162 static __inline int 163 cpu_number(void) 164 { 165 int pir; 166 167 __asm ("mfspr %0,1023" : "=r"(pir)); 168 return pir; 169 } 170 171 void cpu_boot_secondary_processors(void); 172 173 174 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 175 #define CPU_INFO_ITERATOR int 176 #define CPU_INFO_FOREACH(cii, ci) \ 177 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 178 179 #else 180 181 #define cpu_number() 0 182 183 #define CPU_INFO_ITERATOR int 184 #define CPU_INFO_FOREACH(cii, ci) \ 185 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 186 187 #endif /* MULTIPROCESSOR */ 188 189 extern struct cpu_info cpu_info[]; 190 191 static __inline struct cpu_info * 192 curcpu(void) 193 { 194 struct cpu_info *ci; 195 196 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 197 return ci; 198 } 199 200 #define curlwp (curcpu()->ci_curlwp) 201 #define curpcb (curcpu()->ci_curpcb) 202 #define curpm (curcpu()->ci_curpm) 203 204 static __inline register_t 205 mfmsr(void) 206 { 207 register_t msr; 208 209 __asm volatile ("mfmsr %0" : "=r"(msr)); 210 return msr; 211 } 212 213 static __inline void 214 mtmsr(register_t msr) 215 { 216 217 __asm volatile ("mtmsr %0" : : "r"(msr)); 218 } 219 220 static __inline uint32_t 221 mftbl(void) 222 { 223 uint32_t tbl; 224 225 __asm volatile ( 226 #ifdef PPC_IBM403 227 " mftblo %0 \n" 228 #else 229 " mftbl %0 \n" 230 #endif 231 : "=r" (tbl)); 232 233 return tbl; 234 } 235 236 static __inline uint64_t 237 mftb(void) 238 { 239 uint64_t tb; 240 241 #ifdef _LP64 242 __asm volatile ("mftb %0" : "=r"(tb)); 243 #else 244 int tmp; 245 246 __asm volatile ( 247 #ifdef PPC_IBM403 248 "1: mftbhi %0 \n" 249 " mftblo %0+1 \n" 250 " mftbhi %1 \n" 251 #else 252 "1: mftbu %0 \n" 253 " mftb %0+1 \n" 254 " mftbu %1 \n" 255 #endif 256 " cmplw %0,%1 \n" 257 " bne- 1b \n" 258 : "=r" (tb), "=r"(tmp) :: "cr0"); 259 #endif 260 261 return tb; 262 } 263 264 static __inline uint32_t 265 mfrtcl(void) 266 { 267 uint32_t rtcl; 268 269 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 270 return rtcl; 271 } 272 273 static __inline void 274 mfrtc(uint32_t *rtcp) 275 { 276 uint32_t tmp; 277 278 __asm volatile ( 279 "1: mfrtcu %0 \n" 280 " mfrtcl %1 \n" 281 " mfrtcu %2 \n" 282 " cmplw %0,%2 \n" 283 " bne- 1b" 284 : "=r"(*rtcp), "=r"(*(rtcp + 1)), "=r"(tmp) :: "cr0"); 285 } 286 287 static __inline uint32_t 288 mfpvr(void) 289 { 290 uint32_t pvr; 291 292 __asm volatile ("mfpvr %0" : "=r"(pvr)); 293 return (pvr); 294 } 295 296 static __inline int 297 cntlzw(uint32_t val) 298 { 299 int cnt; 300 301 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 302 return (cnt); 303 } 304 305 #if defined(PPC_IBM4XX) || defined(PPC_IBM403) 306 /* 307 * DCR (Device Control Register) access. These have to be 308 * macros because register address is encoded as immediate 309 * operand. 310 */ 311 #define mtdcr(reg, val) \ 312 __asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val)) 313 314 #define mfdcr(reg) \ 315 ({ \ 316 uint32_t __val; \ 317 \ 318 __asm volatile("mfdcr %0,%1" : "=r"(__val) : "K"(reg)); \ 319 __val; \ 320 }) 321 322 #define mtcpr(reg, val) \ 323 do { \ 324 mtdcr(DCR_CPR0_CFGADDR, reg); \ 325 mtdcr(DCR_CPR0_CFGDATA, val); \ 326 } while (0/*CONSTCOND*/) 327 328 #define mfcpr(reg) \ 329 ({ \ 330 mtdcr(DCR_CPR0_CFGADDR, reg); \ 331 mfdcr(DCR_CPR0_CFGDATA); \ 332 }) 333 334 #define mtsdr(reg, val) \ 335 do { \ 336 mtdcr(DCR_SDR0_CFGADDR, reg); \ 337 mtdcr(DCR_SDR0_CFGDATA, val); \ 338 } while (0/*CONSTCOND*/) 339 340 #define mfsdr(reg) \ 341 ({ \ 342 mtdcr(DCR_SDR0_CFGADDR, reg); \ 343 mfdcr(DCR_SDR0_CFGDATA); \ 344 }) 345 #endif /* PPC_IBM4XX || PPC_IBM403 */ 346 347 #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) 348 #define CLKF_PC(frame) ((frame)->srr0) 349 #define CLKF_INTR(frame) ((frame)->depth > 0) 350 351 #define LWP_PC(l) (trapframe(l)->srr0) 352 353 #define cpu_proc_fork(p1, p2) 354 #define cpu_idle() (curcpu()->ci_idlespin()) 355 356 extern int powersave; 357 extern int cpu_timebase; 358 extern int cpu_printfataltraps; 359 extern char cpu_model[]; 360 361 struct cpu_info *cpu_attach_common(struct device *, int); 362 void cpu_setup(struct device *, struct cpu_info *); 363 void cpu_identify(char *, size_t); 364 int cpu_get_dfs(void); 365 void cpu_set_dfs(int); 366 void delay (unsigned int); 367 void cpu_probe_cache(void); 368 void dcache_flush_page(vaddr_t); 369 void icache_flush_page(vaddr_t); 370 void dcache_flush(vaddr_t, vsize_t); 371 void icache_flush(vaddr_t, vsize_t); 372 void *mapiodev(paddr_t, psize_t); 373 void unmapiodev(vaddr_t, vsize_t); 374 375 #ifdef MULTIPROCESSOR 376 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 377 void md_presync_timebase(volatile struct cpu_hatch_data *); 378 void md_start_timebase(volatile struct cpu_hatch_data *); 379 void md_sync_timebase(volatile struct cpu_hatch_data *); 380 void md_setup_interrupts(void); 381 int cpu_spinup(struct device *, struct cpu_info *); 382 register_t cpu_hatch(void); 383 void cpu_spinup_trampoline(void); 384 #endif 385 386 #define DELAY(n) delay(n) 387 388 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1) 389 #define cpu_did_resched(l) ((void)(curcpu()->ci_want_resched = 0)) 390 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1) 391 #define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */ 392 393 #if !defined(PPC_IBM4XX) 394 void oea_init(void (*)(void)); 395 void oea_startup(const char *); 396 void oea_dumpsys(void); 397 void oea_install_extint(void (*)(void)); 398 paddr_t kvtop(void *); 399 void softnet(int); 400 401 extern paddr_t msgbuf_paddr; 402 extern int cpu_altivec; 403 #endif 404 405 #endif /* _KERNEL */ 406 407 /* XXX The below breaks unified pmap on ppc32 */ 408 409 #if defined(_KERNEL) || defined(_STANDALONE) 410 #if !defined(CACHELINESIZE) 411 #ifdef PPC_IBM403 412 #define CACHELINESIZE 16 413 #define MAXCACHELINESIZE 16 414 #else 415 #if defined (PPC_OEA64_BRIDGE) 416 #define CACHELINESIZE 128 417 #define MAXCACHELINESIZE 128 418 #else 419 #define CACHELINESIZE 32 420 #define MAXCACHELINESIZE 32 421 #endif /* PPC_OEA64_BRIDGE */ 422 #endif 423 #endif 424 #endif 425 426 void __syncicache(void *, size_t); 427 428 /* 429 * CTL_MACHDEP definitions. 430 */ 431 #define CPU_CACHELINE 1 432 #define CPU_TIMEBASE 2 433 #define CPU_CPUTEMP 3 434 #define CPU_PRINTFATALTRAPS 4 435 #define CPU_CACHEINFO 5 436 #define CPU_ALTIVEC 6 437 #define CPU_MODEL 7 438 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 439 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 440 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 441 #define CPU_MAXID 11 /* number of valid machdep ids */ 442 443 #endif /* _POWERPC_CPU_H_ */ 444
Indexes created Wed Sep 24 02:09:48 GMT 2025