cpu.h revision 1.74
1 /* $NetBSD: cpu.h,v 1.74 2011/01/18 01:02:54 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #ifdef _KERNEL 53 #include <machine/frame.h> 54 #include <machine/psl.h> 55 #include <machine/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #endif 59 60 #include <sys/cpu_data.h> 61 62 struct cpu_info { 63 struct cpu_data ci_data; /* MI per-cpu data */ 64 #ifdef _KERNEL 65 device_t ci_dev; /* device of corresponding cpu */ 66 struct cpu_softc *ci_softc; /* private cpu info */ 67 struct lwp *ci_curlwp; /* current owner of the processor */ 68 69 struct pcb *ci_curpcb; 70 struct pmap *ci_curpm; 71 struct lwp * volatile ci_fpulwp; 72 struct lwp * volatile ci_veclwp; 73 int ci_cpuid; 74 75 volatile int ci_astpending; 76 int ci_want_resched; 77 volatile uint64_t ci_lastintr; 78 volatile u_long ci_lasttb; 79 volatile int ci_tickspending; 80 volatile int ci_cpl; 81 volatile int ci_iactive; 82 volatile int ci_idepth; 83 #ifndef PPC_BOOKE 84 volatile imask_t ci_ipending; 85 #endif 86 int ci_mtx_oldspl; 87 int ci_mtx_count; 88 #ifdef PPC_IBM4XX 89 char *ci_intstk; 90 #endif 91 #ifndef PPC_BOOKE 92 #define CPUSAVE_LEN 8 93 register_t ci_tempsave[CPUSAVE_LEN]; 94 register_t ci_ddbsave[CPUSAVE_LEN]; 95 register_t ci_ipkdbsave[CPUSAVE_LEN]; 96 #define CPUSAVE_R28 0 /* where r28 gets saved */ 97 #define CPUSAVE_R29 1 /* where r29 gets saved */ 98 #define CPUSAVE_R30 2 /* where r30 gets saved */ 99 #define CPUSAVE_R31 3 /* where r31 gets saved */ 100 #if defined(PPC_IBM4XX) 101 #define CPUSAVE_DEAR 4 /* where SPR_DEAR gets saved */ 102 #define CPUSAVE_ESR 5 /* where SPR_ESR gets saved */ 103 register_t ci_tlbmisssave[CPUSAVE_LEN]; 104 #else 105 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 106 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 107 #define DISISAVE_LEN 4 108 register_t ci_disisave[DISISAVE_LEN]; 109 #endif 110 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 111 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 112 #else /* PPC_BOOKE */ 113 #define CPUSAVE_LEN 128 114 register_t ci_savelifo[CPUSAVE_LEN]; 115 struct pmap_segtab *ci_pmap_segtabs[2]; 116 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 117 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 118 struct pmap_tlb_info *ci_tlb_info; 119 #endif /* PPC_BOOKE */ 120 struct cache_info ci_ci; 121 void *ci_sysmon_cookie; 122 void (*ci_idlespin)(void); 123 uint32_t ci_khz; 124 struct evcnt ci_ev_clock; /* clock intrs */ 125 struct evcnt ci_ev_statclock; /* stat clock */ 126 #ifndef PPC_BOOKE 127 struct evcnt ci_ev_softclock; /* softclock intrs */ 128 struct evcnt ci_ev_softnet; /* softnet intrs */ 129 struct evcnt ci_ev_softserial; /* softserial intrs */ 130 #endif 131 struct evcnt ci_ev_traps; /* calls to trap() */ 132 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 133 struct evcnt ci_ev_udsi; /* user DSI traps */ 134 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 135 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 136 struct evcnt ci_ev_isi; /* user ISI traps */ 137 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 138 struct evcnt ci_ev_pgm; /* user PGM traps */ 139 struct evcnt ci_ev_fpu; /* FPU traps */ 140 struct evcnt ci_ev_fpusw; /* FPU context switch */ 141 struct evcnt ci_ev_ali; /* Alignment traps */ 142 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 143 struct evcnt ci_ev_scalls; /* system call traps */ 144 struct evcnt ci_ev_vec; /* Altivec traps */ 145 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 146 struct evcnt ci_ev_umchk; /* user MCHK events */ 147 struct evcnt ci_ev_ipi; /* IPIs received */ 148 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 149 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 150 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 151 #endif /* _KERNEL */ 152 }; 153 #endif /* _KERNEL || _KMEMUSER */ 154 155 #ifdef _KERNEL 156 157 #ifdef MULTIPROCESSOR 158 159 struct cpu_hatch_data { 160 struct device *self; 161 struct cpu_info *ci; 162 int running; 163 int pir; 164 int asr; 165 int hid0; 166 int sdr1; 167 int sr[16]; 168 int batu[4], batl[4]; 169 int tbu, tbl; 170 }; 171 172 static __inline int 173 cpu_number(void) 174 { 175 int pir; 176 177 __asm ("mfspr %0,1023" : "=r"(pir)); 178 return pir; 179 } 180 181 void cpu_boot_secondary_processors(void); 182 183 184 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 185 #define CPU_INFO_ITERATOR int 186 #define CPU_INFO_FOREACH(cii, ci) \ 187 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 188 189 #else 190 191 #define cpu_number() 0 192 193 #define CPU_INFO_ITERATOR int 194 #define CPU_INFO_FOREACH(cii, ci) \ 195 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 196 197 #endif /* MULTIPROCESSOR */ 198 199 extern struct cpu_info cpu_info[]; 200 201 static __inline struct cpu_info * 202 curcpu(void) 203 { 204 struct cpu_info *ci; 205 206 __asm volatile ("mfsprg %0,0" : "=r"(ci)); 207 return ci; 208 } 209 210 #define curlwp (curcpu()->ci_curlwp) 211 #define curpcb (curcpu()->ci_curpcb) 212 #define curpm (curcpu()->ci_curpm) 213 214 static __inline register_t 215 mfmsr(void) 216 { 217 register_t msr; 218 219 __asm volatile ("mfmsr %0" : "=r"(msr)); 220 return msr; 221 } 222 223 static __inline void 224 mtmsr(register_t msr) 225 { 226 //KASSERT(msr & PSL_CE); 227 //KASSERT(msr & PSL_DE); 228 __asm volatile ("mtmsr %0" : : "r"(msr)); 229 } 230 231 static __inline uint32_t 232 mftbl(void) 233 { 234 uint32_t tbl; 235 236 __asm volatile ( 237 #ifdef PPC_IBM403 238 " mftblo %[tbl]" "\n" 239 #elif defined(PPC_BOOKE) 240 " mfspr %[tbl],268" "\n" 241 #else 242 " mftbl %[tbl]" "\n" 243 #endif 244 : [tbl] "=r" (tbl)); 245 246 return tbl; 247 } 248 249 static __inline uint64_t 250 mftb(void) 251 { 252 uint64_t tb; 253 254 #ifdef _LP64 255 __asm volatile ("mftb %0" : "=r"(tb)); 256 #else 257 int tmp; 258 259 __asm volatile ( 260 #ifdef PPC_IBM403 261 "1: mftbhi %[tb]" "\n" 262 " mftblo %L[tb]" "\n" 263 " mftbhi %[tmp]" "\n" 264 #elif defined(PPC_BOOKE) 265 "1: mfspr %[tb],269" "\n" 266 " mfspr %L[tb],268" "\n" 267 " mfspr %[tmp],269" "\n" 268 #else 269 "1: mftbu %[tb]" "\n" 270 " mftb %L[tb]" "\n" 271 " mftbu %[tmp]" "\n" 272 #endif 273 " cmplw %[tb],%[tmp]" "\n" 274 " bne- 1b" "\n" 275 : [tb] "=r" (tb), [tmp] "=r"(tmp) 276 :: "cr0"); 277 #endif 278 279 return tb; 280 } 281 282 static __inline uint32_t 283 mfrtcl(void) 284 { 285 uint32_t rtcl; 286 287 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 288 return rtcl; 289 } 290 291 static __inline void 292 mfrtc(uint32_t *rtcp) 293 { 294 uint32_t tmp; 295 296 __asm volatile ( 297 "1: mfrtcu %[rtcu]" "\n" 298 " mfrtcl %[rtcl]" "\n" 299 " mfrtcu %[tmp]" "\n" 300 " cmplw %[rtcu],%[tmp]" "\n" 301 " bne- 1b" 302 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 303 :: "cr0"); 304 } 305 306 static __inline uint32_t 307 mfpvr(void) 308 { 309 uint32_t pvr; 310 311 __asm volatile ("mfpvr %0" : "=r"(pvr)); 312 return (pvr); 313 } 314 315 static __inline int 316 cntlzw(uint32_t val) 317 { 318 int cnt; 319 320 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 321 return (cnt); 322 } 323 324 #define CLKF_USERMODE(frame) (((frame)->cf_srr1 & PSL_PR) != 0) 325 #define CLKF_PC(frame) ((frame)->cf_srr0) 326 #define CLKF_INTR(frame) ((frame)->cf_idepth >= 0) 327 328 #define LWP_PC(l) (trapframe(l)->tf_srr0) 329 330 #define cpu_proc_fork(p1, p2) 331 332 extern int powersave; 333 extern int cpu_timebase; 334 extern int cpu_printfataltraps; 335 extern char cpu_model[]; 336 337 void cpu_uarea_remap(struct lwp *); 338 struct cpu_info *cpu_attach_common(struct device *, int); 339 void cpu_setup(struct device *, struct cpu_info *); 340 void cpu_identify(char *, size_t); 341 int cpu_get_dfs(void); 342 void cpu_set_dfs(int); 343 void delay (unsigned int); 344 void cpu_probe_cache(void); 345 #ifndef PPC_BOOKE 346 void dcache_flush_page(vaddr_t); 347 void icache_flush_page(vaddr_t); 348 void dcache_flush(vaddr_t, vsize_t); 349 void icache_flush(vaddr_t, vsize_t); 350 #else 351 void dcache_wb_page(vaddr_t); 352 void dcache_wbinv_page(vaddr_t); 353 void dcache_inv_page(vaddr_t); 354 void dcache_zero_page(vaddr_t); 355 void icache_inv_page(vaddr_t); 356 void dcache_wb(vaddr_t, vsize_t); 357 void dcache_wbinv(vaddr_t, vsize_t); 358 void dcache_inv(vaddr_t, vsize_t); 359 void icache_inv(vaddr_t, vsize_t); 360 #endif 361 void *mapiodev(paddr_t, psize_t); 362 void unmapiodev(vaddr_t, vsize_t); 363 364 #ifdef MULTIPROCESSOR 365 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 366 void md_presync_timebase(volatile struct cpu_hatch_data *); 367 void md_start_timebase(volatile struct cpu_hatch_data *); 368 void md_sync_timebase(volatile struct cpu_hatch_data *); 369 void md_setup_interrupts(void); 370 int cpu_spinup(struct device *, struct cpu_info *); 371 register_t cpu_hatch(void); 372 void cpu_spinup_trampoline(void); 373 #endif 374 375 #define DELAY(n) delay(n) 376 377 #define cpu_need_resched(ci, v) (ci->ci_want_resched = ci->ci_astpending = 1) 378 #define cpu_did_resched(l) ((void)(curcpu()->ci_want_resched = 0)) 379 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, curcpu()->ci_astpending = 1) 380 #define cpu_signotify(l) (curcpu()->ci_astpending = 1) /* XXXSMP */ 381 382 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) 383 void oea_init(void (*)(void)); 384 void oea_startup(const char *); 385 void oea_dumpsys(void); 386 void oea_install_extint(void (*)(void)); 387 paddr_t kvtop(void *); 388 void softnet(int); 389 390 extern paddr_t msgbuf_paddr; 391 extern int cpu_altivec; 392 #endif 393 394 #endif /* _KERNEL */ 395 396 /* XXX The below breaks unified pmap on ppc32 */ 397 398 #if defined(_KERNEL) || defined(_STANDALONE) 399 #if !defined(CACHELINESIZE) 400 #ifdef PPC_IBM403 401 #define CACHELINESIZE 16 402 #define MAXCACHELINESIZE 16 403 #else 404 #if defined (PPC_OEA64_BRIDGE) 405 #define CACHELINESIZE 128 406 #define MAXCACHELINESIZE 128 407 #else 408 #define CACHELINESIZE 32 409 #define MAXCACHELINESIZE 32 410 #endif /* PPC_OEA64_BRIDGE */ 411 #endif 412 #endif 413 #endif 414 415 void __syncicache(void *, size_t); 416 417 /* 418 * CTL_MACHDEP definitions. 419 */ 420 #define CPU_CACHELINE 1 421 #define CPU_TIMEBASE 2 422 #define CPU_CPUTEMP 3 423 #define CPU_PRINTFATALTRAPS 4 424 #define CPU_CACHEINFO 5 425 #define CPU_ALTIVEC 6 426 #define CPU_MODEL 7 427 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 428 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 429 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 430 #define CPU_MAXID 11 /* number of valid machdep ids */ 431 432 #endif /* _POWERPC_CPU_H_ */ 433
Indexes created Wed Sep 24 05:09:52 GMT 2025