cpu.h revision 1.76.2.1
1 /* $NetBSD: cpu.h,v 1.76.2.1 2011/06/23 14:19:30 cherry Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_modular.h" 49 #include "opt_multiprocessor.h" 50 #include "opt_ppcarch.h" 51 #endif 52 53 #ifdef _KERNEL 54 #include <machine/intr.h> 55 #include <sys/device_if.h> 56 #include <sys/evcnt.h> 57 #endif 58 59 #include <sys/cpu_data.h> 60 61 struct cpu_info { 62 struct cpu_data ci_data; /* MI per-cpu data */ 63 #ifdef _KERNEL 64 device_t ci_dev; /* device of corresponding cpu */ 65 struct cpu_softc *ci_softc; /* private cpu info */ 66 struct lwp *ci_curlwp; /* current owner of the processor */ 67 68 struct pcb *ci_curpcb; 69 struct pmap *ci_curpm; 70 struct lwp *ci_softlwps[SOFTINT_COUNT]; 71 int ci_cpuid; /* from SPR_PIR */ 72 73 int ci_want_resched; 74 volatile uint64_t ci_lastintr; 75 volatile u_long ci_lasttb; 76 volatile int ci_tickspending; 77 volatile int ci_cpl; 78 volatile int ci_iactive; 79 volatile int ci_idepth; 80 union { 81 #if !defined(PPC_BOOKE) && !defined(_MODULE) 82 volatile imask_t un1_ipending; 83 #define ci_ipending ci_un1.un1_ipending 84 #endif 85 uint64_t un1_pad64; 86 } ci_un1; 87 volatile uint32_t ci_pending_ipis; 88 int ci_mtx_oldspl; 89 int ci_mtx_count; 90 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 91 char *ci_intstk; 92 #endif 93 #define CI_SAVETEMP (0*CPUSAVE_LEN) 94 #define CI_SAVEDDB (1*CPUSAVE_LEN) 95 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) 96 #define CI_SAVEMMU (3*CPUSAVE_LEN) 97 #define CI_SAVEMAX (4*CPUSAVE_LEN) 98 #define CPUSAVE_LEN 8 99 #if !defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 100 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 101 #else 102 #define CPUSAVE_SIZE 128 103 #endif 104 #define CPUSAVE_R28 0 /* where r28 gets saved */ 105 #define CPUSAVE_R29 1 /* where r29 gets saved */ 106 #define CPUSAVE_R30 2 /* where r30 gets saved */ 107 #define CPUSAVE_R31 3 /* where r31 gets saved */ 108 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 109 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 110 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 111 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 112 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 113 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 114 register_t ci_savearea[CPUSAVE_SIZE]; 115 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 116 uint32_t ci_pmap_asid_cur; 117 struct pmap_segtab *ci_pmap_segtabs[2]; 118 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 119 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 120 struct pmap_tlb_info *ci_tlb_info; 121 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 122 struct cache_info ci_ci; 123 void *ci_sysmon_cookie; 124 void (*ci_idlespin)(void); 125 uint32_t ci_khz; 126 struct evcnt ci_ev_clock; /* clock intrs */ 127 struct evcnt ci_ev_statclock; /* stat clock */ 128 struct evcnt ci_ev_traps; /* calls to trap() */ 129 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 130 struct evcnt ci_ev_udsi; /* user DSI traps */ 131 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 132 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 133 struct evcnt ci_ev_isi; /* user ISI traps */ 134 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 135 struct evcnt ci_ev_pgm; /* user PGM traps */ 136 struct evcnt ci_ev_debug; /* user debug traps */ 137 struct evcnt ci_ev_fpu; /* FPU traps */ 138 struct evcnt ci_ev_fpusw; /* FPU context switch */ 139 struct evcnt ci_ev_ali; /* Alignment traps */ 140 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 141 struct evcnt ci_ev_scalls; /* system call traps */ 142 struct evcnt ci_ev_vec; /* Altivec traps */ 143 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 144 struct evcnt ci_ev_umchk; /* user MCHK events */ 145 struct evcnt ci_ev_ipi; /* IPIs received */ 146 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 147 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 148 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 149 #endif /* _KERNEL */ 150 }; 151 #endif /* _KERNEL || _KMEMUSER */ 152 153 #ifdef _KERNEL 154 155 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 156 struct cpu_hatch_data { 157 device_t self; 158 struct cpu_info *ci; 159 int running; 160 int pir; 161 int asr; 162 int hid0; 163 int sdr1; 164 int sr[16]; 165 int batu[4], batl[4]; 166 int tbu, tbl; 167 }; 168 #endif /* MULTIPROCESSOR && !_MODULE */ 169 170 #if defined(MULTIPROCESSOR) || defined(_MODULE) 171 #define cpu_number() (curcpu()->ci_index + 0) 172 173 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 174 #define CPU_INFO_ITERATOR int 175 #define CPU_INFO_FOREACH(cii, ci) \ 176 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 177 178 #else 179 #define cpu_number() 0 180 181 #define CPU_IS_PRIMARY(ci) true 182 #define CPU_INFO_ITERATOR int 183 #define CPU_INFO_FOREACH(cii, ci) \ 184 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 185 186 #endif /* MULTIPROCESSOR || _MODULE */ 187 188 extern struct cpu_info cpu_info[]; 189 190 static __inline struct cpu_info * curcpu(void) __pure; 191 static __inline struct cpu_info * 192 curcpu(void) 193 { 194 struct cpu_info *ci; 195 196 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 197 return ci; 198 } 199 200 register struct lwp *powerpc_curlwp __asm("r13"); 201 #define curlwp powerpc_curlwp 202 #define curpcb (curcpu()->ci_curpcb) 203 #define curpm (curcpu()->ci_curpm) 204 205 static __inline register_t 206 mfmsr(void) 207 { 208 register_t msr; 209 210 __asm volatile ("mfmsr %0" : "=r"(msr)); 211 return msr; 212 } 213 214 static __inline void 215 mtmsr(register_t msr) 216 { 217 //KASSERT(msr & PSL_CE); 218 //KASSERT(msr & PSL_DE); 219 __asm volatile ("mtmsr %0" : : "r"(msr)); 220 } 221 222 #if !defined(_MODULE) 223 static __inline uint32_t 224 mftbl(void) 225 { 226 uint32_t tbl; 227 228 __asm volatile ( 229 #ifdef PPC_IBM403 230 " mftblo %[tbl]" "\n" 231 #elif defined(PPC_BOOKE) 232 " mfspr %[tbl],268" "\n" 233 #else 234 " mftbl %[tbl]" "\n" 235 #endif 236 : [tbl] "=r" (tbl)); 237 238 return tbl; 239 } 240 241 static __inline uint64_t 242 mftb(void) 243 { 244 uint64_t tb; 245 246 #ifdef _LP64 247 __asm volatile ("mftb %0" : "=r"(tb)); 248 #else 249 int tmp; 250 251 __asm volatile ( 252 #ifdef PPC_IBM403 253 "1: mftbhi %[tb]" "\n" 254 " mftblo %L[tb]" "\n" 255 " mftbhi %[tmp]" "\n" 256 #elif defined(PPC_BOOKE) 257 "1: mfspr %[tb],269" "\n" 258 " mfspr %L[tb],268" "\n" 259 " mfspr %[tmp],269" "\n" 260 #else 261 "1: mftbu %[tb]" "\n" 262 " mftb %L[tb]" "\n" 263 " mftbu %[tmp]" "\n" 264 #endif 265 " cmplw %[tb],%[tmp]" "\n" 266 " bne- 1b" "\n" 267 : [tb] "=r" (tb), [tmp] "=r"(tmp) 268 :: "cr0"); 269 #endif 270 271 return tb; 272 } 273 274 static __inline uint32_t 275 mfrtcl(void) 276 { 277 uint32_t rtcl; 278 279 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 280 return rtcl; 281 } 282 283 static __inline void 284 mfrtc(uint32_t *rtcp) 285 { 286 uint32_t tmp; 287 288 __asm volatile ( 289 "1: mfrtcu %[rtcu]" "\n" 290 " mfrtcl %[rtcl]" "\n" 291 " mfrtcu %[tmp]" "\n" 292 " cmplw %[rtcu],%[tmp]" "\n" 293 " bne- 1b" 294 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 295 :: "cr0"); 296 } 297 #endif /* !_MODULE */ 298 299 static __inline uint32_t 300 mfpvr(void) 301 { 302 uint32_t pvr; 303 304 __asm volatile ("mfpvr %0" : "=r"(pvr)); 305 return (pvr); 306 } 307 308 #ifdef _MODULE 309 extern const char __CPU_MAXNUM; 310 /* 311 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 312 * corresponding R_PPC_ADDR16_HI relocation. 313 */ 314 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 315 #endif /* _MODULE */ 316 317 #if !defined(_MODULE) 318 extern int powersave; 319 extern int cpu_timebase; 320 extern int cpu_printfataltraps; 321 extern char cpu_model[]; 322 323 struct cpu_info * 324 cpu_attach_common(device_t, int); 325 void cpu_setup(device_t, struct cpu_info *); 326 void cpu_identify(char *, size_t); 327 void cpu_probe_cache(void); 328 329 void dcache_wb_page(vaddr_t); 330 void dcache_wbinv_page(vaddr_t); 331 void dcache_inv_page(vaddr_t); 332 void dcache_zero_page(vaddr_t); 333 void icache_inv_page(vaddr_t); 334 void dcache_wb(vaddr_t, vsize_t); 335 void dcache_wbinv(vaddr_t, vsize_t); 336 void dcache_inv(vaddr_t, vsize_t); 337 void icache_inv(vaddr_t, vsize_t); 338 339 void * mapiodev(paddr_t, psize_t); 340 void unmapiodev(vaddr_t, vsize_t); 341 342 #ifdef MULTIPROCESSOR 343 int md_setup_trampoline(volatile struct cpu_hatch_data *, 344 struct cpu_info *); 345 void md_presync_timebase(volatile struct cpu_hatch_data *); 346 void md_start_timebase(volatile struct cpu_hatch_data *); 347 void md_sync_timebase(volatile struct cpu_hatch_data *); 348 void md_setup_interrupts(void); 349 int cpu_spinup(device_t, struct cpu_info *); 350 register_t 351 cpu_hatch(void); 352 void cpu_spinup_trampoline(void); 353 void cpu_boot_secondary_processors(void); 354 #endif /* MULTIPROCESSOR */ 355 #endif /* !_MODULE */ 356 357 #define cpu_proc_fork(p1, p2) 358 359 #define DELAY(n) delay(n) 360 void delay(unsigned int); 361 362 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 363 #define CLKF_PC(cf) cpu_clkf_pc(cf) 364 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 365 366 bool cpu_clkf_usermode(const struct clockframe *); 367 vaddr_t cpu_clkf_pc(const struct clockframe *); 368 bool cpu_clkf_intr(const struct clockframe *); 369 370 #define LWP_PC(l) cpu_lwp_pc(l) 371 372 vaddr_t cpu_lwp_pc(struct lwp *); 373 374 void cpu_ast(struct lwp *, struct cpu_info *); 375 void * cpu_uarea_alloc(bool); 376 bool cpu_uarea_free(void *); 377 void cpu_need_resched(struct cpu_info *, int); 378 void cpu_signotify(struct lwp *); 379 void cpu_need_proftick(struct lwp *); 380 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 381 382 void cpu_fixup_stubs(void); 383 384 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 385 int cpu_get_dfs(void); 386 void cpu_set_dfs(int); 387 388 void oea_init(void (*)(void)); 389 void oea_startup(const char *); 390 void oea_dumpsys(void); 391 void oea_install_extint(void (*)(void)); 392 paddr_t kvtop(void *); 393 394 extern paddr_t msgbuf_paddr; 395 extern int cpu_altivec; 396 #endif 397 398 #endif /* _KERNEL */ 399 400 /* XXX The below breaks unified pmap on ppc32 */ 401 402 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 403 && (defined(_KERNEL) || defined(_STANDALONE)) 404 #if defined(PPC_IBM403) 405 #define CACHELINESIZE 16 406 #define MAXCACHELINESIZE 16 407 #elif defined (PPC_OEA64_BRIDGE) 408 #define CACHELINESIZE 128 409 #define MAXCACHELINESIZE 128 410 #else 411 #define CACHELINESIZE 32 412 #define MAXCACHELINESIZE 32 413 #endif /* PPC_OEA64_BRIDGE */ 414 #endif 415 416 void __syncicache(void *, size_t); 417 418 /* 419 * CTL_MACHDEP definitions. 420 */ 421 #define CPU_CACHELINE 1 422 #define CPU_TIMEBASE 2 423 #define CPU_CPUTEMP 3 424 #define CPU_PRINTFATALTRAPS 4 425 #define CPU_CACHEINFO 5 426 #define CPU_ALTIVEC 6 427 #define CPU_MODEL 7 428 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 429 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 430 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 431 #define CPU_MAXID 11 /* number of valid machdep ids */ 432 433 #endif /* _POWERPC_CPU_H_ */ 434
Indexes created Thu Oct 23 22:10:10 GMT 2025