cpu.h revision 1.81
1 /* $NetBSD: cpu.h,v 1.81 2011/06/15 15:18:20 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_multiprocessor.h" 49 #include "opt_ppcarch.h" 50 #endif 51 52 #ifdef _KERNEL 53 #include <machine/frame.h> 54 #include <machine/psl.h> 55 #include <machine/intr.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #endif 59 60 #include <sys/cpu_data.h> 61 62 struct cpu_info { 63 struct cpu_data ci_data; /* MI per-cpu data */ 64 #ifdef _KERNEL 65 device_t ci_dev; /* device of corresponding cpu */ 66 struct cpu_softc *ci_softc; /* private cpu info */ 67 struct lwp *ci_curlwp; /* current owner of the processor */ 68 69 struct pcb *ci_curpcb; 70 struct pmap *ci_curpm; 71 struct lwp *ci_softlwps[SOFTINT_COUNT]; 72 int ci_cpuid; /* from SPR_PIR */ 73 74 int ci_want_resched; 75 volatile uint64_t ci_lastintr; 76 volatile u_long ci_lasttb; 77 volatile int ci_tickspending; 78 volatile int ci_cpl; 79 volatile int ci_iactive; 80 volatile int ci_idepth; 81 #ifndef PPC_BOOKE 82 volatile imask_t ci_ipending; 83 #endif 84 volatile uint32_t ci_pending_ipis; 85 int ci_mtx_oldspl; 86 int ci_mtx_count; 87 #ifdef PPC_IBM4XX 88 char *ci_intstk; 89 #endif 90 #ifndef PPC_BOOKE 91 #define CPUSAVE_LEN 8 92 register_t ci_tempsave[CPUSAVE_LEN]; 93 register_t ci_ddbsave[CPUSAVE_LEN]; 94 register_t ci_ipkdbsave[CPUSAVE_LEN]; 95 #define CPUSAVE_R28 0 /* where r28 gets saved */ 96 #define CPUSAVE_R29 1 /* where r29 gets saved */ 97 #define CPUSAVE_R30 2 /* where r30 gets saved */ 98 #define CPUSAVE_R31 3 /* where r31 gets saved */ 99 #if defined(PPC_IBM4XX) 100 #define CPUSAVE_DEAR 4 /* where SPR_DEAR gets saved */ 101 #define CPUSAVE_ESR 5 /* where SPR_ESR gets saved */ 102 register_t ci_tlbmisssave[CPUSAVE_LEN]; 103 #else 104 #define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */ 105 #define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */ 106 #define DISISAVE_LEN 4 107 register_t ci_disisave[DISISAVE_LEN]; 108 #endif 109 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 110 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 111 #else /* PPC_BOOKE */ 112 #define CPUSAVE_LEN 128 113 register_t ci_savelifo[CPUSAVE_LEN]; 114 struct pmap_segtab *ci_pmap_segtabs[2]; 115 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 116 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 117 struct pmap_tlb_info *ci_tlb_info; 118 #endif /* PPC_BOOKE */ 119 struct cache_info ci_ci; 120 void *ci_sysmon_cookie; 121 void (*ci_idlespin)(void); 122 uint32_t ci_khz; 123 struct evcnt ci_ev_clock; /* clock intrs */ 124 struct evcnt ci_ev_statclock; /* stat clock */ 125 #ifndef PPC_BOOKE 126 struct evcnt ci_ev_softclock; /* softclock intrs */ 127 struct evcnt ci_ev_softnet; /* softnet intrs */ 128 struct evcnt ci_ev_softserial; /* softserial intrs */ 129 #endif 130 struct evcnt ci_ev_traps; /* calls to trap() */ 131 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 132 struct evcnt ci_ev_udsi; /* user DSI traps */ 133 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 134 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 135 struct evcnt ci_ev_isi; /* user ISI traps */ 136 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 137 struct evcnt ci_ev_pgm; /* user PGM traps */ 138 struct evcnt ci_ev_debug; /* user debug traps */ 139 struct evcnt ci_ev_fpu; /* FPU traps */ 140 struct evcnt ci_ev_fpusw; /* FPU context switch */ 141 struct evcnt ci_ev_ali; /* Alignment traps */ 142 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 143 struct evcnt ci_ev_scalls; /* system call traps */ 144 struct evcnt ci_ev_vec; /* Altivec traps */ 145 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 146 struct evcnt ci_ev_umchk; /* user MCHK events */ 147 struct evcnt ci_ev_ipi; /* IPIs received */ 148 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 149 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 150 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 151 #endif /* _KERNEL */ 152 }; 153 #endif /* _KERNEL || _KMEMUSER */ 154 155 #ifdef _KERNEL 156 157 #ifdef MULTIPROCESSOR 158 159 struct cpu_hatch_data { 160 struct device *self; 161 struct cpu_info *ci; 162 int running; 163 int pir; 164 int asr; 165 int hid0; 166 int sdr1; 167 int sr[16]; 168 int batu[4], batl[4]; 169 int tbu, tbl; 170 }; 171 172 static __inline int 173 cpu_number(void) 174 { 175 int pir; 176 177 __asm ("mfspr %0,1023" : "=r"(pir)); 178 return pir; 179 } 180 181 void cpu_boot_secondary_processors(void); 182 183 184 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 185 #define CPU_INFO_ITERATOR int 186 #define CPU_INFO_FOREACH(cii, ci) \ 187 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 188 189 #else 190 191 #define cpu_number() 0 192 193 #define CPU_INFO_ITERATOR int 194 #define CPU_INFO_FOREACH(cii, ci) \ 195 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 196 197 #endif /* MULTIPROCESSOR */ 198 199 extern struct cpu_info cpu_info[]; 200 201 static __inline struct cpu_info * curcpu(void) __pure; 202 static __inline struct cpu_info * 203 curcpu(void) 204 { 205 struct cpu_info *ci; 206 207 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 208 return ci; 209 } 210 211 register struct lwp *powerpc_curlwp __asm("r13"); 212 #define curlwp powerpc_curlwp 213 #define curpcb (curcpu()->ci_curpcb) 214 #define curpm (curcpu()->ci_curpm) 215 216 static __inline register_t 217 mfmsr(void) 218 { 219 register_t msr; 220 221 __asm volatile ("mfmsr %0" : "=r"(msr)); 222 return msr; 223 } 224 225 static __inline void 226 mtmsr(register_t msr) 227 { 228 //KASSERT(msr & PSL_CE); 229 //KASSERT(msr & PSL_DE); 230 __asm volatile ("mtmsr %0" : : "r"(msr)); 231 } 232 233 static __inline uint32_t 234 mftbl(void) 235 { 236 uint32_t tbl; 237 238 __asm volatile ( 239 #ifdef PPC_IBM403 240 " mftblo %[tbl]" "\n" 241 #elif defined(PPC_BOOKE) 242 " mfspr %[tbl],268" "\n" 243 #else 244 " mftbl %[tbl]" "\n" 245 #endif 246 : [tbl] "=r" (tbl)); 247 248 return tbl; 249 } 250 251 static __inline uint64_t 252 mftb(void) 253 { 254 uint64_t tb; 255 256 #ifdef _LP64 257 __asm volatile ("mftb %0" : "=r"(tb)); 258 #else 259 int tmp; 260 261 __asm volatile ( 262 #ifdef PPC_IBM403 263 "1: mftbhi %[tb]" "\n" 264 " mftblo %L[tb]" "\n" 265 " mftbhi %[tmp]" "\n" 266 #elif defined(PPC_BOOKE) 267 "1: mfspr %[tb],269" "\n" 268 " mfspr %L[tb],268" "\n" 269 " mfspr %[tmp],269" "\n" 270 #else 271 "1: mftbu %[tb]" "\n" 272 " mftb %L[tb]" "\n" 273 " mftbu %[tmp]" "\n" 274 #endif 275 " cmplw %[tb],%[tmp]" "\n" 276 " bne- 1b" "\n" 277 : [tb] "=r" (tb), [tmp] "=r"(tmp) 278 :: "cr0"); 279 #endif 280 281 return tb; 282 } 283 284 static __inline uint32_t 285 mfrtcl(void) 286 { 287 uint32_t rtcl; 288 289 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 290 return rtcl; 291 } 292 293 static __inline void 294 mfrtc(uint32_t *rtcp) 295 { 296 uint32_t tmp; 297 298 __asm volatile ( 299 "1: mfrtcu %[rtcu]" "\n" 300 " mfrtcl %[rtcl]" "\n" 301 " mfrtcu %[tmp]" "\n" 302 " cmplw %[rtcu],%[tmp]" "\n" 303 " bne- 1b" 304 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 305 :: "cr0"); 306 } 307 308 static __inline uint32_t 309 mfpvr(void) 310 { 311 uint32_t pvr; 312 313 __asm volatile ("mfpvr %0" : "=r"(pvr)); 314 return (pvr); 315 } 316 317 static __inline int 318 cntlzw(uint32_t val) 319 { 320 int cnt; 321 322 __asm volatile ("cntlzw %0,%1" : "=r"(cnt) : "r"(val)); 323 return (cnt); 324 } 325 326 /* 327 * functions to access the G3's cache throttling register 328 * bits 1 - 9 specify additional waits on cache acess 329 * bit 0 enables cache throttling 330 */ 331 332 static __inline int 333 mfictc(void) 334 { 335 int reg; 336 337 __asm ("mfspr %0,1019" : "=r"(reg)); 338 return reg; 339 } 340 341 static __inline void 342 mtictc(uint32_t reg) 343 { 344 345 __asm ("mtspr 1019,%0" :: "r"(reg)); 346 } 347 348 #define CLKF_USERMODE(frame) (((frame)->cf_srr1 & PSL_PR) != 0) 349 #define CLKF_PC(frame) ((frame)->cf_srr0) 350 #define CLKF_INTR(frame) ((frame)->cf_idepth > 0) 351 352 #define LWP_PC(l) (trapframe(l)->tf_srr0) 353 354 #define cpu_proc_fork(p1, p2) 355 356 extern int powersave; 357 extern int cpu_timebase; 358 extern int cpu_printfataltraps; 359 extern char cpu_model[]; 360 361 struct cpu_info *cpu_attach_common(device_t, int); 362 void cpu_setup(device_t, struct cpu_info *); 363 void cpu_identify(char *, size_t); 364 int cpu_get_dfs(void); 365 void cpu_set_dfs(int); 366 void delay (unsigned int); 367 void cpu_probe_cache(void); 368 #ifndef PPC_BOOKE 369 void dcache_flush_page(vaddr_t); 370 void icache_flush_page(vaddr_t); 371 void dcache_flush(vaddr_t, vsize_t); 372 void icache_flush(vaddr_t, vsize_t); 373 #else 374 void dcache_wb_page(vaddr_t); 375 void dcache_wbinv_page(vaddr_t); 376 void dcache_inv_page(vaddr_t); 377 void dcache_zero_page(vaddr_t); 378 void icache_inv_page(vaddr_t); 379 void dcache_wb(vaddr_t, vsize_t); 380 void dcache_wbinv(vaddr_t, vsize_t); 381 void dcache_inv(vaddr_t, vsize_t); 382 void icache_inv(vaddr_t, vsize_t); 383 #endif 384 void *mapiodev(paddr_t, psize_t); 385 void unmapiodev(vaddr_t, vsize_t); 386 387 #ifdef MULTIPROCESSOR 388 int md_setup_trampoline(volatile struct cpu_hatch_data *, struct cpu_info *); 389 void md_presync_timebase(volatile struct cpu_hatch_data *); 390 void md_start_timebase(volatile struct cpu_hatch_data *); 391 void md_sync_timebase(volatile struct cpu_hatch_data *); 392 void md_setup_interrupts(void); 393 int cpu_spinup(struct device *, struct cpu_info *); 394 register_t cpu_hatch(void); 395 void cpu_spinup_trampoline(void); 396 #endif 397 398 #define DELAY(n) delay(n) 399 400 void * cpu_uarea_alloc(bool); 401 bool cpu_uarea_free(void *); 402 void cpu_need_resched(struct cpu_info *, int); 403 void cpu_signotify(struct lwp *); 404 void cpu_need_proftick(struct lwp *); 405 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 406 407 void cpu_fixup_stubs(void); 408 409 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) 410 void oea_init(void (*)(void)); 411 void oea_startup(const char *); 412 void oea_dumpsys(void); 413 void oea_install_extint(void (*)(void)); 414 paddr_t kvtop(void *); 415 void softnet(int); 416 417 extern paddr_t msgbuf_paddr; 418 extern int cpu_altivec; 419 #endif 420 421 #endif /* _KERNEL */ 422 423 /* XXX The below breaks unified pmap on ppc32 */ 424 425 #if defined(_KERNEL) || defined(_STANDALONE) 426 #if !defined(CACHELINESIZE) 427 #ifdef PPC_IBM403 428 #define CACHELINESIZE 16 429 #define MAXCACHELINESIZE 16 430 #else 431 #if defined (PPC_OEA64_BRIDGE) 432 #define CACHELINESIZE 128 433 #define MAXCACHELINESIZE 128 434 #else 435 #define CACHELINESIZE 32 436 #define MAXCACHELINESIZE 32 437 #endif /* PPC_OEA64_BRIDGE */ 438 #endif 439 #endif 440 #endif 441 442 void __syncicache(void *, size_t); 443 444 /* 445 * CTL_MACHDEP definitions. 446 */ 447 #define CPU_CACHELINE 1 448 #define CPU_TIMEBASE 2 449 #define CPU_CPUTEMP 3 450 #define CPU_PRINTFATALTRAPS 4 451 #define CPU_CACHEINFO 5 452 #define CPU_ALTIVEC 6 453 #define CPU_MODEL 7 454 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 455 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 456 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 457 #define CPU_MAXID 11 /* number of valid machdep ids */ 458 459 #endif /* _POWERPC_CPU_H_ */ 460
Indexes created Fri Sep 26 08:10:20 GMT 2025