cpu.h revision 1.84
1 /* $NetBSD: cpu.h,v 1.84 2011/06/20 17:15:38 matt Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_modular.h" 49 #include "opt_multiprocessor.h" 50 #include "opt_ppcarch.h" 51 #endif 52 53 #ifdef _KERNEL 54 #include <machine/intr.h> 55 #include <sys/device_if.h> 56 #include <sys/evcnt.h> 57 #endif 58 59 #include <sys/cpu_data.h> 60 61 struct cpu_info { 62 struct cpu_data ci_data; /* MI per-cpu data */ 63 #ifdef _KERNEL 64 device_t ci_dev; /* device of corresponding cpu */ 65 struct cpu_softc *ci_softc; /* private cpu info */ 66 struct lwp *ci_curlwp; /* current owner of the processor */ 67 68 struct pcb *ci_curpcb; 69 struct pmap *ci_curpm; 70 struct lwp *ci_softlwps[SOFTINT_COUNT]; 71 int ci_cpuid; /* from SPR_PIR */ 72 73 int ci_want_resched; 74 volatile uint64_t ci_lastintr; 75 volatile u_long ci_lasttb; 76 volatile int ci_tickspending; 77 volatile int ci_cpl; 78 volatile int ci_iactive; 79 volatile int ci_idepth; 80 union { 81 #if !defined(PPC_BOOKE) && !defined(_MODULE) 82 volatile imask_t un1_ipending; 83 #define ci_ipending ci_un1.un1_ipending 84 #endif 85 uint64_t un1_pad64; 86 } ci_un1; 87 volatile uint32_t ci_pending_ipis; 88 int ci_mtx_oldspl; 89 int ci_mtx_count; 90 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 91 char *ci_intstk; 92 #endif 93 #define CI_SAVETEMP (0*CPUSAVE_LEN) 94 #define CI_SAVEDDB (1*CPUSAVE_LEN) 95 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) 96 #define CI_SAVEMMU (3*CPUSAVE_LEN) 97 #define CI_SAVEMAX (4*CPUSAVE_LEN) 98 #define CPUSAVE_LEN 8 99 #if !defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 100 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 101 #else 102 #define CPUSAVE_SIZE 128 103 #endif 104 #define CPUSAVE_R28 0 /* where r28 gets saved */ 105 #define CPUSAVE_R29 1 /* where r29 gets saved */ 106 #define CPUSAVE_R30 2 /* where r30 gets saved */ 107 #define CPUSAVE_R31 3 /* where r31 gets saved */ 108 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 109 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 110 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 111 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 112 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 113 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 114 register_t ci_savearea[CPUSAVE_SIZE]; 115 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 116 struct pmap_segtab *ci_pmap_segtabs[2]; 117 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 118 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 119 struct pmap_tlb_info *ci_tlb_info; 120 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 121 struct cache_info ci_ci; 122 void *ci_sysmon_cookie; 123 void (*ci_idlespin)(void); 124 uint32_t ci_khz; 125 struct evcnt ci_ev_clock; /* clock intrs */ 126 struct evcnt ci_ev_statclock; /* stat clock */ 127 struct evcnt ci_ev_softclock; /* softclock intrs */ 128 struct evcnt ci_ev_softnet; /* softnet intrs */ 129 struct evcnt ci_ev_softserial; /* softserial intrs */ 130 struct evcnt ci_ev_traps; /* calls to trap() */ 131 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 132 struct evcnt ci_ev_udsi; /* user DSI traps */ 133 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 134 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 135 struct evcnt ci_ev_isi; /* user ISI traps */ 136 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 137 struct evcnt ci_ev_pgm; /* user PGM traps */ 138 struct evcnt ci_ev_debug; /* user debug traps */ 139 struct evcnt ci_ev_fpu; /* FPU traps */ 140 struct evcnt ci_ev_fpusw; /* FPU context switch */ 141 struct evcnt ci_ev_ali; /* Alignment traps */ 142 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 143 struct evcnt ci_ev_scalls; /* system call traps */ 144 struct evcnt ci_ev_vec; /* Altivec traps */ 145 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 146 struct evcnt ci_ev_umchk; /* user MCHK events */ 147 struct evcnt ci_ev_ipi; /* IPIs received */ 148 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 149 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 150 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 151 #endif /* _KERNEL */ 152 }; 153 #endif /* _KERNEL || _KMEMUSER */ 154 155 #ifdef _KERNEL 156 157 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 158 struct cpu_hatch_data { 159 device_t self; 160 struct cpu_info *ci; 161 int running; 162 int pir; 163 int asr; 164 int hid0; 165 int sdr1; 166 int sr[16]; 167 int batu[4], batl[4]; 168 int tbu, tbl; 169 }; 170 #endif /* MULTIPROCESSOR && !_MODULE */ 171 172 #if defined(MULTIPROCESSOR) || defined(_MODULE) 173 #define cpu_number() (curcpu()->ci_index + 0) 174 175 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 176 #define CPU_INFO_ITERATOR int 177 #define CPU_INFO_FOREACH(cii, ci) \ 178 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 179 180 #else 181 #define cpu_number() 0 182 183 #define CPU_IS_PRIMARY(ci) true 184 #define CPU_INFO_ITERATOR int 185 #define CPU_INFO_FOREACH(cii, ci) \ 186 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 187 188 #endif /* MULTIPROCESSOR || _MODULE */ 189 190 extern struct cpu_info cpu_info[]; 191 192 static __inline struct cpu_info * curcpu(void) __pure; 193 static __inline struct cpu_info * 194 curcpu(void) 195 { 196 struct cpu_info *ci; 197 198 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 199 return ci; 200 } 201 202 register struct lwp *powerpc_curlwp __asm("r13"); 203 #define curlwp powerpc_curlwp 204 #define curpcb (curcpu()->ci_curpcb) 205 #define curpm (curcpu()->ci_curpm) 206 207 static __inline register_t 208 mfmsr(void) 209 { 210 register_t msr; 211 212 __asm volatile ("mfmsr %0" : "=r"(msr)); 213 return msr; 214 } 215 216 static __inline void 217 mtmsr(register_t msr) 218 { 219 //KASSERT(msr & PSL_CE); 220 //KASSERT(msr & PSL_DE); 221 __asm volatile ("mtmsr %0" : : "r"(msr)); 222 } 223 224 #if !defined(_MODULE) 225 static __inline uint32_t 226 mftbl(void) 227 { 228 uint32_t tbl; 229 230 __asm volatile ( 231 #ifdef PPC_IBM403 232 " mftblo %[tbl]" "\n" 233 #elif defined(PPC_BOOKE) 234 " mfspr %[tbl],268" "\n" 235 #else 236 " mftbl %[tbl]" "\n" 237 #endif 238 : [tbl] "=r" (tbl)); 239 240 return tbl; 241 } 242 243 static __inline uint64_t 244 mftb(void) 245 { 246 uint64_t tb; 247 248 #ifdef _LP64 249 __asm volatile ("mftb %0" : "=r"(tb)); 250 #else 251 int tmp; 252 253 __asm volatile ( 254 #ifdef PPC_IBM403 255 "1: mftbhi %[tb]" "\n" 256 " mftblo %L[tb]" "\n" 257 " mftbhi %[tmp]" "\n" 258 #elif defined(PPC_BOOKE) 259 "1: mfspr %[tb],269" "\n" 260 " mfspr %L[tb],268" "\n" 261 " mfspr %[tmp],269" "\n" 262 #else 263 "1: mftbu %[tb]" "\n" 264 " mftb %L[tb]" "\n" 265 " mftbu %[tmp]" "\n" 266 #endif 267 " cmplw %[tb],%[tmp]" "\n" 268 " bne- 1b" "\n" 269 : [tb] "=r" (tb), [tmp] "=r"(tmp) 270 :: "cr0"); 271 #endif 272 273 return tb; 274 } 275 276 static __inline uint32_t 277 mfrtcl(void) 278 { 279 uint32_t rtcl; 280 281 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 282 return rtcl; 283 } 284 285 static __inline void 286 mfrtc(uint32_t *rtcp) 287 { 288 uint32_t tmp; 289 290 __asm volatile ( 291 "1: mfrtcu %[rtcu]" "\n" 292 " mfrtcl %[rtcl]" "\n" 293 " mfrtcu %[tmp]" "\n" 294 " cmplw %[rtcu],%[tmp]" "\n" 295 " bne- 1b" 296 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 297 :: "cr0"); 298 } 299 #endif /* !_MODULE */ 300 301 static __inline uint32_t 302 mfpvr(void) 303 { 304 uint32_t pvr; 305 306 __asm volatile ("mfpvr %0" : "=r"(pvr)); 307 return (pvr); 308 } 309 310 #ifdef _MODULE 311 extern const char __CPU_MAXNUM; 312 /* 313 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 314 * corresponding R_PPC_ADDR16_HI relocation. 315 */ 316 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 317 #endif /* _MODULE */ 318 319 #if !defined(_MODULE) 320 extern int powersave; 321 extern int cpu_timebase; 322 extern int cpu_printfataltraps; 323 extern char cpu_model[]; 324 325 struct cpu_info * 326 cpu_attach_common(device_t, int); 327 void cpu_setup(device_t, struct cpu_info *); 328 void cpu_identify(char *, size_t); 329 int cpu_get_dfs(void); 330 void cpu_set_dfs(int); 331 void cpu_probe_cache(void); 332 #ifndef PPC_BOOKE 333 void dcache_flush_page(vaddr_t); 334 void icache_flush_page(vaddr_t); 335 void dcache_flush(vaddr_t, vsize_t); 336 void icache_flush(vaddr_t, vsize_t); 337 #else 338 void dcache_wb_page(vaddr_t); 339 void dcache_wbinv_page(vaddr_t); 340 void dcache_inv_page(vaddr_t); 341 void dcache_zero_page(vaddr_t); 342 void icache_inv_page(vaddr_t); 343 void dcache_wb(vaddr_t, vsize_t); 344 void dcache_wbinv(vaddr_t, vsize_t); 345 void dcache_inv(vaddr_t, vsize_t); 346 void icache_inv(vaddr_t, vsize_t); 347 #endif 348 void * mapiodev(paddr_t, psize_t); 349 void unmapiodev(vaddr_t, vsize_t); 350 351 #ifdef MULTIPROCESSOR 352 int md_setup_trampoline(volatile struct cpu_hatch_data *, 353 struct cpu_info *); 354 void md_presync_timebase(volatile struct cpu_hatch_data *); 355 void md_start_timebase(volatile struct cpu_hatch_data *); 356 void md_sync_timebase(volatile struct cpu_hatch_data *); 357 void md_setup_interrupts(void); 358 int cpu_spinup(device_t, struct cpu_info *); 359 register_t 360 cpu_hatch(void); 361 void cpu_spinup_trampoline(void); 362 void cpu_boot_secondary_processors(void); 363 #endif /* MULTIPROCESSOR */ 364 #endif /* !_MODULE */ 365 366 #define cpu_proc_fork(p1, p2) 367 368 #define DELAY(n) delay(n) 369 void delay(unsigned int); 370 371 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 372 #define CLKF_PC(cf) cpu_clkf_pc(cf) 373 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 374 375 bool cpu_clkf_usermode(const struct clockframe *); 376 vaddr_t cpu_clkf_pc(const struct clockframe *); 377 bool cpu_clkf_intr(const struct clockframe *); 378 379 #define LWP_PC(l) cpu_lwp_pc(l) 380 381 vaddr_t cpu_lwp_pc(struct lwp *); 382 383 void * cpu_uarea_alloc(bool); 384 bool cpu_uarea_free(void *); 385 void cpu_need_resched(struct cpu_info *, int); 386 void cpu_signotify(struct lwp *); 387 void cpu_need_proftick(struct lwp *); 388 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 389 390 void cpu_fixup_stubs(void); 391 392 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 393 void oea_init(void (*)(void)); 394 void oea_startup(const char *); 395 void oea_dumpsys(void); 396 void oea_install_extint(void (*)(void)); 397 paddr_t kvtop(void *); 398 399 extern paddr_t msgbuf_paddr; 400 extern int cpu_altivec; 401 #endif 402 403 #endif /* _KERNEL */ 404 405 /* XXX The below breaks unified pmap on ppc32 */ 406 407 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 408 && (defined(_KERNEL) || defined(_STANDALONE)) 409 #if defined(PPC_IBM403) 410 #define CACHELINESIZE 16 411 #define MAXCACHELINESIZE 16 412 #elif defined (PPC_OEA64_BRIDGE) 413 #define CACHELINESIZE 128 414 #define MAXCACHELINESIZE 128 415 #else 416 #define CACHELINESIZE 32 417 #define MAXCACHELINESIZE 32 418 #endif /* PPC_OEA64_BRIDGE */ 419 #endif 420 421 void __syncicache(void *, size_t); 422 423 /* 424 * CTL_MACHDEP definitions. 425 */ 426 #define CPU_CACHELINE 1 427 #define CPU_TIMEBASE 2 428 #define CPU_CPUTEMP 3 429 #define CPU_PRINTFATALTRAPS 4 430 #define CPU_CACHEINFO 5 431 #define CPU_ALTIVEC 6 432 #define CPU_MODEL 7 433 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 434 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 435 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 436 #define CPU_MAXID 11 /* number of valid machdep ids */ 437 438 #endif /* _POWERPC_CPU_H_ */ 439
Indexes created Wed Sep 24 05:09:52 GMT 2025