cpu.h revision 1.88.6.3
1 /* $NetBSD: cpu.h,v 1.88.6.3 2012/04/29 23:04:41 mrg Exp $ */ 2 3 /* 4 * Copyright (C) 1999 Wolfgang Solfrank. 5 * Copyright (C) 1999 TooLs GmbH. 6 * Copyright (C) 1995-1997 Wolfgang Solfrank. 7 * Copyright (C) 1995-1997 TooLs GmbH. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by TooLs GmbH. 21 * 4. The name of TooLs GmbH may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 #ifndef _POWERPC_CPU_H_ 36 #define _POWERPC_CPU_H_ 37 38 struct cache_info { 39 int dcache_size; 40 int dcache_line_size; 41 int icache_size; 42 int icache_line_size; 43 }; 44 45 #if defined(_KERNEL) || defined(_KMEMUSER) 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_modular.h" 49 #include "opt_multiprocessor.h" 50 #include "opt_ppcarch.h" 51 #endif 52 53 #ifdef _KERNEL 54 #include <machine/intr.h> 55 #include <sys/device_if.h> 56 #include <sys/evcnt.h> 57 #endif 58 59 #include <sys/cpu_data.h> 60 61 struct cpu_info { 62 struct cpu_data ci_data; /* MI per-cpu data */ 63 #ifdef _KERNEL 64 device_t ci_dev; /* device of corresponding cpu */ 65 struct cpu_softc *ci_softc; /* private cpu info */ 66 struct lwp *ci_curlwp; /* current owner of the processor */ 67 68 struct pcb *ci_curpcb; 69 struct pmap *ci_curpm; 70 struct lwp *ci_softlwps[SOFTINT_COUNT]; 71 int ci_cpuid; /* from SPR_PIR */ 72 73 int ci_want_resched; 74 volatile uint64_t ci_lastintr; 75 volatile u_long ci_lasttb; 76 volatile int ci_tickspending; 77 volatile int ci_cpl; 78 volatile int ci_iactive; 79 volatile int ci_idepth; 80 union { 81 #if !defined(PPC_BOOKE) && !defined(_MODULE) 82 volatile imask_t un1_ipending; 83 #define ci_ipending ci_un1.un1_ipending 84 #endif 85 uint64_t un1_pad64; 86 } ci_un1; 87 volatile uint32_t ci_pending_ipis; 88 int ci_mtx_oldspl; 89 int ci_mtx_count; 90 #if defined(PPC_IBM4XX) || defined(MODULAR) || defined(_MODULE) 91 char *ci_intstk; 92 #endif 93 #define CI_SAVETEMP (0*CPUSAVE_LEN) 94 #define CI_SAVEDDB (1*CPUSAVE_LEN) 95 #define CI_SAVEIPKDB (2*CPUSAVE_LEN) 96 #define CI_SAVEMMU (3*CPUSAVE_LEN) 97 #define CI_SAVEMAX (4*CPUSAVE_LEN) 98 #define CPUSAVE_LEN 8 99 #if !defined(PPC_BOOKE) && !defined(MODULAR) && !defined(_MODULE) 100 #define CPUSAVE_SIZE (CI_SAVEMAX*CPUSAVE_LEN) 101 #else 102 #define CPUSAVE_SIZE 128 103 #endif 104 #define CPUSAVE_R28 0 /* where r28 gets saved */ 105 #define CPUSAVE_R29 1 /* where r29 gets saved */ 106 #define CPUSAVE_R30 2 /* where r30 gets saved */ 107 #define CPUSAVE_R31 3 /* where r31 gets saved */ 108 #define CPUSAVE_DEAR 4 /* where IBM4XX SPR_DEAR gets saved */ 109 #define CPUSAVE_DAR 4 /* where OEA SPR_DAR gets saved */ 110 #define CPUSAVE_ESR 5 /* where IBM4XX SPR_ESR gets saved */ 111 #define CPUSAVE_DSISR 5 /* where OEA SPR_DSISR gets saved */ 112 #define CPUSAVE_SRR0 6 /* where SRR0 gets saved */ 113 #define CPUSAVE_SRR1 7 /* where SRR1 gets saved */ 114 register_t ci_savearea[CPUSAVE_SIZE]; 115 #if defined(PPC_BOOKE) || defined(MODULAR) || defined(_MODULE) 116 uint32_t ci_pmap_asid_cur; 117 struct pmap_segtab *ci_pmap_segtabs[2]; 118 #define ci_pmap_kern_segtab ci_pmap_segtabs[0] 119 #define ci_pmap_user_segtab ci_pmap_segtabs[1] 120 struct pmap_tlb_info *ci_tlb_info; 121 #endif /* PPC_BOOKE || MODULAR || _MODULE */ 122 struct cache_info ci_ci; 123 void *ci_sysmon_cookie; 124 void (*ci_idlespin)(void); 125 uint32_t ci_khz; 126 struct evcnt ci_ev_clock; /* clock intrs */ 127 struct evcnt ci_ev_statclock; /* stat clock */ 128 struct evcnt ci_ev_traps; /* calls to trap() */ 129 struct evcnt ci_ev_kdsi; /* kernel DSI traps */ 130 struct evcnt ci_ev_udsi; /* user DSI traps */ 131 struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */ 132 struct evcnt ci_ev_kisi; /* kernel ISI traps */ 133 struct evcnt ci_ev_isi; /* user ISI traps */ 134 struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */ 135 struct evcnt ci_ev_pgm; /* user PGM traps */ 136 struct evcnt ci_ev_debug; /* user debug traps */ 137 struct evcnt ci_ev_fpu; /* FPU traps */ 138 struct evcnt ci_ev_fpusw; /* FPU context switch */ 139 struct evcnt ci_ev_ali; /* Alignment traps */ 140 struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */ 141 struct evcnt ci_ev_scalls; /* system call traps */ 142 struct evcnt ci_ev_vec; /* Altivec traps */ 143 struct evcnt ci_ev_vecsw; /* Altivec context switches */ 144 struct evcnt ci_ev_umchk; /* user MCHK events */ 145 struct evcnt ci_ev_ipi; /* IPIs received */ 146 struct evcnt ci_ev_tlbmiss_soft; /* tlb miss (no trap) */ 147 struct evcnt ci_ev_dtlbmiss_hard; /* data tlb miss (trap) */ 148 struct evcnt ci_ev_itlbmiss_hard; /* instruction tlb miss (trap) */ 149 #endif /* _KERNEL */ 150 }; 151 #endif /* _KERNEL || _KMEMUSER */ 152 153 #ifdef _KERNEL 154 155 #if defined(MULTIPROCESSOR) && !defined(_MODULE) 156 struct cpu_hatch_data { 157 int hatch_running; 158 device_t hatch_self; 159 struct cpu_info *hatch_ci; 160 uint32_t hatch_tbu; 161 uint32_t hatch_tbl; 162 uint32_t hatch_hid0; 163 uint32_t hatch_pir; 164 #if defined(PPC_OEA) || defined(PPC_OEA64_BRIDGE) 165 uintptr_t hatch_asr; 166 uintptr_t hatch_sdr1; 167 uint32_t hatch_sr[16]; 168 uintptr_t hatch_batu[8], hatch_batl[8]; 169 #endif 170 #if defined(PPC_BOOKE) 171 vaddr_t hatch_sp; 172 #endif 173 }; 174 175 struct cpuset_info { 176 __cpuset_t cpus_running; 177 __cpuset_t cpus_hatched; 178 __cpuset_t cpus_paused; 179 __cpuset_t cpus_resumed; 180 __cpuset_t cpus_halted; 181 }; 182 183 extern volatile struct cpuset_info cpuset_info; 184 #endif /* MULTIPROCESSOR && !_MODULE */ 185 186 #if defined(MULTIPROCESSOR) || defined(_MODULE) 187 #define cpu_number() (curcpu()->ci_index + 0) 188 189 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 190 #define CPU_INFO_ITERATOR int 191 #define CPU_INFO_FOREACH(cii, ci) \ 192 cii = 0, ci = &cpu_info[0]; cii < ncpu; cii++, ci++ 193 194 #else 195 #define cpu_number() 0 196 197 #define CPU_IS_PRIMARY(ci) true 198 #define CPU_INFO_ITERATOR int 199 #define CPU_INFO_FOREACH(cii, ci) \ 200 cii = 0, ci = curcpu(); ci != NULL; ci = NULL 201 202 #endif /* MULTIPROCESSOR || _MODULE */ 203 204 extern struct cpu_info cpu_info[]; 205 206 static __inline struct cpu_info * curcpu(void) __pure; 207 static __inline struct cpu_info * 208 curcpu(void) 209 { 210 struct cpu_info *ci; 211 212 __asm volatile ("mfsprg0 %0" : "=r"(ci)); 213 return ci; 214 } 215 216 #ifdef __clang__ 217 #define curlwp (curcpu()->ci_curlwp) 218 #else 219 register struct lwp *powerpc_curlwp __asm("r13"); 220 #define curlwp powerpc_curlwp 221 #endif 222 #define curpcb (curcpu()->ci_curpcb) 223 #define curpm (curcpu()->ci_curpm) 224 225 static __inline register_t 226 mfmsr(void) 227 { 228 register_t msr; 229 230 __asm volatile ("mfmsr %0" : "=r"(msr)); 231 return msr; 232 } 233 234 static __inline void 235 mtmsr(register_t msr) 236 { 237 //KASSERT(msr & PSL_CE); 238 //KASSERT(msr & PSL_DE); 239 __asm volatile ("mtmsr %0" : : "r"(msr)); 240 } 241 242 #if !defined(_MODULE) 243 static __inline uint32_t 244 mftbl(void) 245 { 246 uint32_t tbl; 247 248 __asm volatile ( 249 #ifdef PPC_IBM403 250 " mftblo %[tbl]" "\n" 251 #elif defined(PPC_BOOKE) 252 " mfspr %[tbl],268" "\n" 253 #else 254 " mftbl %[tbl]" "\n" 255 #endif 256 : [tbl] "=r" (tbl)); 257 258 return tbl; 259 } 260 261 static __inline uint64_t 262 mftb(void) 263 { 264 uint64_t tb; 265 266 #ifdef _LP64 267 __asm volatile ("mftb %0" : "=r"(tb)); 268 #else 269 int tmp; 270 271 __asm volatile ( 272 #ifdef PPC_IBM403 273 "1: mftbhi %[tb]" "\n" 274 " mftblo %L[tb]" "\n" 275 " mftbhi %[tmp]" "\n" 276 #elif defined(PPC_BOOKE) 277 "1: mfspr %[tb],269" "\n" 278 " mfspr %L[tb],268" "\n" 279 " mfspr %[tmp],269" "\n" 280 #else 281 "1: mftbu %[tb]" "\n" 282 " mftb %L[tb]" "\n" 283 " mftbu %[tmp]" "\n" 284 #endif 285 " cmplw %[tb],%[tmp]" "\n" 286 " bne- 1b" "\n" 287 : [tb] "=r" (tb), [tmp] "=r"(tmp) 288 :: "cr0"); 289 #endif 290 291 return tb; 292 } 293 294 static __inline uint32_t 295 mfrtcl(void) 296 { 297 uint32_t rtcl; 298 299 __asm volatile ("mfrtcl %0" : "=r"(rtcl)); 300 return rtcl; 301 } 302 303 static __inline void 304 mfrtc(uint32_t *rtcp) 305 { 306 uint32_t tmp; 307 308 __asm volatile ( 309 "1: mfrtcu %[rtcu]" "\n" 310 " mfrtcl %[rtcl]" "\n" 311 " mfrtcu %[tmp]" "\n" 312 " cmplw %[rtcu],%[tmp]" "\n" 313 " bne- 1b" 314 : [rtcu] "=r"(rtcp[0]), [rtcl] "=r"(rtcp[1]), [tmp] "=r"(tmp) 315 :: "cr0"); 316 } 317 #endif /* !_MODULE */ 318 319 static __inline uint32_t 320 mfpvr(void) 321 { 322 uint32_t pvr; 323 324 __asm volatile ("mfpvr %0" : "=r"(pvr)); 325 return (pvr); 326 } 327 328 #ifdef _MODULE 329 extern const char __CPU_MAXNUM; 330 /* 331 * Make with 0xffff to force a R_PPC_ADDR16_LO without the 332 * corresponding R_PPC_ADDR16_HI relocation. 333 */ 334 #define CPU_MAXNUM (((uintptr_t)&__CPU_MAXNUM)&0xffff) 335 #endif /* _MODULE */ 336 337 #if !defined(_MODULE) 338 extern int powersave; 339 extern int cpu_timebase; 340 extern int cpu_printfataltraps; 341 extern char cpu_model[]; 342 343 struct cpu_info * 344 cpu_attach_common(device_t, int); 345 void cpu_setup(device_t, struct cpu_info *); 346 void cpu_identify(char *, size_t); 347 void cpu_probe_cache(void); 348 349 void dcache_wb_page(vaddr_t); 350 void dcache_wbinv_page(vaddr_t); 351 void dcache_inv_page(vaddr_t); 352 void dcache_zero_page(vaddr_t); 353 void icache_inv_page(vaddr_t); 354 void dcache_wb(vaddr_t, vsize_t); 355 void dcache_wbinv(vaddr_t, vsize_t); 356 void dcache_inv(vaddr_t, vsize_t); 357 void icache_inv(vaddr_t, vsize_t); 358 359 void * mapiodev(paddr_t, psize_t, bool); 360 void unmapiodev(vaddr_t, vsize_t); 361 362 #ifdef MULTIPROCESSOR 363 int md_setup_trampoline(volatile struct cpu_hatch_data *, 364 struct cpu_info *); 365 void md_presync_timebase(volatile struct cpu_hatch_data *); 366 void md_start_timebase(volatile struct cpu_hatch_data *); 367 void md_sync_timebase(volatile struct cpu_hatch_data *); 368 void md_setup_interrupts(void); 369 int cpu_spinup(device_t, struct cpu_info *); 370 register_t 371 cpu_hatch(void); 372 void cpu_spinup_trampoline(void); 373 void cpu_boot_secondary_processors(void); 374 #endif /* MULTIPROCESSOR */ 375 #endif /* !_MODULE */ 376 377 #define cpu_proc_fork(p1, p2) 378 379 #define DELAY(n) delay(n) 380 void delay(unsigned int); 381 382 #define CLKF_USERMODE(cf) cpu_clkf_usermode(cf) 383 #define CLKF_PC(cf) cpu_clkf_pc(cf) 384 #define CLKF_INTR(cf) cpu_clkf_intr(cf) 385 386 bool cpu_clkf_usermode(const struct clockframe *); 387 vaddr_t cpu_clkf_pc(const struct clockframe *); 388 bool cpu_clkf_intr(const struct clockframe *); 389 390 #define LWP_PC(l) cpu_lwp_pc(l) 391 392 vaddr_t cpu_lwp_pc(struct lwp *); 393 394 void cpu_ast(struct lwp *, struct cpu_info *); 395 void * cpu_uarea_alloc(bool); 396 bool cpu_uarea_free(void *); 397 void cpu_need_resched(struct cpu_info *, int); 398 void cpu_signotify(struct lwp *); 399 void cpu_need_proftick(struct lwp *); 400 #define cpu_did_resched(l) ((l)->l_md.md_astpending = 0) 401 402 void cpu_fixup_stubs(void); 403 404 #if !defined(PPC_IBM4XX) && !defined(PPC_BOOKE) && !defined(_MODULE) 405 int cpu_get_dfs(void); 406 void cpu_set_dfs(int); 407 408 void oea_init(void (*)(void)); 409 void oea_startup(const char *); 410 void oea_dumpsys(void); 411 void oea_install_extint(void (*)(void)); 412 paddr_t kvtop(void *); 413 414 extern paddr_t msgbuf_paddr; 415 extern int cpu_altivec; 416 #endif 417 418 #endif /* _KERNEL */ 419 420 /* XXX The below breaks unified pmap on ppc32 */ 421 422 #if !defined(CACHELINESIZE) && !defined(_MODULE) \ 423 && (defined(_KERNEL) || defined(_STANDALONE)) 424 #if defined(PPC_IBM403) 425 #define CACHELINESIZE 16 426 #define MAXCACHELINESIZE 16 427 #elif defined (PPC_OEA64_BRIDGE) 428 #define CACHELINESIZE 128 429 #define MAXCACHELINESIZE 128 430 #else 431 #define CACHELINESIZE 32 432 #define MAXCACHELINESIZE 32 433 #endif /* PPC_OEA64_BRIDGE */ 434 #endif 435 436 void __syncicache(void *, size_t); 437 438 /* 439 * CTL_MACHDEP definitions. 440 */ 441 #define CPU_CACHELINE 1 442 #define CPU_TIMEBASE 2 443 #define CPU_CPUTEMP 3 444 #define CPU_PRINTFATALTRAPS 4 445 #define CPU_CACHEINFO 5 446 #define CPU_ALTIVEC 6 447 #define CPU_MODEL 7 448 #define CPU_POWERSAVE 8 /* int: use CPU powersave mode */ 449 #define CPU_BOOTED_DEVICE 9 /* string: device we booted from */ 450 #define CPU_BOOTED_KERNEL 10 /* string: kernel we booted */ 451 #define CPU_EXECPROT 11 /* bool: PROT_EXEC works */ 452 #define CPU_MAXID 12 /* number of valid machdep ids */ 453 454 #endif /* _POWERPC_CPU_H_ */ 455
Indexes created Sun Oct 19 02:09:48 GMT 2025