instr.h revision 1.4.104.4
1 /* $NetBSD: instr.h,v 1.4.104.4 2011/10/14 17:21:26 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)instr.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 #ifndef _POWERPC_INSTR_H_ 44 #define _POWERPC_INSTR_H_ 45 46 /* 47 * An instruction. 48 */ 49 union instr { 50 int i_int; /* as a whole */ 51 52 53 /* 54 * Any instruction type. 55 */ 56 struct { 57 u_int i_opcd:6; /* first-level decode */ 58 u_int :25; 59 u_int i_rc:1; 60 } i_any; 61 62 /* 63 * Format A 64 */ 65 struct { 66 u_int i_opcd:6; 67 u_int i_frt:5; 68 u_int i_fra:5; 69 u_int i_frb:5; 70 u_int i_frc:5; 71 u_int i_xo:5; 72 u_int i_rc:1; 73 } i_a; 74 75 /* 76 * Format B 77 */ 78 struct { 79 u_int i_opcd:6; 80 u_int i_bo:5; 81 u_int i_bi:5; 82 int i_bd:14; 83 u_int i_aa:1; 84 u_int i_lk:1; 85 } i_b; 86 87 /* 88 * Format D 89 */ 90 struct { 91 u_int i_opcd:6; 92 u_int i_rs:5; 93 u_int i_ra:5; 94 int i_d:16; 95 } i_d; 96 97 /* 98 * Format DE 99 */ 100 struct { 101 u_int i_opcd:6; 102 u_int i_rs:5; 103 u_int i_ra:5; 104 int i_d:12; 105 u_int i_xo:4; 106 } i_de; 107 108 /* 109 * Format I 110 */ 111 struct { 112 u_int i_opcd:6; 113 int i_li:24; 114 int i_aa:1; 115 int i_lk:1; 116 } i_i; 117 118 /* 119 * Format M 120 */ 121 struct { 122 u_int i_opcd:6; 123 u_int i_rs:5; 124 u_int i_ra:5; 125 u_int i_rb:5; 126 int i_mb:5; 127 int i_me:5; 128 u_int i_rc:1; 129 } i_m; 130 131 /* 132 * Format MD 133 */ 134 struct { 135 u_int i_opcd:6; 136 u_int i_rs:5; 137 u_int i_ra:5; 138 u_int i_rb:5; 139 int i_sh1_5:5; 140 int i_mb:6; 141 u_int i_xo:3; 142 int i_sh0:2; 143 u_int i_rc:1; 144 } i_md; 145 146 /* 147 * Format MDS 148 */ 149 struct { 150 u_int i_opcd:6; 151 u_int i_rs:5; 152 u_int i_ra:5; 153 u_int i_rb:5; 154 int i_sh:5; 155 int i_mb:6; 156 u_int i_xo:4; 157 u_int i_rc:1; 158 } i_mds; 159 160 161 /* 162 * Format S 163 */ 164 struct { 165 u_int i_opcd:6; 166 int :24; 167 int i_i:1; 168 int :1; 169 } i_s; 170 171 /* 172 * Format X 173 */ 174 struct { 175 u_int i_opcd:6; 176 u_int i_rs:5; 177 u_int i_ra:5; 178 u_int i_rb:5; 179 u_int i_xo:10; 180 u_int i_rc:1; 181 } i_x; 182 183 /* 184 * Format XFL 185 */ 186 struct { 187 u_int i_opcd:6; 188 int :1; 189 int i_flm:8; 190 int :1; 191 int i_frb:5; 192 u_int i_xo:10; 193 int :1; 194 } i_xfl; 195 196 /* 197 * Format XFX 198 */ 199 struct { 200 u_int i_opcd:6; 201 int i_dcrn:10; 202 u_int i_xo:10; 203 int :1; 204 } i_xfx; 205 206 /* 207 * Format XL 208 */ 209 struct { 210 u_int i_opcd:6; 211 int i_bt:5; 212 int i_ba:5; 213 int i_bb:5; 214 u_int i_xo:10; 215 int i_lk:1; 216 } i_xl; 217 218 /* 219 * Format XS 220 */ 221 struct { 222 u_int i_opcd:6; 223 u_int i_rs:5; 224 u_int i_ra:5; 225 int i_sh0_4:5; 226 u_int i_xo:9; 227 int i_sh5:1; 228 u_int i_rc:1; 229 } i_xs; 230 231 }; 232 233 #define i_rt i_rs 234 235 /* 236 * Primary opcode numbers: 237 */ 238 239 #define OPC_TDI 0x02 240 #define OPC_TWI 0x03 241 #define OPC_MULLI 0x07 242 #define OPC_SUBFIC 0x08 243 #define OPC_BCE 0x09 244 #define OPC_CMPLI 0x0a 245 #define OPC_CMPI 0x0b 246 #define OPC_ADDIC 0x0c 247 #define OPC_ADDIC_DOT 0x0d 248 #define OPC_ADDI 0x0e 249 #define OPC_ADDIS 0x0f 250 #define OPC_BC 0x10 251 #define OPC_SC 0x11 252 #define OPC_B 0x12 253 #define OPC_branch_19 0x13 254 #define OPC_RLWIMI 0x14 255 #define OPC_RLWINM 0x15 256 #define OPC_BE 0x16 257 #define OPC_RLWNM 0x17 258 #define OPC_ORI 0x18 259 #define OPC_ORIS 0x19 260 #define OPC_XORI 0x1a 261 #define OPC_XORIS 0x1b 262 #define OPC_ANDI 0x1c 263 #define OPC_ANDIS 0x1d 264 #define OPC_dwe_rot_30 0x1e 265 #define OPC_integer_31 0x1f 266 #define OPC_LWZ 0x20 267 #define OPC_LWZU 0x21 268 #define OPC_LBZ 0x22 269 #define OPC_LBZU 0x23 270 #define OPC_STW 0x24 271 #define OPC_STWU 0x25 272 #define OPC_STB 0x26 273 #define OPC_STBU 0x27 274 #define OPC_LHZ 0x28 275 #define OPC_LHZU 0x29 276 #define OPC_LHA 0x2a 277 #define OPC_LHAU 0x2b 278 #define OPC_STH 0x2c 279 #define OPC_STHU 0x2d 280 #define OPC_LMW 0x2e 281 #define OPC_STMW 0x2f 282 #define OPC_LFS 0x30 283 #define OPC_LFSU 0x31 284 #define OPC_LFD 0x32 285 #define OPC_LFDU 0x33 286 #define OPC_STFS 0x34 287 #define OPC_STFSU 0x35 288 #define OPC_STFD 0x36 289 #define OPC_STFDU 0x37 290 #define OPC_load_st_58 0x3a 291 #define OPC_sp_fp_59 0x3b 292 #define OPC_load_st_62 0x3e 293 #define OPC_dp_fp_63 0x3f 294 295 /* 296 * Opcode 31 sub-types (FP only) 297 */ 298 #define OPC31_TW 0x004 299 #define OPC31_LFSX 0x217 300 #define OPC31_LFSUX 0x237 301 #define OPC31_LFDX 0x257 302 #define OPC31_LFDUX 0x277 303 #define OPC31_STFSX 0x297 304 #define OPC31_STFSUX 0x2b7 305 #define OPC31_STFDX 0x2d7 306 #define OPC31_STFDUX 0x2f7 307 #define OPC31_STFIWX 0x3d7 308 309 /* Mask for all valid indexed FP load/store ops (except stfiwx) */ 310 #define OPC31_FPMASK 0x31f 311 #define OPC31_FPOP 0x217 312 313 /* m[ft]spr are also opcode 31; ra/rb encode the spr */ 314 #define OPC31_MFSPR 0x153 315 #define OPC31_MTSPR 0x1d3 316 317 /* 318 * Opcode 59 sub-types: 319 */ 320 321 #define OPC59_FDIVS 0x12 322 #define OPC59_FSUBS 0x14 323 #define OPC59_FADDS 0x15 324 #define OPC59_FSQRTS 0x16 325 #define OPC59_FRES 0x18 326 #define OPC59_FMULS 0x19 327 #define OPC59_FMSUBS 0x1c 328 #define OPC59_FMADDS 0x1d 329 #define OPC59_FNMSUBS 0x1e 330 #define OPC59_FNMADDS 0x1f 331 332 /* 333 * Opcode 62 sub-types: 334 */ 335 #define OPC62_LDE 0x0 336 #define OPC62_LDEU 0x1 337 #define OPC62_LFSE 0x4 338 #define OPC62_LFSEU 0x5 339 #define OPC62_LFDE 0x6 340 #define OPC62_LFDEU 0x7 341 #define OPC62_STDE 0x8 342 #define OPC62_STDEU 0x9 343 #define OPC62_STFSE 0xc 344 #define OPC62_STFSEU 0xd 345 #define OPC62_STFDE 0xe 346 #define OPC62_STFDEU 0xf 347 348 /* 349 * Opcode 63 sub-types: 350 * 351 * (The first group are masks....) 352 */ 353 354 #define OPC63M_MASK 0x10 355 #define OPC63M_FDIV 0x12 356 #define OPC63M_FSUB 0x14 357 #define OPC63M_FADD 0x15 358 #define OPC63M_FSQRT 0x16 359 #define OPC63M_FSEL 0x17 360 #define OPC63M_FMUL 0x19 361 #define OPC63M_FRSQRTE 0x1a 362 #define OPC63M_FMSUB 0x1c 363 #define OPC63M_FMADD 0x1d 364 #define OPC63M_FNMSUB 0x1e 365 #define OPC63M_FNMADD 0x1f 366 367 #define OPC63_FCMPU 0x00 368 #define OPC63_FRSP 0x0c 369 #define OPC63_FCTIW 0x0e 370 #define OPC63_FCTIWZ 0x0f 371 #define OPC63_FCMPO 0x20 372 #define OPC63_MTFSB1 0x26 373 #define OPC63_FNEG 0x28 374 #define OPC63_MCRFS 0x40 375 #define OPC63_MTFSB0 0x46 376 #define OPC63_FMR 0x48 377 #define OPC63_MTFSFI 0x86 378 #define OPC63_FNABS 0x88 379 #define OPC63_FABS 0x108 380 #define OPC63_MFFS 0x247 381 #define OPC63_MTFSF 0x2c7 382 #define OPC63_FCTID 0x32e 383 #define OPC63_FCTIDZ 0x32f 384 #define OPC63_FCFID 0x34e 385 386 /* 387 * Branch instruction modifiers. 388 */ 389 #define B_LK 0x01 /* Link flag (LR=CIA+4) */ 390 #define B_AA 0x02 /* Absolute flag */ 391 392 /* 393 * Helpers for decoding mfspr 394 */ 395 #define OPC_MFSPR_CODE 0x7c0002a6 396 #define OPC_MFSPR_MASK (~(0x1f << 21)) 397 #define OPC_MFSPR(spr) (OPC_MFSPR_CODE |\ 398 (((spr) & 0x1f) << 16) |\ 399 (((spr) & 0x3e0) << 6)) 400 #define OPC_MFSPR_REG(o) (((o) >> 21) & 0x1f) 401 #define OPC_MFSPR_P(o, spr) (((o) & OPC_MFSPR_MASK) == OPC_MFSPR(spr)) 402 403 #define OPC_MFMSR_CODE 0x7c0000a8 404 #define OPC_MFMSR_MASK 0xfc1fffff 405 #define OPC_MFMSR OPC_MFMSR_CODE 406 #define OPC_MFMSR_REG(o) (((o) >> 21) & 0x1f) 407 #define OPC_MFMSR_P(o) (((o) & OPC_MFMSR_MASK) == OPC_MFMSR_CODE) 408 409 /* 410 * booke doesn't have lwsync even though gcc emits it so we have to emulate it. 411 */ 412 #define OPC_LWSYNC 0x7c2004ac 413 414 /* 415 * FPU data types. 416 */ 417 #define FTYPE_LNG -1 /* data = 64-bit signed long integer */ 418 #define FTYPE_INT 0 /* data = 32-bit signed integer */ 419 #define FTYPE_SNG 1 /* data = 32-bit float */ 420 #define FTYPE_DBL 2 /* data = 64-bit double */ 421 422 /* 423 * FPCSR rounding modes. 424 */ 425 #define FSR_RD_RN 0 /* round to nearest */ 426 #define FSR_RD_RZ 1 /* round towards 0 */ 427 #define FSR_RD_RP 2 /* round towards +inf */ 428 #define FSR_RD_RM 3 /* round towards -inf */ 429 430 /* 431 * Convert an address to an offset used in a PowerPC branch instruction. 432 * We simply shift away the low bits since we are going convert the bl 433 * to a bla. 434 */ 435 #define fixup_addr2offset(x) ((uintptr_t)(x) >> 2) 436 struct powerpc_jump_fixup_info { 437 uint32_t jfi_stub; 438 uint32_t jfi_real; 439 }; 440 441 void powerpc_fixup_stubs(uint32_t *, uint32_t *, uint32_t *, uint32_t *); 442 443 444 #endif /* !_POWERPC_INSTR_H_ */ 445
Indexes created Fri Oct 03 02:09:57 GMT 2025