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      1 /*	$NetBSD: hid.h,v 1.15 2024/03/10 17:07:31 rillig Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _POWERPC_OEA_HID_H_
     30 #define _POWERPC_OEA_HID_H_
     31 
     32 #ifdef _KERNEL_OPT
     33 #include "opt_ppcarch.h"
     34 #endif
     35 
     36 /* Hardware Implementation Dependent registers for the PowerPC */
     37 
     38 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE)
     39 /* this way we can use the same bit numbers as IBM's PowerPC manuals */
     40 #define HIDBIT(x) (0x8000000000000000LL >> x)
     41 #define HID0_64_ONE_PPC	HIDBIT(0)   /* one instruction per dispatch group */
     42 #define HID0_64_DO_SNGL	HIDBIT(1)   /* single group completion mode */
     43 #define HID0_64_ISYNCSC	HIDBIT(2)   /* Disable isync scoreboard optimization */
     44 #define HID0_64_SER_GP	HIDBIT(3)   /* Serialize group dispatch */
     45 #define HID0_64_DEEPNAP	HIDBIT(7)   /* Enable deep nap mode (970) */
     46 #define HID0_64_DOZE	HIDBIT(8)   /* Enable doze mode */
     47 #define HID0_64_NAP	HIDBIT(9)   /* Enable nap mode */
     48 #define HID0_64_DPM	HIDBIT(11)  /* Enable Dynamic power management */
     49 #define HID0_64_TG	HIDBIT(13)  /* Perfmon threshold granularity control */
     50 #define HID0_64_HNG_DIS	HIDBIT(14)  /* Disable processor hang-detection */
     51 #define HID0_64_NHR	HIDBIT(15)  /* No Hard Reset */
     52 #define HID0_64_INORDER	HIDBIT(16)  /* Serialized group issue mode */
     53 #define HID0_64_TB_CTRL	HIDBIT(18)  /* TB keeps running if CPU stopped */
     54 #define HID0_64_EX_TBEN	HIDBIT(19)  /* timebase runs at external clock */
     55 #define HID0_64_CIABREN	HIDBIT(22)  /* enable CIABR register */
     56 #define HID0_64_HDICEEN	HIDBIT(23)  /* hypervisor decrementer enable */
     57 #define HID0_64_EN_ATTN	HIDBIT(31)  /* support processor attention inst. */
     58 #define HID0_64_EN_MCHK	HIDBIT(32)  /* ext. mchk interrupts */
     59 #endif
     60 #define HID0_EMCP	0x80000000  /* Enable MCP */
     61 #define HID0_DBP	0x40000000  /* Disable 60x bus parity generation */
     62 #define HID0_EBA	0x20000000  /* Enable 60x bus address parity checking */
     63 #define HID0_EBD	0x10000000  /* Enable 60x bus data parity checking */
     64 #define HID0_BCLK	0x08000000  /* CLK_OUT clock type selection */
     65 #define HID0_EICE	0x04000000  /* Enable ICE output */
     66 #define HID0_TBEN	0x04000000  /* Time base enable (7450) */
     67 #define HID0_ECLK	0x02000000  /* CLK_OUT clock type selection */
     68 #define HID0_PAR	0x01000000  /* Disable precharge of ARTRY */
     69 #define HID0_STEN	0x01000000  /* Software table search enable (7450) */
     70 #define HID0_DOZE	0x00800000  /* Enable doze mode */
     71 #define HID0_HIGH_BAT_EN 0x00800000  /* Enable additional BATs (74[45][578]) */
     72 #define HID0_NAP	0x00400000  /* Enable nap mode */
     73 #define HID0_SLEEP	0x00200000  /* Enable sleep mode */
     74 #define HID0_DPM	0x00100000  /* Enable Dynamic power management */
     75 #define HID0_RISEG	0x00080000  /* Read I-SEG */
     76 #define HID0_BHTCLR	0x00040000  /* Clear branch history table (7450) */
     77 #define HID0_EIEC	0x00040000  /* Enable internal error checking */
     78 #define HID0_XAEN	0x00020000  /* Enable eXtended Addressing (7450) */
     79 #define HID0_NHR	0x00010000  /* Not hard reset */
     80 #define HID0_ICE	0x00008000  /* Enable i-cache */
     81 #define HID0_DCE	0x00004000  /* Enable d-cache */
     82 #define HID0_ILOCK	0x00002000  /* i-cache lock */
     83 #define HID0_DLOCK	0x00001000  /* d-cache lock */
     84 #define HID0_ICFI	0x00000800  /* i-cache flash invalidate */
     85 #define HID0_DCFI	0x00000400  /* d-cache flash invalidate */
     86 #define HID0_SPD	0x00000200  /* Disable speculative cache access */
     87 #define HID0_IFEM	0x00000100  /* Enable M-bit for I-fetch */
     88 #define HID0_XBSEN	0x00000100  /* Extended BAT block size enable (7455+) */
     89 #define HID0_SGE	0x00000080  /* Enable store gathering */
     90 #define HID0_DCFA	0x00000040  /* Data cache flush assist */
     91 #define HID0_BTIC	0x00000020  /* Enable BTIC */
     92 #define HID0_LRSTK	0x00000010  /* Link register stack enable (7450) */
     93 #define HID0_ABE	0x00000008  /* Enable address broadcast */
     94 #define HID0_FOLD	0x00000008  /* Branch folding enable (7450) */
     95 #define HID0_BHT	0x00000004  /* Enable branch history table */
     96 #define HID0_BTCD	0x00000002  /* Branch target addr cache disable (604) */
     97 #define HID0_NOPTI	0x00000001  /* No-op the dcbt(st) */
     98 
     99 #define HID0_BITMASK "\020" \
    100     "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \
    101     "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \
    102     "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \
    103     "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI"
    104 
    105 #define HID0_7450_BITMASK "\020" \
    106     "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \
    107     "\030HIGH_BAT_EN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \
    108     "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \
    109     "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI"
    110 
    111 #define HID0_970_BITMASK "\020" \
    112     "\040EMCP"
    113 
    114 #define HID0_970_BITMASK_U "\020" \
    115     "\040ONEPPC\037DOSNGL\036ISYNCSC\035SERGP\034res\033res\032res\031DEEPNAP" \
    116     "\030DOZE\027NAP\026res\025DPM\024res\023TG\022HNGDIS\021NHR" \
    117     "\020INORDER\017res\016TBCTRL\015EXTBEN\014res\013res\012CIABREN\011HDICEEN" \
    118     "\001ENATTN"
    119 /*
    120  *  HID0 bit definitions per CPU model
    121  *
    122  * bit	603	604	750	7400	7410	7450
    123  *   0	EMCP	EMCP	EMCP	EMCP	EMCP	-
    124  *   1	-	ECP	DBP	-	-	-
    125  *   2	EBA	EBA	EBA	EBA	EDA	-
    126  *   3	EBD	EBD	EBD	EBD	EBD	-
    127  *   4	SBCLK	-	BCLK	BCKL	BCLK	-
    128  *   5	EICE	-	-	-	-	TBEN
    129  *   6	ECLK	-	ECLK	ECLK	ECLK	-
    130  *   7	PAR	PAR	PAR	PAR	PAR	STEN
    131  *   8	DOZE	-	DOZE	DOZE	DOZE	HIGH_BAT_EN
    132  *   9	NAP	-	NAP	NAP	NAP	NAP
    133  *  10	SLEEP	-	SLEEP	SLEEP	SLEEP	SLEEP
    134  *  11	DPM	-	DPM	DPM	DPM	DPM
    135  *  12	RISEG	-	-	RISEG	-	-
    136  *  13	-	-	-	EIEC	EIEC	BHTCLR
    137  *  14	-	-	-	-	-	XAEN
    138  *  15	-	NHR	NHR	NHR	NHR	NHR
    139  *  16	ICE	ICE	ICE	ICE	ICE	ICE
    140  *  17	DCE	DCE	DCE	DCE	DCE	DCE
    141  *  18	ILOCK	ILOCK	ILOCK	ILOCK	ILOCK	ILOCK
    142  *  19	DLOCK	DLOCK	DLOCK	DLOCK	DLOCK	DLOCK
    143  *  20	ICFI	ICFI	ICFI	ICFI	ICFI	ICFI
    144  *  21	DCFI	DCFI	DCFI	DCFI	DCFI	DCFI
    145  *  22	-	-	SPD	SPD	SPG	SPD
    146  *  23	-	-	IFEM	IFTT	IFTT	XBSEN
    147  *  24	-	SIE	SGE	SGE	SGE	SGE
    148  *  25	-	-	DCFA	DCFA	DCFA	-
    149  *  26	-	-	BTIC	BTIC	BTIC	BTIC
    150  *  27	FBIOB	-	-	-	-	LRSTK
    151  *  28	-	-	ABE	-	-	FOLD
    152  *  29	-	BHT	BHT	BHT	BHT	BHT
    153  *  30	-	BTCD	-	NOPDST	NOPDST	NOPDST
    154  *  31	NOOPTI	-	NOOPTI	NOPTI	NOPTI	NOPTI
    155  *
    156  *  604: ECP = Enable cache parity checking
    157  *  604: SIE = Serial instruction execution disable
    158  *  604: BTCD = Branch target address cache disable
    159  * 7450: TBEN = Time Base Enable
    160  * 7450: STEN = Software table lookup enable
    161  * 7450: BHTCLR = Branch history clear
    162  * 7450: LRSTK = Link Register Stack Enable
    163  * 7450: FOLD = Branch folding enable
    164  */
    165 
    166 #define	HID1_EMCP	0x80000000	/* Machine Check Signal Enable */
    167 #define	HID1_EBA	0x20000000	/* Enable/Disable 60x/MPX Bus Address
    168 					   Parity Checking */
    169 #define	HID1_EBD	0x10000000	/* Enable/Disable 60x/MPX Bus Data
    170 					   Parity Checking */
    171 #define	HID1_BCLK	0x08000000	/* CLK_OUT */
    172 #define	HID1_ECLK	0x02000000	/* CLK_OUT */
    173 #define	HID1_PAR	0x01000000	/* Disable Precharge for ... */
    174 #define	HID1_DFS4	0x00800000	/* Dynamic Freq Switch / 4 (7448) */
    175 #define	HID1_DFS2	0x00400000	/* Dynamic Freq Switch / 2 (7447A) */
    176 #define	HID1_SYNCBE	0x00000800	/* Enable sync/eieio broadcast */
    177 #define	HID1_ABE	0x00000400	/* Enable address broadcast */
    178 
    179 /* PPC970 HID4 */
    180 #define HID4_RMLR0	0x0000000000000020	/* real mode limit bit 0 */
    181 #define HID4_RMLR1	0x4000000000000000	/* real mode limit bit 1 */
    182 #define HID4_RMLR2	0x2000000000000000	/* real mode limit bit 2 */
    183 /*
    184  * real mode limit bits 012
    185  * 011 - 64MB
    186  * 111 - 128MB
    187  * 100 - 256MB
    188  * x10 - 1GB
    189  * x01 - 16GB
    190  * 000 - 256GB
    191  */
    192 
    193 #endif /* _POWERPC_OEA_HID_H_ */
    194