pio.h revision 1.8 1 1.8 rin /* $NetBSD: pio.h,v 1.8 2020/02/20 05:10:01 rin Exp $ */
2 1.1 briggs /* $OpenBSD: pio.h,v 1.1 1997/10/13 10:53:47 pefo Exp $ */
3 1.1 briggs
4 1.1 briggs /*
5 1.1 briggs * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA.
6 1.1 briggs *
7 1.1 briggs * Redistribution and use in source and binary forms, with or without
8 1.1 briggs * modification, are permitted provided that the following conditions
9 1.1 briggs * are met:
10 1.1 briggs * 1. Redistributions of source code must retain the above copyright
11 1.1 briggs * notice, this list of conditions and the following disclaimer.
12 1.1 briggs * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 briggs * notice, this list of conditions and the following disclaimer in the
14 1.1 briggs * documentation and/or other materials provided with the distribution.
15 1.1 briggs * 3. All advertising materials mentioning features or use of this software
16 1.1 briggs * must display the following acknowledgement:
17 1.1 briggs * This product includes software developed under OpenBSD by
18 1.1 briggs * Per Fogelstrom Opsycon AB for RTMX Inc, North Carolina, USA.
19 1.1 briggs * 4. The name of the author may not be used to endorse or promote products
20 1.1 briggs * derived from this software without specific prior written permission.
21 1.1 briggs *
22 1.1 briggs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
23 1.1 briggs * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 1.1 briggs * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 briggs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
26 1.1 briggs * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 briggs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 briggs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 briggs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 briggs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 briggs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 briggs * SUCH DAMAGE.
33 1.1 briggs *
34 1.1 briggs */
35 1.1 briggs
36 1.2 matt #ifndef _POWERPC_PIO_H_
37 1.2 matt #define _POWERPC_PIO_H_
38 1.1 briggs /*
39 1.1 briggs * I/O macros.
40 1.1 briggs */
41 1.1 briggs
42 1.8 rin #if defined(PPC_IBM4XX) && !defined(PPC_IBM440)
43 1.8 rin /* eieio is implemented as sync */
44 1.8 rin #define IO_BARRIER() __asm volatile("sync")
45 1.8 rin #else
46 1.8 rin #define IO_BARRIER() __asm volatile("eieio; sync")
47 1.8 rin #endif
48 1.8 rin
49 1.7 matt static __inline void __outb(volatile uint8_t *a, uint8_t v);
50 1.7 matt static __inline void __outw(volatile uint16_t *a, uint16_t v);
51 1.7 matt static __inline void __outl(volatile uint32_t *a, uint32_t v);
52 1.7 matt static __inline void __outwrb(volatile uint16_t *a, uint16_t v);
53 1.7 matt static __inline void __outlrb(volatile uint32_t *a, uint32_t v);
54 1.7 matt static __inline uint8_t __inb(volatile uint8_t *a);
55 1.7 matt static __inline uint16_t __inw(volatile uint16_t *a);
56 1.7 matt static __inline uint32_t __inl(volatile uint32_t *a);
57 1.7 matt static __inline uint16_t __inwrb(volatile uint16_t *a);
58 1.7 matt static __inline uint32_t __inlrb(volatile uint32_t *a);
59 1.7 matt static __inline void __outsb(volatile uint8_t *, const uint8_t *, size_t);
60 1.7 matt static __inline void __outsw(volatile uint16_t *, const uint16_t *, size_t);
61 1.7 matt static __inline void __outsl(volatile uint32_t *, const uint32_t *, size_t);
62 1.7 matt static __inline void __outswrb(volatile uint16_t *, const uint16_t *, size_t);
63 1.7 matt static __inline void __outslrb(volatile uint32_t *, const uint32_t *, size_t);
64 1.7 matt static __inline void __insb(volatile uint8_t *, uint8_t *, size_t);
65 1.7 matt static __inline void __insw(volatile uint16_t *, uint16_t *, size_t);
66 1.7 matt static __inline void __insl(volatile uint32_t *, uint32_t *, size_t);
67 1.7 matt static __inline void __inswrb(volatile uint16_t *, uint16_t *, size_t);
68 1.7 matt static __inline void __inslrb(volatile uint32_t *, uint32_t *, size_t);
69 1.7 matt
70 1.7 matt static __inline void
71 1.7 matt __outb(volatile uint8_t *a, uint8_t v)
72 1.1 briggs {
73 1.1 briggs *a = v;
74 1.8 rin IO_BARRIER();
75 1.1 briggs }
76 1.1 briggs
77 1.5 perry static __inline void
78 1.7 matt __outw(volatile uint16_t *a, uint16_t v)
79 1.1 briggs {
80 1.1 briggs *a = v;
81 1.8 rin IO_BARRIER();
82 1.1 briggs }
83 1.1 briggs
84 1.5 perry static __inline void
85 1.7 matt __outl(volatile uint32_t *a, uint32_t v)
86 1.1 briggs {
87 1.1 briggs *a = v;
88 1.8 rin IO_BARRIER();
89 1.1 briggs }
90 1.1 briggs
91 1.5 perry static __inline void
92 1.7 matt __outwrb(volatile uint16_t *a, uint16_t v)
93 1.1 briggs {
94 1.4 perry __asm volatile("sthbrx %0, 0, %1" :: "r"(v), "r"(a));
95 1.8 rin IO_BARRIER();
96 1.1 briggs }
97 1.1 briggs
98 1.5 perry static __inline void
99 1.7 matt __outlrb(volatile uint32_t *a, uint32_t v)
100 1.1 briggs {
101 1.4 perry __asm volatile("stwbrx %0, 0, %1" :: "r"(v), "r"(a));
102 1.8 rin IO_BARRIER();
103 1.1 briggs }
104 1.1 briggs
105 1.7 matt static __inline uint8_t
106 1.7 matt __inb(volatile uint8_t *a)
107 1.1 briggs {
108 1.7 matt uint8_t _v_;
109 1.1 briggs
110 1.1 briggs _v_ = *a;
111 1.8 rin IO_BARRIER();
112 1.1 briggs return _v_;
113 1.1 briggs }
114 1.1 briggs
115 1.7 matt static __inline uint16_t
116 1.7 matt __inw(volatile uint16_t *a)
117 1.1 briggs {
118 1.7 matt uint16_t _v_;
119 1.1 briggs
120 1.1 briggs _v_ = *a;
121 1.8 rin IO_BARRIER();
122 1.1 briggs return _v_;
123 1.1 briggs }
124 1.1 briggs
125 1.7 matt static __inline uint32_t
126 1.7 matt __inl(volatile uint32_t *a)
127 1.1 briggs {
128 1.7 matt uint32_t _v_;
129 1.1 briggs
130 1.1 briggs _v_ = *a;
131 1.8 rin IO_BARRIER();
132 1.1 briggs return _v_;
133 1.1 briggs }
134 1.1 briggs
135 1.7 matt static __inline uint16_t
136 1.7 matt __inwrb(volatile uint16_t *a)
137 1.1 briggs {
138 1.7 matt uint16_t _v_;
139 1.1 briggs
140 1.4 perry __asm volatile("lhbrx %0, 0, %1" : "=r"(_v_) : "r"(a));
141 1.8 rin IO_BARRIER();
142 1.1 briggs return _v_;
143 1.1 briggs }
144 1.1 briggs
145 1.7 matt static __inline uint32_t
146 1.7 matt __inlrb(volatile uint32_t *a)
147 1.1 briggs {
148 1.7 matt uint32_t _v_;
149 1.1 briggs
150 1.4 perry __asm volatile("lwbrx %0, 0, %1" : "=r"(_v_) : "r"(a));
151 1.8 rin IO_BARRIER();
152 1.1 briggs return _v_;
153 1.1 briggs }
154 1.1 briggs
155 1.7 matt #define outb(a,v) (__outb((volatile uint8_t *)(a), v))
156 1.1 briggs #define out8(a,v) outb(a,v)
157 1.7 matt #define outw(a,v) (__outw((volatile uint16_t *)(a), v))
158 1.1 briggs #define out16(a,v) outw(a,v)
159 1.7 matt #define outl(a,v) (__outl((volatile uint32_t *)(a), v))
160 1.1 briggs #define out32(a,v) outl(a,v)
161 1.7 matt #define inb(a) (__inb((volatile uint8_t *)(a)))
162 1.1 briggs #define in8(a) inb(a)
163 1.7 matt #define inw(a) (__inw((volatile uint16_t *)(a)))
164 1.1 briggs #define in16(a) inw(a)
165 1.7 matt #define inl(a) (__inl((volatile uint32_t *)(a)))
166 1.1 briggs #define in32(a) inl(a)
167 1.1 briggs
168 1.1 briggs #define out8rb(a,v) outb(a,v)
169 1.7 matt #define outwrb(a,v) (__outwrb((volatile uint16_t *)(a), v))
170 1.1 briggs #define out16rb(a,v) outwrb(a,v)
171 1.7 matt #define outlrb(a,v) (__outlrb((volatile uint32_t *)(a), v))
172 1.1 briggs #define out32rb(a,v) outlrb(a,v)
173 1.1 briggs #define in8rb(a) inb(a)
174 1.7 matt #define inwrb(a) (__inwrb((volatile uint16_t *)(a)))
175 1.1 briggs #define in16rb(a) inwrb(a)
176 1.7 matt #define inlrb(a) (__inlrb((volatile uint32_t *)(a)))
177 1.1 briggs #define in32rb(a) inlrb(a)
178 1.1 briggs
179 1.1 briggs
180 1.5 perry static __inline void
181 1.7 matt __outsb(volatile uint8_t *a, const uint8_t *s, size_t c)
182 1.1 briggs {
183 1.1 briggs while (c--)
184 1.1 briggs *a = *s++;
185 1.8 rin IO_BARRIER();
186 1.1 briggs }
187 1.1 briggs
188 1.5 perry static __inline void
189 1.7 matt __outsw(volatile uint16_t *a, const uint16_t *s, size_t c)
190 1.1 briggs {
191 1.1 briggs while (c--)
192 1.1 briggs *a = *s++;
193 1.8 rin IO_BARRIER();
194 1.1 briggs }
195 1.1 briggs
196 1.5 perry static __inline void
197 1.7 matt __outsl(volatile uint32_t *a, const uint32_t *s, size_t c)
198 1.1 briggs {
199 1.1 briggs while (c--)
200 1.1 briggs *a = *s++;
201 1.8 rin IO_BARRIER();
202 1.1 briggs }
203 1.1 briggs
204 1.5 perry static __inline void
205 1.7 matt __outswrb(volatile uint16_t *a, const uint16_t *s, size_t c)
206 1.1 briggs {
207 1.1 briggs while (c--)
208 1.4 perry __asm volatile("sthbrx %0, 0, %1" :: "r"(*s++), "r"(a));
209 1.8 rin IO_BARRIER();
210 1.1 briggs }
211 1.1 briggs
212 1.5 perry static __inline void
213 1.7 matt __outslrb(volatile uint32_t *a, const uint32_t *s, size_t c)
214 1.1 briggs {
215 1.1 briggs while (c--)
216 1.4 perry __asm volatile("stwbrx %0, 0, %1" :: "r"(*s++), "r"(a));
217 1.8 rin IO_BARRIER();
218 1.1 briggs }
219 1.1 briggs
220 1.5 perry static __inline void
221 1.7 matt __insb(volatile uint8_t *a, uint8_t *d, size_t c)
222 1.1 briggs {
223 1.1 briggs while (c--)
224 1.1 briggs *d++ = *a;
225 1.8 rin IO_BARRIER();
226 1.1 briggs }
227 1.1 briggs
228 1.5 perry static __inline void
229 1.7 matt __insw(volatile uint16_t *a, uint16_t *d, size_t c)
230 1.1 briggs {
231 1.1 briggs while (c--)
232 1.1 briggs *d++ = *a;
233 1.8 rin IO_BARRIER();
234 1.1 briggs }
235 1.1 briggs
236 1.5 perry static __inline void
237 1.7 matt __insl(volatile uint32_t *a, uint32_t *d, size_t c)
238 1.1 briggs {
239 1.1 briggs while (c--)
240 1.1 briggs *d++ = *a;
241 1.8 rin IO_BARRIER();
242 1.1 briggs }
243 1.1 briggs
244 1.5 perry static __inline void
245 1.7 matt __inswrb(volatile uint16_t *a, uint16_t *d, size_t c)
246 1.1 briggs {
247 1.1 briggs while (c--)
248 1.4 perry __asm volatile("lhbrx %0, 0, %1" : "=r"(*d++) : "r"(a));
249 1.8 rin IO_BARRIER();
250 1.1 briggs }
251 1.1 briggs
252 1.5 perry static __inline void
253 1.7 matt __inslrb(volatile uint32_t *a, uint32_t *d, size_t c)
254 1.1 briggs {
255 1.1 briggs while (c--)
256 1.4 perry __asm volatile("lwbrx %0, 0, %1" : "=r"(*d++) : "r"(a));
257 1.8 rin IO_BARRIER();
258 1.1 briggs }
259 1.1 briggs
260 1.7 matt #define outsb(a,s,c) (__outsb((volatile uint8_t *)(a), s, c))
261 1.1 briggs #define outs8(a,s,c) outsb(a,s,c)
262 1.7 matt #define outsw(a,s,c) (__outsw((volatile uint16_t *)(a), s, c))
263 1.1 briggs #define outs16(a,s,c) outsw(a,s,c)
264 1.7 matt #define outsl(a,s,c) (__outsl((volatile uint32_t *)(a), s, c))
265 1.1 briggs #define outs32(a,s,c) outsl(a,s,c)
266 1.7 matt #define insb(a,d,c) (__insb((volatile uint8_t *)(a), d, c))
267 1.1 briggs #define ins8(a,d,c) insb(a,d,c)
268 1.7 matt #define insw(a,d,c) (__insw((volatile uint16_t *)(a), d, c))
269 1.1 briggs #define ins16(a,d,c) insw(a,d,c)
270 1.7 matt #define insl(a,d,c) (__insl((volatile uint32_t *)(a), d, c))
271 1.1 briggs #define ins32(a,d,c) insl(a,d,c)
272 1.1 briggs
273 1.1 briggs #define outs8rb(a,s,c) outsb(a,s,c)
274 1.7 matt #define outswrb(a,s,c) (__outswrb((volatile uint16_t *)(a), s, c))
275 1.1 briggs #define outs16rb(a,s,c) outswrb(a,s,c)
276 1.7 matt #define outslrb(a,s,c) (__outslrb((volatile uint32_t *)(a), s, c))
277 1.1 briggs #define outs32rb(a,s,c) outslrb(a,s,c)
278 1.1 briggs #define ins8rb(a,d,c) insb(a,d,c)
279 1.7 matt #define inswrb(a,d,c) (__inswrb((volatile uint16_t *)(a), d, c))
280 1.1 briggs #define ins16rb(a,d,c) inswrb(a,d,c)
281 1.7 matt #define inslrb(a,d,c) (__inslrb((volatile uint32_t *)(a), d, c))
282 1.1 briggs #define ins32rb(a,d,c) inslrb(a,d,c)
283 1.1 briggs
284 1.8 rin #undef IO_BARRIER
285 1.8 rin
286 1.2 matt #endif /*_POWERPC_PIO_H_*/
287