altivec.c revision 1.5
1 /* $NetBSD: altivec.c,v 1.5 2003/07/15 02:54:45 lukem Exp $ */ 2 3 /* 4 * Copyright (C) 1996 Wolfgang Solfrank. 5 * Copyright (C) 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: altivec.c,v 1.5 2003/07/15 02:54:45 lukem Exp $"); 36 37 #include "opt_multiprocessor.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/sa.h> 42 #include <sys/systm.h> 43 #include <sys/user.h> 44 #include <sys/malloc.h> 45 #include <sys/pool.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <powerpc/altivec.h> 50 #include <powerpc/spr.h> 51 #include <powerpc/psl.h> 52 53 void 54 enable_vec() 55 { 56 struct cpu_info *ci = curcpu(); 57 struct lwp *l = curlwp; 58 struct pcb *pcb = &l->l_addr->u_pcb; 59 struct trapframe *tf = trapframe(l); 60 struct vreg *vr = &pcb->pcb_vr; 61 register_t msr; 62 63 KASSERT(pcb->pcb_veccpu == NULL); 64 65 pcb->pcb_flags |= PCB_ALTIVEC; 66 67 /* 68 * Enable AltiVec temporarily (and disable interrupts). 69 */ 70 msr = mfmsr(); 71 mtmsr((msr & ~PSL_EE) | PSL_VEC); 72 __asm __volatile ("isync"); 73 if (ci->ci_veclwp) { 74 save_vec_cpu(); 75 } 76 KASSERT(curcpu()->ci_veclwp == NULL); 77 78 /* 79 * Restore VSCR by first loading it into a vector and then into VSCR. 80 * (this needs to done before loading the user's vector registers 81 * since we need to use a scratch vector register) 82 */ 83 __asm __volatile("vxor %2,%2,%2; lvewx %2,%0,%1; mtvscr %2" \ 84 :: "b"(vr), "r"(offsetof(struct vreg, vscr)), "n"(0)); 85 86 /* 87 * VRSAVE will be restored when trap frame returns 88 */ 89 tf->tf_xtra[TF_VRSAVE] = vr->vrsave; 90 91 #define LVX(n,vr) __asm /*__volatile*/("lvx %2,%0,%1" \ 92 :: "b"(vr), "r"(offsetof(struct vreg, vreg[n])), "n"(n)); 93 94 /* 95 * Load all 32 vector registers 96 */ 97 LVX( 0,vr); LVX( 1,vr); LVX( 2,vr); LVX( 3,vr); 98 LVX( 4,vr); LVX( 5,vr); LVX( 6,vr); LVX( 7,vr); 99 LVX( 8,vr); LVX( 9,vr); LVX(10,vr); LVX(11,vr); 100 LVX(12,vr); LVX(13,vr); LVX(14,vr); LVX(15,vr); 101 102 LVX(16,vr); LVX(17,vr); LVX(18,vr); LVX(19,vr); 103 LVX(20,vr); LVX(21,vr); LVX(22,vr); LVX(23,vr); 104 LVX(24,vr); LVX(25,vr); LVX(26,vr); LVX(27,vr); 105 LVX(28,vr); LVX(29,vr); LVX(30,vr); LVX(31,vr); 106 __asm __volatile ("isync"); 107 108 /* 109 * Enable AltiVec when we return to user-mode. 110 * Record the new ownership of the AltiVec unit. 111 */ 112 tf->srr1 |= PSL_VEC; 113 curcpu()->ci_veclwp = l; 114 pcb->pcb_veccpu = curcpu(); 115 __asm __volatile ("sync"); 116 117 /* 118 * Restore MSR (turn off AltiVec) 119 */ 120 mtmsr(msr); 121 } 122 123 void 124 save_vec_cpu(void) 125 { 126 struct cpu_info *ci = curcpu(); 127 struct lwp *l; 128 struct pcb *pcb; 129 struct vreg *vr; 130 struct trapframe *tf; 131 register_t msr; 132 133 /* 134 * Turn on AltiVEC, turn off interrupts. 135 */ 136 msr = mfmsr(); 137 mtmsr((msr & ~PSL_EE) | PSL_VEC); 138 __asm __volatile ("isync"); 139 l = ci->ci_veclwp; 140 if (l == NULL) { 141 goto out; 142 } 143 pcb = &l->l_addr->u_pcb; 144 vr = &pcb->pcb_vr; 145 tf = trapframe(l); 146 147 #define STVX(n,vr) __asm /*__volatile*/("stvx %2,%0,%1" \ 148 :: "b"(vr), "r"(offsetof(struct vreg, vreg[n])), "n"(n)); 149 150 /* 151 * Save the vector registers. 152 */ 153 STVX( 0,vr); STVX( 1,vr); STVX( 2,vr); STVX( 3,vr); 154 STVX( 4,vr); STVX( 5,vr); STVX( 6,vr); STVX( 7,vr); 155 STVX( 8,vr); STVX( 9,vr); STVX(10,vr); STVX(11,vr); 156 STVX(12,vr); STVX(13,vr); STVX(14,vr); STVX(15,vr); 157 158 STVX(16,vr); STVX(17,vr); STVX(18,vr); STVX(19,vr); 159 STVX(20,vr); STVX(21,vr); STVX(22,vr); STVX(23,vr); 160 STVX(24,vr); STVX(25,vr); STVX(26,vr); STVX(27,vr); 161 STVX(28,vr); STVX(29,vr); STVX(30,vr); STVX(31,vr); 162 163 /* 164 * Save VSCR (this needs to be done after save the vector registers 165 * since we need to use one as scratch). 166 */ 167 __asm __volatile("mfvscr %2; stvewx %2,%0,%1" \ 168 :: "b"(vr), "r"(offsetof(struct vreg, vscr)), "n"(0)); 169 170 /* 171 * Save VRSAVE 172 */ 173 vr->vrsave = tf->tf_xtra[TF_VRSAVE]; 174 175 /* 176 * Note that we aren't using any CPU resources and stop any 177 * data streams. 178 */ 179 tf->srr1 &= ~PSL_VEC; 180 pcb->pcb_veccpu = NULL; 181 ci->ci_veclwp = NULL; 182 __asm __volatile ("dssall; sync"); 183 184 out: 185 186 /* 187 * Restore MSR (turn off AltiVec) 188 */ 189 mtmsr(msr); 190 } 191 192 /* 193 * Save a process's AltiVEC state to its PCB. The state may be in any CPU. 194 * The process must either be curproc or traced by curproc (and stopped). 195 * (The point being that the process must not run on another CPU during 196 * this function). 197 */ 198 void 199 save_vec_lwp(l) 200 struct lwp *l; 201 { 202 struct pcb *pcb = &l->l_addr->u_pcb; 203 struct cpu_info *ci = curcpu(); 204 205 /* 206 * If it's already in the PCB, there's nothing to do. 207 */ 208 209 if (pcb->pcb_veccpu == NULL) { 210 return; 211 } 212 213 /* 214 * If the state is in the current CPU, just flush the current CPU's 215 * state. 216 */ 217 218 if (l == ci->ci_veclwp) { 219 save_vec_cpu(); 220 return; 221 } 222 223 #ifdef MULTIPROCESSOR 224 225 /* 226 * It must be on another CPU, flush it from there. 227 */ 228 229 mp_save_vec_lwp(l); 230 #endif 231 } 232 233 #define ZERO_VEC 19 234 235 void 236 vzeropage(paddr_t pa) 237 { 238 const paddr_t ea = pa + PAGE_SIZE; 239 uint32_t vec[7], *vp = (void *) roundup((uintptr_t) vec, 16); 240 register_t omsr, msr; 241 242 __asm __volatile("mfmsr %0" : "=r"(omsr) :); 243 244 /* 245 * Turn on AltiVec, turn off interrupts. 246 */ 247 msr = (omsr & ~PSL_EE) | PSL_VEC; 248 __asm __volatile("sync; mtmsr %0; isync" :: "r"(msr)); 249 250 /* 251 * Save the VEC register we are going to use before we disable 252 * relocation. 253 */ 254 __asm("stvx %1,0,%0" :: "r"(vp), "n"(ZERO_VEC)); 255 __asm("vxor %0,%0,%0" :: "n"(ZERO_VEC)); 256 257 /* 258 * Turn off data relocation (DMMU off). 259 */ 260 msr &= ~PSL_DR; 261 __asm __volatile("sync; mtmsr %0; isync" :: "r"(msr)); 262 263 /* 264 * Zero the page using a single cache line. 265 */ 266 do { 267 __asm("stvx %2,%0,%1" :: "b"(pa), "r"( 0), "n"(ZERO_VEC)); 268 __asm("stvxl %2,%0,%1" :: "b"(pa), "r"(16), "n"(ZERO_VEC)); 269 __asm("stvx %2,%0,%1" :: "b"(pa), "r"(32), "n"(ZERO_VEC)); 270 __asm("stvxl %2,%0,%1" :: "b"(pa), "r"(48), "n"(ZERO_VEC)); 271 pa += 64; 272 } while (pa < ea); 273 274 /* 275 * Restore data relocation (DMMU on); 276 */ 277 msr |= PSL_DR; 278 __asm __volatile("sync; mtmsr %0; isync" :: "r"(msr)); 279 280 /* 281 * Restore VEC register (now that we can access the stack again). 282 */ 283 __asm("lvx %1,0,%0" :: "r"(vp), "n"(ZERO_VEC)); 284 285 /* 286 * Restore old MSR (AltiVec OFF). 287 */ 288 __asm __volatile("sync; mtmsr %0; isync" :: "r"(omsr)); 289 } 290 291 #define LO_VEC 16 292 #define HI_VEC 17 293 294 void 295 vcopypage(paddr_t dst, paddr_t src) 296 { 297 const paddr_t edst = dst + PAGE_SIZE; 298 uint32_t vec[11], *vp = (void *) roundup((uintptr_t) vec, 16); 299 register_t omsr, msr; 300 301 __asm __volatile("mfmsr %0" : "=r"(omsr) :); 302 303 /* 304 * Turn on AltiVec, turn off interrupts. 305 */ 306 msr = (omsr & ~PSL_EE) | PSL_VEC; 307 __asm __volatile("sync; mtmsr %0; isync" :: "r"(msr)); 308 309 /* 310 * Save the VEC registers we will be using before we disable 311 * relocation. 312 */ 313 __asm("stvx %2,%1,%0" :: "b"(vp), "r"( 0), "n"(LO_VEC)); 314 __asm("stvx %2,%1,%0" :: "b"(vp), "r"(16), "n"(HI_VEC)); 315 316 /* 317 * Turn off data relocation (DMMU off). 318 */ 319 msr &= ~PSL_DR; 320 __asm __volatile("sync; mtmsr %0; isync" :: "r"(msr)); 321 322 /* 323 * Copy the page using a single cache line. On most PPCs, two 324 * vector registers occupy one cache line. 325 */ 326 do { 327 __asm("lvx %2,%0,%1" :: "b"(src), "r"( 0), "n"(LO_VEC)); 328 __asm("stvx %2,%0,%1" :: "b"(dst), "r"( 0), "n"(LO_VEC)); 329 __asm("lvxl %2,%0,%1" :: "b"(src), "r"(16), "n"(HI_VEC)); 330 __asm("stvxl %2,%0,%1" :: "b"(dst), "r"(16), "n"(HI_VEC)); 331 src += 32; 332 dst += 32; 333 } while (dst < edst); 334 335 /* 336 * Restore data relocation (DMMU on); 337 */ 338 msr |= PSL_DR; 339 __asm __volatile("sync; mtmsr %0; isync" :: "r"(msr)); 340 341 /* 342 * Restore VEC registers (now that we can access the stack again). 343 */ 344 __asm("lvx %2,%1,%0" :: "b"(vp), "r"( 0), "n"(LO_VEC)); 345 __asm("lvx %2,%1,%0" :: "b"(vp), "r"(16), "n"(HI_VEC)); 346 347 /* 348 * Restore old MSR (AltiVec OFF). 349 */ 350 __asm __volatile("sync; mtmsr %0; isync" :: "r"(omsr)); 351 } 352
Indexes created Fri Sep 26 20:09:58 GMT 2025