cpu_subr.c revision 1.101
1 /* $NetBSD: cpu_subr.c,v 1.101 2019/09/20 21:27:29 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.101 2019/09/20 21:27:29 macallan Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 extern void init_scom_speedctl(void); 77 78 int cpu = -1; 79 int ncpus; 80 81 struct fmttab { 82 register_t fmt_mask; 83 register_t fmt_value; 84 const char *fmt_string; 85 }; 86 87 /* 88 * This should be one per CPU but since we only support it on 750 variants it 89 * doesn't really matter since none of them support SMP 90 */ 91 envsys_data_t sensor; 92 93 static const struct fmttab cpu_7450_l2cr_formats[] = { 94 { L2CR_L2E, 0, " disabled" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 96 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 97 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 98 { L2CR_L2E, ~0, " 256KB L2 cache" }, 99 { L2CR_L2PE, 0, " no parity" }, 100 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 101 { 0, 0, NULL } 102 }; 103 104 static const struct fmttab cpu_7448_l2cr_formats[] = { 105 { L2CR_L2E, 0, " disabled" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 107 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 108 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 109 { L2CR_L2E, ~0, " 1MB L2 cache" }, 110 { L2CR_L2PE, 0, " no parity" }, 111 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 112 { 0, 0, NULL } 113 }; 114 115 static const struct fmttab cpu_7457_l2cr_formats[] = { 116 { L2CR_L2E, 0, " disabled" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 118 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 119 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 120 { L2CR_L2E, ~0, " 512KB L2 cache" }, 121 { L2CR_L2PE, 0, " no parity" }, 122 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 123 { 0, 0, NULL } 124 }; 125 126 static const struct fmttab cpu_7450_l3cr_formats[] = { 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 128 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 129 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 130 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 131 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 133 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 134 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 135 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 136 { L3CR_L3SIZ, ~0, " L3 cache" }, 137 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 138 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 139 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 140 { L3CR_L3CLK, ~0, " at" }, 141 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 142 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 143 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 144 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 145 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 146 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 147 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 148 { L3CR_L3CLK, ~0, " ratio" }, 149 { 0, 0, NULL }, 150 }; 151 152 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 153 { L2CR_L2E, 0, " disabled" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 155 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 156 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 157 { 0, ~0, " 512KB" }, 158 { L2CR_L2WT, L2CR_L2WT, " WT" }, 159 { L2CR_L2WT, 0, " WB" }, 160 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 161 { 0, ~0, " L2 cache" }, 162 { 0, 0, NULL } 163 }; 164 165 static const struct fmttab cpu_l2cr_formats[] = { 166 { L2CR_L2E, 0, " disabled" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 168 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 169 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 170 { L2CR_L2PE, L2CR_L2PE, " parity" }, 171 { L2CR_L2PE, 0, " no-parity" }, 172 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 173 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 174 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 175 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 176 { L2CR_L2WT, L2CR_L2WT, " WT" }, 177 { L2CR_L2WT, 0, " WB" }, 178 { L2CR_L2E, ~0, " L2 cache" }, 179 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 180 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 181 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 182 { L2CR_L2CLK, ~0, " at" }, 183 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 184 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 185 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 186 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 187 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 188 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 189 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 190 { L2CR_L2CLK, ~0, " ratio" }, 191 { 0, 0, NULL } 192 }; 193 194 static void cpu_fmttab_print(const struct fmttab *, register_t); 195 196 struct cputab { 197 const char name[8]; 198 uint16_t version; 199 uint16_t revfmt; 200 }; 201 #define REVFMT_MAJMIN 1 /* %u.%u */ 202 #define REVFMT_HEX 2 /* 0x%04x */ 203 #define REVFMT_DEC 3 /* %u */ 204 static const struct cputab models[] = { 205 { "601", MPC601, REVFMT_DEC }, 206 { "602", MPC602, REVFMT_DEC }, 207 { "603", MPC603, REVFMT_MAJMIN }, 208 { "603e", MPC603e, REVFMT_MAJMIN }, 209 { "603ev", MPC603ev, REVFMT_MAJMIN }, 210 { "G2", MPCG2, REVFMT_MAJMIN }, 211 { "604", MPC604, REVFMT_MAJMIN }, 212 { "604e", MPC604e, REVFMT_MAJMIN }, 213 { "604ev", MPC604ev, REVFMT_MAJMIN }, 214 { "620", MPC620, REVFMT_HEX }, 215 { "750", MPC750, REVFMT_MAJMIN }, 216 { "750FX", IBM750FX, REVFMT_MAJMIN }, 217 { "750GX", IBM750GX, REVFMT_MAJMIN }, 218 { "7400", MPC7400, REVFMT_MAJMIN }, 219 { "7410", MPC7410, REVFMT_MAJMIN }, 220 { "7450", MPC7450, REVFMT_MAJMIN }, 221 { "7455", MPC7455, REVFMT_MAJMIN }, 222 { "7457", MPC7457, REVFMT_MAJMIN }, 223 { "7447A", MPC7447A, REVFMT_MAJMIN }, 224 { "7448", MPC7448, REVFMT_MAJMIN }, 225 { "8240", MPC8240, REVFMT_MAJMIN }, 226 { "8245", MPC8245, REVFMT_MAJMIN }, 227 { "970", IBM970, REVFMT_MAJMIN }, 228 { "970FX", IBM970FX, REVFMT_MAJMIN }, 229 { "970MP", IBM970MP, REVFMT_MAJMIN }, 230 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 231 { "", 0, REVFMT_HEX } 232 }; 233 234 #ifdef MULTIPROCESSOR 235 struct cpu_info cpu_info[CPU_MAXNUM] = { 236 [0] = { 237 .ci_curlwp = &lwp0, 238 }, 239 }; 240 volatile struct cpu_hatch_data *cpu_hatch_data; 241 volatile int cpu_hatch_stack; 242 #define HATCH_STACK_SIZE 0x1000 243 extern int ticks_per_intr; 244 #include <powerpc/oea/bat.h> 245 #include <powerpc/pic/picvar.h> 246 #include <powerpc/pic/ipivar.h> 247 extern struct bat battable[]; 248 #else 249 struct cpu_info cpu_info[1] = { 250 [0] = { 251 .ci_curlwp = &lwp0, 252 }, 253 }; 254 #endif /*MULTIPROCESSOR*/ 255 256 int cpu_altivec; 257 register_t cpu_psluserset; 258 register_t cpu_pslusermod; 259 register_t cpu_pslusermask = 0xffff; 260 261 /* This is to be called from locore.S, and nowhere else. */ 262 263 void 264 cpu_model_init(void) 265 { 266 u_int pvr, vers; 267 268 pvr = mfpvr(); 269 vers = pvr >> 16; 270 271 oeacpufeat = 0; 272 273 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 274 vers == IBMCELL || vers == IBMPOWER6P5) { 275 oeacpufeat |= OEACPU_64; 276 oeacpufeat |= OEACPU_64_BRIDGE; 277 oeacpufeat |= OEACPU_NOBAT; 278 279 } else if (vers == MPC601) { 280 oeacpufeat |= OEACPU_601; 281 282 } else if (MPC745X_P(vers)) { 283 register_t hid1 = mfspr(SPR_HID1); 284 285 if (vers != MPC7450) { 286 register_t hid0 = mfspr(SPR_HID0); 287 288 /* Enable more SPRG registers */ 289 oeacpufeat |= OEACPU_HIGHSPRG; 290 291 /* Enable more BAT registers */ 292 oeacpufeat |= OEACPU_HIGHBAT; 293 hid0 |= HID0_HIGH_BAT_EN; 294 295 /* Enable larger BAT registers */ 296 oeacpufeat |= OEACPU_XBSEN; 297 hid0 |= HID0_XBSEN; 298 299 mtspr(SPR_HID0, hid0); 300 __asm volatile("sync;isync"); 301 } 302 303 /* Enable address broadcasting for MP systems */ 304 hid1 |= HID1_SYNCBE | HID1_ABE; 305 306 mtspr(SPR_HID1, hid1); 307 __asm volatile("sync;isync"); 308 309 } else if (vers == IBM750FX || vers == IBM750GX) { 310 oeacpufeat |= OEACPU_HIGHBAT; 311 } 312 } 313 314 void 315 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 316 { 317 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 318 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 319 (data & fmt->fmt_mask) == fmt->fmt_value) 320 aprint_normal("%s", fmt->fmt_string); 321 } 322 } 323 324 void 325 cpu_idlespin(void) 326 { 327 register_t msr; 328 329 if (powersave <= 0) 330 return; 331 332 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 333 if (cpu_altivec) 334 __asm volatile("dssall"); 335 #endif 336 337 __asm volatile( 338 "sync;" 339 "mfmsr %0;" 340 "oris %0,%0,%1@h;" /* enter power saving mode */ 341 "mtmsr %0;" 342 "isync;" 343 : "=r"(msr) 344 : "J"(PSL_POW)); 345 } 346 347 void 348 cpu_probe_cache(void) 349 { 350 u_int assoc, pvr, vers; 351 352 pvr = mfpvr(); 353 vers = pvr >> 16; 354 355 356 /* Presently common across almost all implementations. */ 357 curcpu()->ci_ci.dcache_line_size = 32; 358 curcpu()->ci_ci.icache_line_size = 32; 359 360 361 switch (vers) { 362 #define K *1024 363 case IBM750FX: 364 case IBM750GX: 365 case MPC601: 366 case MPC750: 367 case MPC7400: 368 case MPC7447A: 369 case MPC7448: 370 case MPC7450: 371 case MPC7455: 372 case MPC7457: 373 curcpu()->ci_ci.dcache_size = 32 K; 374 curcpu()->ci_ci.icache_size = 32 K; 375 assoc = 8; 376 break; 377 case MPC603: 378 curcpu()->ci_ci.dcache_size = 8 K; 379 curcpu()->ci_ci.icache_size = 8 K; 380 assoc = 2; 381 break; 382 case MPC603e: 383 case MPC603ev: 384 case MPC604: 385 case MPC8240: 386 case MPC8245: 387 case MPCG2: 388 curcpu()->ci_ci.dcache_size = 16 K; 389 curcpu()->ci_ci.icache_size = 16 K; 390 assoc = 4; 391 break; 392 case MPC604e: 393 case MPC604ev: 394 curcpu()->ci_ci.dcache_size = 32 K; 395 curcpu()->ci_ci.icache_size = 32 K; 396 assoc = 4; 397 break; 398 case IBMPOWER3II: 399 curcpu()->ci_ci.dcache_size = 64 K; 400 curcpu()->ci_ci.icache_size = 32 K; 401 curcpu()->ci_ci.dcache_line_size = 128; 402 curcpu()->ci_ci.icache_line_size = 128; 403 assoc = 128; /* not a typo */ 404 break; 405 case IBM970: 406 case IBM970FX: 407 case IBM970MP: 408 curcpu()->ci_ci.dcache_size = 32 K; 409 curcpu()->ci_ci.icache_size = 64 K; 410 curcpu()->ci_ci.dcache_line_size = 128; 411 curcpu()->ci_ci.icache_line_size = 128; 412 assoc = 2; 413 break; 414 415 default: 416 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 417 curcpu()->ci_ci.icache_size = PAGE_SIZE; 418 assoc = 1; 419 #undef K 420 } 421 422 /* 423 * Possibly recolor. 424 */ 425 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 426 } 427 428 struct cpu_info * 429 cpu_attach_common(device_t self, int id) 430 { 431 struct cpu_info *ci; 432 u_int pvr, vers; 433 434 ci = &cpu_info[id]; 435 #ifndef MULTIPROCESSOR 436 /* 437 * If this isn't the primary CPU, print an error message 438 * and just bail out. 439 */ 440 if (id != 0) { 441 aprint_naive("\n"); 442 aprint_normal(": ID %d\n", id); 443 aprint_normal_dev(self, 444 "processor off-line; " 445 "multiprocessor support not present in kernel\n"); 446 return (NULL); 447 } 448 #endif 449 450 ci->ci_cpuid = id; 451 ci->ci_idepth = -1; 452 ci->ci_dev = self; 453 ci->ci_idlespin = cpu_idlespin; 454 455 pvr = mfpvr(); 456 vers = (pvr >> 16) & 0xffff; 457 458 switch (id) { 459 case 0: 460 /* load my cpu_number to PIR */ 461 switch (vers) { 462 case MPC601: 463 case MPC604: 464 case MPC604e: 465 case MPC604ev: 466 case MPC7400: 467 case MPC7410: 468 case MPC7447A: 469 case MPC7448: 470 case MPC7450: 471 case MPC7455: 472 case MPC7457: 473 mtspr(SPR_PIR, id); 474 } 475 cpu_setup(self, ci); 476 break; 477 default: 478 aprint_naive("\n"); 479 if (id >= CPU_MAXNUM) { 480 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 481 panic("cpuattach"); 482 } 483 #ifndef MULTIPROCESSOR 484 aprint_normal(" not configured\n"); 485 return NULL; 486 #else 487 mi_cpu_attach(ci); 488 break; 489 #endif 490 } 491 return (ci); 492 } 493 494 void 495 cpu_setup(device_t self, struct cpu_info *ci) 496 { 497 u_int pvr, vers; 498 const char * const xname = device_xname(self); 499 const char *bitmask; 500 char hidbuf[128]; 501 char model[80]; 502 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 503 char hidbuf_u[128]; 504 const char *bitmasku = NULL; 505 volatile uint64_t hid64_0, hid64_0_save; 506 #endif 507 #if !defined(_ARCH_PPC64) 508 register_t hid0 = 0, hid0_save = 0; 509 #endif 510 511 pvr = mfpvr(); 512 vers = (pvr >> 16) & 0xffff; 513 514 cpu_identify(model, sizeof(model)); 515 aprint_naive("\n"); 516 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 517 cpu_number() == 0 ? " (primary)" : ""); 518 519 /* set the cpu number */ 520 ci->ci_cpuid = cpu_number(); 521 #if defined(_ARCH_PPC64) 522 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 523 hid64_0_save = hid64_0; 524 #else 525 #if defined(PPC_OEA64_BRIDGE) 526 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 527 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 528 else 529 #endif 530 hid0_save = hid0 = mfspr(SPR_HID0); 531 #endif 532 533 534 cpu_probe_cache(); 535 536 /* 537 * Configure power-saving mode. 538 */ 539 switch (vers) { 540 #if !defined(_ARCH_PPC64) 541 case MPC604: 542 case MPC604e: 543 case MPC604ev: 544 /* 545 * Do not have HID0 support settings, but can support 546 * MSR[POW] off 547 */ 548 powersave = 1; 549 break; 550 551 case MPC603: 552 case MPC603e: 553 case MPC603ev: 554 case MPC7400: 555 case MPC7410: 556 case MPC8240: 557 case MPC8245: 558 case MPCG2: 559 /* Select DOZE mode. */ 560 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 561 hid0 |= HID0_DOZE | HID0_DPM; 562 powersave = 1; 563 break; 564 565 case MPC750: 566 case IBM750FX: 567 case IBM750GX: 568 /* Select NAP mode. */ 569 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 570 hid0 |= HID0_NAP | HID0_DPM; 571 powersave = 1; 572 break; 573 574 case MPC7447A: 575 case MPC7448: 576 case MPC7457: 577 case MPC7455: 578 case MPC7450: 579 /* Enable the 7450 branch caches */ 580 hid0 |= HID0_SGE | HID0_BTIC; 581 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 582 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 583 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 584 hid0 &= ~HID0_BTIC; 585 /* Select NAP mode. */ 586 hid0 &= ~HID0_SLEEP; 587 /* XXX my quicksilver hangs if nap is enabled */ 588 if (vers != MPC7450) { 589 hid0 |= HID0_NAP | HID0_DPM; 590 powersave = 1; 591 } 592 break; 593 #endif 594 595 case IBM970: 596 case IBM970FX: 597 case IBM970MP: 598 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 599 #if !defined(_ARCH_PPC64) 600 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 601 #endif 602 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 603 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 604 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 605 powersave = 1; 606 break; 607 #endif 608 case IBMPOWER3II: 609 default: 610 /* No power-saving mode is available. */ ; 611 } 612 613 #ifdef NAPMODE 614 switch (vers) { 615 case IBM750FX: 616 case IBM750GX: 617 case MPC750: 618 case MPC7400: 619 /* Select NAP mode. */ 620 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 621 hid0 |= HID0_NAP; 622 break; 623 } 624 #endif 625 626 switch (vers) { 627 case IBM750FX: 628 case IBM750GX: 629 case MPC750: 630 hid0 &= ~HID0_DBP; /* XXX correct? */ 631 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 632 break; 633 634 case MPC7400: 635 case MPC7410: 636 hid0 &= ~HID0_SPD; 637 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 638 hid0 |= HID0_EIEC; 639 break; 640 } 641 642 /* 643 * according to the 603e manual this is necessary for an external L2 644 * cache to work properly 645 */ 646 switch (vers) { 647 case MPC603e: 648 hid0 |= HID0_ABE; 649 } 650 651 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 652 #if defined(PPC_OEA64_BRIDGE) 653 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 654 #endif 655 if (hid64_0 != hid64_0_save) { 656 mtspr64(SPR_HID0, hid64_0); 657 } 658 #if defined(PPC_OEA64_BRIDGE) 659 } else { 660 #endif 661 #endif 662 663 #if !defined(_ARCH_PPC64) 664 if (hid0 != hid0_save) { 665 mtspr(SPR_HID0, hid0); 666 __asm volatile("sync;isync"); 667 } 668 #endif 669 #if defined(PPC_OEA64_BRIDGE) 670 } 671 #endif 672 673 switch (vers) { 674 case MPC601: 675 bitmask = HID0_601_BITMASK; 676 break; 677 case MPC7447A: 678 case MPC7448: 679 case MPC7450: 680 case MPC7455: 681 case MPC7457: 682 bitmask = HID0_7450_BITMASK; 683 break; 684 case IBM970: 685 case IBM970FX: 686 case IBM970MP: 687 bitmask = HID0_970_BITMASK; 688 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 689 bitmasku = HID0_970_BITMASK_U; 690 #endif 691 break; 692 default: 693 bitmask = HID0_BITMASK; 694 break; 695 } 696 697 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 698 if (bitmasku != NULL) { 699 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 700 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 701 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 702 hidbuf_u, hidbuf, powersave); 703 } else 704 #endif 705 { 706 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 707 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 708 hidbuf, powersave); 709 } 710 711 ci->ci_khz = 0; 712 713 /* 714 * Display speed and cache configuration. 715 */ 716 switch (vers) { 717 case MPC604: 718 case MPC604e: 719 case MPC604ev: 720 case MPC750: 721 case IBM750FX: 722 case IBM750GX: 723 case MPC7400: 724 case MPC7410: 725 case MPC7447A: 726 case MPC7448: 727 case MPC7450: 728 case MPC7455: 729 case MPC7457: 730 aprint_normal_dev(self, ""); 731 cpu_probe_speed(ci); 732 aprint_normal("%u.%02u MHz", 733 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 734 switch (vers) { 735 case MPC7450: /* 7441 does not have L3! */ 736 case MPC7455: /* 7445 does not have L3! */ 737 case MPC7457: /* 7447 does not have L3! */ 738 cpu_config_l3cr(vers); 739 break; 740 case IBM750FX: 741 case IBM750GX: 742 case MPC750: 743 case MPC7400: 744 case MPC7410: 745 case MPC7447A: 746 case MPC7448: 747 cpu_config_l2cr(pvr); 748 break; 749 default: 750 break; 751 } 752 aprint_normal("\n"); 753 break; 754 } 755 756 #if NSYSMON_ENVSYS > 0 757 /* 758 * Attach MPC750 temperature sensor to the envsys subsystem. 759 * XXX the 74xx series also has this sensor, but it is not 760 * XXX supported by Motorola and may return values that are off by 761 * XXX 35-55 degrees C. 762 */ 763 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 764 cpu_tau_setup(ci); 765 #endif 766 767 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 768 if (vers == IBM970MP) 769 init_scom_speedctl(); 770 #endif 771 772 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 773 NULL, xname, "clock"); 774 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 775 NULL, xname, "traps"); 776 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 777 &ci->ci_ev_traps, xname, "kernel DSI traps"); 778 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 779 &ci->ci_ev_traps, xname, "user DSI traps"); 780 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 781 &ci->ci_ev_udsi, xname, "user DSI failures"); 782 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 783 &ci->ci_ev_traps, xname, "kernel ISI traps"); 784 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 785 &ci->ci_ev_traps, xname, "user ISI traps"); 786 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 787 &ci->ci_ev_isi, xname, "user ISI failures"); 788 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 789 &ci->ci_ev_traps, xname, "system call traps"); 790 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 791 &ci->ci_ev_traps, xname, "PGM traps"); 792 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 793 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 794 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 795 &ci->ci_ev_fpu, xname, "FPU context switches"); 796 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 797 &ci->ci_ev_traps, xname, "user alignment traps"); 798 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 799 &ci->ci_ev_ali, xname, "user alignment traps"); 800 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 801 &ci->ci_ev_umchk, xname, "user MCHK failures"); 802 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 803 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 804 #ifdef ALTIVEC 805 if (cpu_altivec) { 806 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 807 &ci->ci_ev_vec, xname, "AltiVec context switches"); 808 } 809 #endif 810 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 811 NULL, xname, "IPIs"); 812 } 813 814 /* 815 * According to a document labeled "PVR Register Settings": 816 ** For integrated microprocessors the PVR register inside the device 817 ** will identify the version of the microprocessor core. You must also 818 ** read the Device ID, PCI register 02, to identify the part and the 819 ** Revision ID, PCI register 08, to identify the revision of the 820 ** integrated microprocessor. 821 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 822 */ 823 824 void 825 cpu_identify(char *str, size_t len) 826 { 827 u_int pvr, major, minor; 828 uint16_t vers, rev, revfmt; 829 const struct cputab *cp; 830 size_t n; 831 832 pvr = mfpvr(); 833 vers = pvr >> 16; 834 rev = pvr; 835 836 switch (vers) { 837 case MPC7410: 838 minor = (pvr >> 0) & 0xff; 839 major = minor <= 4 ? 1 : 2; 840 break; 841 case MPCG2: /*XXX see note above */ 842 major = (pvr >> 4) & 0xf; 843 minor = (pvr >> 0) & 0xf; 844 break; 845 default: 846 major = (pvr >> 8) & 0xf; 847 minor = (pvr >> 0) & 0xf; 848 } 849 850 for (cp = models; cp->name[0] != '\0'; cp++) { 851 if (cp->version == vers) 852 break; 853 } 854 855 if (cpu == -1) 856 cpu = vers; 857 858 revfmt = cp->revfmt; 859 if (rev == MPC750 && pvr == 15) { 860 revfmt = REVFMT_HEX; 861 } 862 863 if (cp->name[0] != '\0') { 864 n = snprintf(str, len, "%s (Revision ", cp->name); 865 } else { 866 n = snprintf(str, len, "Version %#x (Revision ", vers); 867 } 868 if (len > n) { 869 switch (revfmt) { 870 case REVFMT_MAJMIN: 871 snprintf(str + n, len - n, "%u.%u)", major, minor); 872 break; 873 case REVFMT_HEX: 874 snprintf(str + n, len - n, "0x%04x)", rev); 875 break; 876 case REVFMT_DEC: 877 snprintf(str + n, len - n, "%u)", rev); 878 break; 879 } 880 } 881 } 882 883 #ifdef L2CR_CONFIG 884 u_int l2cr_config = L2CR_CONFIG; 885 #else 886 u_int l2cr_config = 0; 887 #endif 888 889 #ifdef L3CR_CONFIG 890 u_int l3cr_config = L3CR_CONFIG; 891 #else 892 u_int l3cr_config = 0; 893 #endif 894 895 void 896 cpu_enable_l2cr(register_t l2cr) 897 { 898 register_t msr, x; 899 uint16_t vers; 900 901 vers = mfpvr() >> 16; 902 903 /* Disable interrupts and set the cache config bits. */ 904 msr = mfmsr(); 905 mtmsr(msr & ~PSL_EE); 906 #ifdef ALTIVEC 907 if (cpu_altivec) 908 __asm volatile("dssall"); 909 #endif 910 __asm volatile("sync"); 911 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 912 __asm volatile("sync"); 913 914 /* Wait for L2 clock to be stable (640 L2 clocks). */ 915 delay(100); 916 917 /* Invalidate all L2 contents. */ 918 if (MPC745X_P(vers)) { 919 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 920 do { 921 x = mfspr(SPR_L2CR); 922 } while (x & L2CR_L2I); 923 } else { 924 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 925 do { 926 x = mfspr(SPR_L2CR); 927 } while (x & L2CR_L2IP); 928 } 929 /* Enable L2 cache. */ 930 l2cr |= L2CR_L2E; 931 mtspr(SPR_L2CR, l2cr); 932 mtmsr(msr); 933 } 934 935 void 936 cpu_enable_l3cr(register_t l3cr) 937 { 938 register_t x; 939 940 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 941 942 /* 943 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 944 * L3CLKEN. (also mask off reserved bits in case they were included 945 * in L3CR_CONFIG) 946 */ 947 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 948 mtspr(SPR_L3CR, l3cr); 949 950 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 951 l3cr |= 0x04000000; 952 mtspr(SPR_L3CR, l3cr); 953 954 /* 3: Set L3CLKEN to 1*/ 955 l3cr |= L3CR_L3CLKEN; 956 mtspr(SPR_L3CR, l3cr); 957 958 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 959 __asm volatile("dssall;sync"); 960 /* L3 cache is already disabled, no need to clear L3E */ 961 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 962 do { 963 x = mfspr(SPR_L3CR); 964 } while (x & L3CR_L3I); 965 966 /* 6: Clear L3CLKEN to 0 */ 967 l3cr &= ~L3CR_L3CLKEN; 968 mtspr(SPR_L3CR, l3cr); 969 970 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 971 __asm volatile("sync"); 972 delay(100); 973 974 /* 8: Set L3E and L3CLKEN */ 975 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 976 mtspr(SPR_L3CR, l3cr); 977 978 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 979 __asm volatile("sync"); 980 delay(100); 981 } 982 983 void 984 cpu_config_l2cr(int pvr) 985 { 986 register_t l2cr; 987 u_int vers = (pvr >> 16) & 0xffff; 988 989 l2cr = mfspr(SPR_L2CR); 990 991 /* 992 * For MP systems, the firmware may only configure the L2 cache 993 * on the first CPU. In this case, assume that the other CPUs 994 * should use the same value for L2CR. 995 */ 996 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 997 l2cr_config = l2cr; 998 } 999 1000 /* 1001 * Configure L2 cache if not enabled. 1002 */ 1003 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1004 cpu_enable_l2cr(l2cr_config); 1005 l2cr = mfspr(SPR_L2CR); 1006 } 1007 1008 if ((l2cr & L2CR_L2E) == 0) { 1009 aprint_normal(" L2 cache present but not enabled "); 1010 return; 1011 } 1012 aprint_normal(","); 1013 1014 switch (vers) { 1015 case IBM750FX: 1016 case IBM750GX: 1017 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1018 break; 1019 case MPC750: 1020 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1021 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 1022 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1023 else 1024 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1025 break; 1026 case MPC7447A: 1027 case MPC7457: 1028 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1029 return; 1030 case MPC7448: 1031 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1032 return; 1033 case MPC7450: 1034 case MPC7455: 1035 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1036 break; 1037 default: 1038 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1039 break; 1040 } 1041 } 1042 1043 void 1044 cpu_config_l3cr(int vers) 1045 { 1046 register_t l2cr; 1047 register_t l3cr; 1048 1049 l2cr = mfspr(SPR_L2CR); 1050 1051 /* 1052 * For MP systems, the firmware may only configure the L2 cache 1053 * on the first CPU. In this case, assume that the other CPUs 1054 * should use the same value for L2CR. 1055 */ 1056 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1057 l2cr_config = l2cr; 1058 } 1059 1060 /* 1061 * Configure L2 cache if not enabled. 1062 */ 1063 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1064 cpu_enable_l2cr(l2cr_config); 1065 l2cr = mfspr(SPR_L2CR); 1066 } 1067 1068 aprint_normal(","); 1069 switch (vers) { 1070 case MPC7447A: 1071 case MPC7457: 1072 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1073 return; 1074 case MPC7448: 1075 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1076 return; 1077 default: 1078 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1079 break; 1080 } 1081 1082 l3cr = mfspr(SPR_L3CR); 1083 1084 /* 1085 * For MP systems, the firmware may only configure the L3 cache 1086 * on the first CPU. In this case, assume that the other CPUs 1087 * should use the same value for L3CR. 1088 */ 1089 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1090 l3cr_config = l3cr; 1091 } 1092 1093 /* 1094 * Configure L3 cache if not enabled. 1095 */ 1096 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1097 cpu_enable_l3cr(l3cr_config); 1098 l3cr = mfspr(SPR_L3CR); 1099 } 1100 1101 if (l3cr & L3CR_L3E) { 1102 aprint_normal(","); 1103 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1104 } 1105 } 1106 1107 void 1108 cpu_probe_speed(struct cpu_info *ci) 1109 { 1110 uint64_t cps; 1111 1112 mtspr(SPR_MMCR0, MMCR0_FC); 1113 mtspr(SPR_PMC1, 0); 1114 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1115 delay(100000); 1116 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1117 1118 mtspr(SPR_MMCR0, MMCR0_FC); 1119 1120 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1121 } 1122 1123 /* 1124 * Read the Dynamic Frequency Switching state and return a divisor for 1125 * the maximum frequency. 1126 */ 1127 int 1128 cpu_get_dfs(void) 1129 { 1130 u_int pvr, vers; 1131 1132 pvr = mfpvr(); 1133 vers = pvr >> 16; 1134 1135 switch (vers) { 1136 case MPC7448: 1137 if (mfspr(SPR_HID1) & HID1_DFS4) 1138 return 4; 1139 /* FALLTHROUGH */ 1140 case MPC7447A: 1141 if (mfspr(SPR_HID1) & HID1_DFS2) 1142 return 2; 1143 } 1144 return 1; 1145 } 1146 1147 /* 1148 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1149 */ 1150 void 1151 cpu_set_dfs(int div) 1152 { 1153 u_int dfs_mask, pvr, vers; 1154 1155 pvr = mfpvr(); 1156 vers = pvr >> 16; 1157 dfs_mask = 0; 1158 1159 switch (vers) { 1160 case MPC7448: 1161 dfs_mask |= HID1_DFS4; 1162 /* FALLTHROUGH */ 1163 case MPC7447A: 1164 dfs_mask |= HID1_DFS2; 1165 break; 1166 default: 1167 printf("cpu_set_dfs: DFS not supported\n"); 1168 return; 1169 1170 } 1171 #ifdef MULTIPROCESSOR 1172 uint64_t where; 1173 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1174 xc_wait(where); 1175 #else 1176 cpu_set_dfs_xcall(&div, &dfs_mask); 1177 #endif 1178 } 1179 1180 static void 1181 cpu_set_dfs_xcall(void *arg1, void *arg2) 1182 { 1183 u_int dfs_mask, hid1, old_hid1; 1184 int *divisor, s; 1185 1186 divisor = arg1; 1187 dfs_mask = *(u_int *)arg2; 1188 1189 s = splhigh(); 1190 hid1 = old_hid1 = mfspr(SPR_HID1); 1191 1192 switch (*divisor) { 1193 case 1: 1194 hid1 &= ~dfs_mask; 1195 break; 1196 case 2: 1197 hid1 &= ~(dfs_mask & HID1_DFS4); 1198 hid1 |= dfs_mask & HID1_DFS2; 1199 break; 1200 case 4: 1201 hid1 &= ~(dfs_mask & HID1_DFS2); 1202 hid1 |= dfs_mask & HID1_DFS4; 1203 break; 1204 } 1205 1206 if (hid1 != old_hid1) { 1207 __asm volatile("sync"); 1208 mtspr(SPR_HID1, hid1); 1209 __asm volatile("sync;isync"); 1210 } 1211 1212 splx(s); 1213 } 1214 1215 #if NSYSMON_ENVSYS > 0 1216 void 1217 cpu_tau_setup(struct cpu_info *ci) 1218 { 1219 struct sysmon_envsys *sme; 1220 int error, therm_delay; 1221 1222 mtspr(SPR_THRM1, SPR_THRM_VALID); 1223 mtspr(SPR_THRM2, 0); 1224 1225 /* 1226 * we need to figure out how much 20+us in units of CPU clock cycles 1227 * are 1228 */ 1229 1230 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1231 1232 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1233 1234 sme = sysmon_envsys_create(); 1235 1236 sensor.units = ENVSYS_STEMP; 1237 sensor.state = ENVSYS_SINVALID; 1238 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1239 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1240 sysmon_envsys_destroy(sme); 1241 return; 1242 } 1243 1244 sme->sme_name = device_xname(ci->ci_dev); 1245 sme->sme_cookie = ci; 1246 sme->sme_refresh = cpu_tau_refresh; 1247 1248 if ((error = sysmon_envsys_register(sme)) != 0) { 1249 aprint_error_dev(ci->ci_dev, 1250 " unable to register with sysmon (%d)\n", error); 1251 sysmon_envsys_destroy(sme); 1252 } 1253 } 1254 1255 /* Find the temperature of the CPU. */ 1256 void 1257 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1258 { 1259 int i, threshold, count; 1260 1261 threshold = 64; /* Half of the 7-bit sensor range */ 1262 1263 /* Successive-approximation code adapted from Motorola 1264 * application note AN1800/D, "Programming the Thermal Assist 1265 * Unit in the MPC750 Microprocessor". 1266 */ 1267 for (i = 5; i >= 0 ; i--) { 1268 mtspr(SPR_THRM1, 1269 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1270 count = 0; 1271 while ((count < 100000) && 1272 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1273 count++; 1274 delay(1); 1275 } 1276 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1277 /* The interrupt bit was set, meaning the 1278 * temperature was above the threshold 1279 */ 1280 threshold += 1 << i; 1281 } else { 1282 /* Temperature was below the threshold */ 1283 threshold -= 1 << i; 1284 } 1285 } 1286 threshold += 2; 1287 1288 /* Convert the temperature in degrees C to microkelvin */ 1289 edata->value_cur = (threshold * 1000000) + 273150000; 1290 edata->state = ENVSYS_SVALID; 1291 } 1292 #endif /* NSYSMON_ENVSYS > 0 */ 1293 1294 #ifdef MULTIPROCESSOR 1295 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1296 1297 int 1298 cpu_spinup(device_t self, struct cpu_info *ci) 1299 { 1300 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1301 struct pglist mlist; 1302 int i, error; 1303 char *hp; 1304 1305 KASSERT(ci != curcpu()); 1306 1307 /* Now allocate a hatch stack */ 1308 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1309 &mlist, 1, 1); 1310 if (error) { 1311 aprint_error(": unable to allocate hatch stack\n"); 1312 return -1; 1313 } 1314 1315 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1316 memset(hp, 0, HATCH_STACK_SIZE); 1317 1318 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1319 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1320 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1321 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1322 1323 cpu_hatch_data = h; 1324 h->hatch_running = 0; 1325 h->hatch_self = self; 1326 h->hatch_ci = ci; 1327 h->hatch_pir = ci->ci_cpuid; 1328 1329 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1330 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1331 1332 /* copy special registers */ 1333 1334 h->hatch_hid0 = mfspr(SPR_HID0); 1335 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1336 h->hatch_hid1 = mfspr(SPR_HID1); 1337 h->hatch_hid4 = mfspr(SPR_HID4); 1338 h->hatch_hid5 = mfspr(SPR_HID5); 1339 #endif 1340 1341 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1342 for (i = 0; i < 16; i++) { 1343 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1344 "r"(i << ADDR_SR_SHFT)); 1345 } 1346 if (oeacpufeat & OEACPU_64) 1347 h->hatch_asr = mfspr(SPR_ASR); 1348 else 1349 h->hatch_asr = 0; 1350 1351 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1352 /* copy the bat regs */ 1353 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1354 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1355 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1356 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1357 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1358 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1359 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1360 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1361 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1362 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1363 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1364 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1365 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1366 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1367 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1368 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1369 __asm volatile ("sync; isync"); 1370 } 1371 1372 if (md_setup_trampoline(h, ci) == -1) 1373 return -1; 1374 md_presync_timebase(h); 1375 md_start_timebase(h); 1376 1377 /* wait for secondary printf */ 1378 1379 delay(200000); 1380 1381 #ifdef CACHE_PROTO_MEI 1382 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1383 __asm volatile ("sync; isync"); 1384 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1385 __asm volatile ("sync; isync"); 1386 #endif 1387 int hatch_bail = 0; 1388 while ((h->hatch_running < 1) && (hatch_bail < 100000)) { 1389 delay(1); 1390 hatch_bail++; 1391 #ifdef CACHE_PROTO_MEI 1392 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1393 __asm volatile ("sync; isync"); 1394 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1395 __asm volatile ("sync; isync"); 1396 #endif 1397 } 1398 if (h->hatch_running < 1) { 1399 #ifdef CACHE_PROTO_MEI 1400 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1401 __asm volatile ("sync; isync"); 1402 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1403 __asm volatile ("sync; isync"); 1404 #endif 1405 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1406 ci->ci_cpuid, cpu_spinstart_ack); 1407 Debugger(); 1408 return -1; 1409 } 1410 1411 /* Register IPI Interrupt */ 1412 if (ipiops.ppc_establish_ipi) 1413 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1414 1415 return 0; 1416 } 1417 1418 static volatile int start_secondary_cpu; 1419 1420 register_t 1421 cpu_hatch(void) 1422 { 1423 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1424 struct cpu_info * const ci = h->hatch_ci; 1425 struct pcb *pcb; 1426 u_int msr; 1427 int i; 1428 1429 /* Initialize timebase. */ 1430 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1431 1432 /* 1433 * Set PIR (Processor Identification Register). i.e. whoami 1434 * Note that PIR is read-only on some CPU versions, so we write to it 1435 * only if it has a different value than we need. 1436 */ 1437 1438 msr = mfspr(SPR_PIR); 1439 if (msr != h->hatch_pir) 1440 mtspr(SPR_PIR, h->hatch_pir); 1441 1442 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1443 curlwp = ci->ci_curlwp; 1444 cpu_spinstart_ack = 0; 1445 1446 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1447 /* Initialize MMU. */ 1448 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1449 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1450 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1451 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1452 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1453 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1454 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1455 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1456 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1457 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1458 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1459 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1460 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1461 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1462 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1463 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1464 } 1465 1466 #ifdef PPC_OEA64_BRIDGE 1467 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1468 1469 mtspr64(SPR_HID0, h->hatch_hid0); 1470 mtspr64(SPR_HID1, h->hatch_hid1); 1471 mtspr64(SPR_HID4, h->hatch_hid4); 1472 mtspr64(SPR_HID5, h->hatch_hid5); 1473 mtspr64(SPR_HIOR, 0); 1474 } else 1475 #endif 1476 mtspr(SPR_HID0, h->hatch_hid0); 1477 1478 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1479 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1480 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1481 } 1482 1483 __asm volatile ("sync"); 1484 for (i = 0; i < 16; i++) 1485 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1486 __asm volatile ("sync; isync"); 1487 1488 if (oeacpufeat & OEACPU_64) 1489 mtspr(SPR_ASR, h->hatch_asr); 1490 1491 cpu_spinstart_ack = 1; 1492 __asm ("ptesync"); 1493 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1494 __asm volatile ("sync; isync"); 1495 1496 cpu_spinstart_ack = 5; 1497 for (i = 0; i < 16; i++) 1498 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1499 "r"(i << ADDR_SR_SHFT)); 1500 1501 /* Enable I/D address translations. */ 1502 msr = mfmsr(); 1503 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1504 mtmsr(msr); 1505 __asm volatile ("sync; isync"); 1506 cpu_spinstart_ack = 2; 1507 1508 md_sync_timebase(h); 1509 1510 cpu_setup(h->hatch_self, ci); 1511 1512 h->hatch_running = 1; 1513 __asm volatile ("sync; isync"); 1514 1515 while (start_secondary_cpu == 0) 1516 ; 1517 1518 __asm volatile ("sync; isync"); 1519 1520 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1521 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1522 1523 md_setup_interrupts(); 1524 1525 ci->ci_ipending = 0; 1526 ci->ci_cpl = 0; 1527 1528 mtmsr(mfmsr() | PSL_EE); 1529 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1530 return pcb->pcb_sp; 1531 } 1532 1533 void 1534 cpu_boot_secondary_processors(void) 1535 { 1536 start_secondary_cpu = 1; 1537 __asm volatile ("sync"); 1538 } 1539 1540 #endif /*MULTIPROCESSOR*/ 1541
Indexes created Thu Sep 25 16:09:42 GMT 2025