cpu_subr.c revision 1.103
1 /* $NetBSD: cpu_subr.c,v 1.103 2020/07/06 09:34:17 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.103 2020/07/06 09:34:17 rin Exp $"); 38 39 #include "sysmon_envsys.h" 40 41 #ifdef _KERNEL_OPT 42 #include "opt_altivec.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_ppccache.h" 45 #include "opt_ppcparam.h" 46 #endif 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/types.h> 52 #include <sys/lwp.h> 53 #include <sys/xcall.h> 54 55 #include <uvm/uvm.h> 56 57 #include <powerpc/pcb.h> 58 #include <powerpc/psl.h> 59 #include <powerpc/spr.h> 60 #include <powerpc/oea/hid.h> 61 #include <powerpc/oea/hid_601.h> 62 #include <powerpc/oea/spr.h> 63 #include <powerpc/oea/cpufeat.h> 64 65 #include <dev/sysmon/sysmonvar.h> 66 67 static void cpu_enable_l2cr(register_t); 68 static void cpu_enable_l3cr(register_t); 69 static void cpu_config_l2cr(int); 70 static void cpu_config_l3cr(int); 71 static void cpu_probe_speed(struct cpu_info *); 72 static void cpu_idlespin(void); 73 static void cpu_set_dfs_xcall(void *, void *); 74 #if NSYSMON_ENVSYS > 0 75 static void cpu_tau_setup(struct cpu_info *); 76 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 77 #endif 78 79 extern void init_scom_speedctl(void); 80 81 int cpu = -1; 82 int ncpus; 83 84 struct fmttab { 85 register_t fmt_mask; 86 register_t fmt_value; 87 const char *fmt_string; 88 }; 89 90 /* 91 * This should be one per CPU but since we only support it on 750 variants it 92 * doesn't really matter since none of them support SMP 93 */ 94 envsys_data_t sensor; 95 96 static const struct fmttab cpu_7450_l2cr_formats[] = { 97 { L2CR_L2E, 0, " disabled" }, 98 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 99 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 101 { L2CR_L2E, ~0, " 256KB L2 cache" }, 102 { L2CR_L2PE, 0, " no parity" }, 103 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 104 { 0, 0, NULL } 105 }; 106 107 static const struct fmttab cpu_7448_l2cr_formats[] = { 108 { L2CR_L2E, 0, " disabled" }, 109 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 110 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 111 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 112 { L2CR_L2E, ~0, " 1MB L2 cache" }, 113 { L2CR_L2PE, 0, " no parity" }, 114 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 115 { 0, 0, NULL } 116 }; 117 118 static const struct fmttab cpu_7457_l2cr_formats[] = { 119 { L2CR_L2E, 0, " disabled" }, 120 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 121 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 122 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 123 { L2CR_L2E, ~0, " 512KB L2 cache" }, 124 { L2CR_L2PE, 0, " no parity" }, 125 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 126 { 0, 0, NULL } 127 }; 128 129 static const struct fmttab cpu_7450_l3cr_formats[] = { 130 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 131 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 132 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 133 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 134 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 135 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 136 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 137 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 138 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 139 { L3CR_L3SIZ, ~0, " L3 cache" }, 140 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 141 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 142 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 143 { L3CR_L3CLK, ~0, " at" }, 144 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 145 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 146 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 147 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 148 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 149 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 150 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 151 { L3CR_L3CLK, ~0, " ratio" }, 152 { 0, 0, NULL }, 153 }; 154 155 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 156 { L2CR_L2E, 0, " disabled" }, 157 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 158 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 159 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 160 { 0, ~0, " 512KB" }, 161 { L2CR_L2WT, L2CR_L2WT, " WT" }, 162 { L2CR_L2WT, 0, " WB" }, 163 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 164 { 0, ~0, " L2 cache" }, 165 { 0, 0, NULL } 166 }; 167 168 static const struct fmttab cpu_l2cr_formats[] = { 169 { L2CR_L2E, 0, " disabled" }, 170 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 171 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 172 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 173 { L2CR_L2PE, L2CR_L2PE, " parity" }, 174 { L2CR_L2PE, 0, " no-parity" }, 175 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 176 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 177 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 178 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 179 { L2CR_L2WT, L2CR_L2WT, " WT" }, 180 { L2CR_L2WT, 0, " WB" }, 181 { L2CR_L2E, ~0, " L2 cache" }, 182 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 183 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 184 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 185 { L2CR_L2CLK, ~0, " at" }, 186 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 187 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 188 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 189 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 190 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 191 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 192 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 193 { L2CR_L2CLK, ~0, " ratio" }, 194 { 0, 0, NULL } 195 }; 196 197 static void cpu_fmttab_print(const struct fmttab *, register_t); 198 199 struct cputab { 200 const char name[8]; 201 uint16_t version; 202 uint16_t revfmt; 203 }; 204 #define REVFMT_MAJMIN 1 /* %u.%u */ 205 #define REVFMT_HEX 2 /* 0x%04x */ 206 #define REVFMT_DEC 3 /* %u */ 207 static const struct cputab models[] = { 208 { "601", MPC601, REVFMT_DEC }, 209 { "602", MPC602, REVFMT_DEC }, 210 { "603", MPC603, REVFMT_MAJMIN }, 211 { "603e", MPC603e, REVFMT_MAJMIN }, 212 { "603ev", MPC603ev, REVFMT_MAJMIN }, 213 { "G2", MPCG2, REVFMT_MAJMIN }, 214 { "604", MPC604, REVFMT_MAJMIN }, 215 { "604e", MPC604e, REVFMT_MAJMIN }, 216 { "604ev", MPC604ev, REVFMT_MAJMIN }, 217 { "620", MPC620, REVFMT_HEX }, 218 { "750", MPC750, REVFMT_MAJMIN }, 219 { "750FX", IBM750FX, REVFMT_MAJMIN }, 220 { "750GX", IBM750GX, REVFMT_MAJMIN }, 221 { "7400", MPC7400, REVFMT_MAJMIN }, 222 { "7410", MPC7410, REVFMT_MAJMIN }, 223 { "7450", MPC7450, REVFMT_MAJMIN }, 224 { "7455", MPC7455, REVFMT_MAJMIN }, 225 { "7457", MPC7457, REVFMT_MAJMIN }, 226 { "7447A", MPC7447A, REVFMT_MAJMIN }, 227 { "7448", MPC7448, REVFMT_MAJMIN }, 228 { "8240", MPC8240, REVFMT_MAJMIN }, 229 { "8245", MPC8245, REVFMT_MAJMIN }, 230 { "970", IBM970, REVFMT_MAJMIN }, 231 { "970FX", IBM970FX, REVFMT_MAJMIN }, 232 { "970MP", IBM970MP, REVFMT_MAJMIN }, 233 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 234 { "", 0, REVFMT_HEX } 235 }; 236 237 #ifdef MULTIPROCESSOR 238 struct cpu_info cpu_info[CPU_MAXNUM] = { 239 [0] = { 240 .ci_curlwp = &lwp0, 241 }, 242 }; 243 volatile struct cpu_hatch_data *cpu_hatch_data; 244 volatile int cpu_hatch_stack; 245 #define HATCH_STACK_SIZE 0x1000 246 extern int ticks_per_intr; 247 #include <powerpc/oea/bat.h> 248 #include <powerpc/pic/picvar.h> 249 #include <powerpc/pic/ipivar.h> 250 extern struct bat battable[]; 251 #else 252 struct cpu_info cpu_info[1] = { 253 [0] = { 254 .ci_curlwp = &lwp0, 255 }, 256 }; 257 #endif /*MULTIPROCESSOR*/ 258 259 int cpu_altivec; 260 register_t cpu_psluserset; 261 register_t cpu_pslusermod; 262 register_t cpu_pslusermask = 0xffff; 263 264 /* This is to be called from locore.S, and nowhere else. */ 265 266 void 267 cpu_model_init(void) 268 { 269 u_int pvr, vers; 270 271 pvr = mfpvr(); 272 vers = pvr >> 16; 273 274 oeacpufeat = 0; 275 276 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 277 vers == IBMCELL || vers == IBMPOWER6P5) { 278 oeacpufeat |= OEACPU_64; 279 oeacpufeat |= OEACPU_64_BRIDGE; 280 oeacpufeat |= OEACPU_NOBAT; 281 282 } else if (vers == MPC601) { 283 oeacpufeat |= OEACPU_601; 284 285 } else if (MPC745X_P(vers)) { 286 register_t hid1 = mfspr(SPR_HID1); 287 288 if (vers != MPC7450) { 289 register_t hid0 = mfspr(SPR_HID0); 290 291 /* Enable more SPRG registers */ 292 oeacpufeat |= OEACPU_HIGHSPRG; 293 294 /* Enable more BAT registers */ 295 oeacpufeat |= OEACPU_HIGHBAT; 296 hid0 |= HID0_HIGH_BAT_EN; 297 298 /* Enable larger BAT registers */ 299 oeacpufeat |= OEACPU_XBSEN; 300 hid0 |= HID0_XBSEN; 301 302 mtspr(SPR_HID0, hid0); 303 __asm volatile("sync;isync"); 304 } 305 306 /* Enable address broadcasting for MP systems */ 307 hid1 |= HID1_SYNCBE | HID1_ABE; 308 309 mtspr(SPR_HID1, hid1); 310 __asm volatile("sync;isync"); 311 312 } else if (vers == IBM750FX || vers == IBM750GX) { 313 oeacpufeat |= OEACPU_HIGHBAT; 314 } 315 } 316 317 void 318 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 319 { 320 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 321 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 322 (data & fmt->fmt_mask) == fmt->fmt_value) 323 aprint_normal("%s", fmt->fmt_string); 324 } 325 } 326 327 void 328 cpu_idlespin(void) 329 { 330 register_t msr; 331 332 if (powersave <= 0) 333 return; 334 335 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 336 if (cpu_altivec) 337 __asm volatile("dssall"); 338 #endif 339 340 __asm volatile( 341 "sync;" 342 "mfmsr %0;" 343 "oris %0,%0,%1@h;" /* enter power saving mode */ 344 "mtmsr %0;" 345 "isync;" 346 : "=r"(msr) 347 : "J"(PSL_POW)); 348 } 349 350 void 351 cpu_probe_cache(void) 352 { 353 u_int assoc, pvr, vers; 354 355 pvr = mfpvr(); 356 vers = pvr >> 16; 357 358 359 /* Presently common across almost all implementations. */ 360 curcpu()->ci_ci.dcache_line_size = 32; 361 curcpu()->ci_ci.icache_line_size = 32; 362 363 364 switch (vers) { 365 #define K *1024 366 case IBM750FX: 367 case IBM750GX: 368 case MPC601: 369 case MPC750: 370 case MPC7400: 371 case MPC7447A: 372 case MPC7448: 373 case MPC7450: 374 case MPC7455: 375 case MPC7457: 376 curcpu()->ci_ci.dcache_size = 32 K; 377 curcpu()->ci_ci.icache_size = 32 K; 378 assoc = 8; 379 break; 380 case MPC603: 381 curcpu()->ci_ci.dcache_size = 8 K; 382 curcpu()->ci_ci.icache_size = 8 K; 383 assoc = 2; 384 break; 385 case MPC603e: 386 case MPC603ev: 387 case MPC604: 388 case MPC8240: 389 case MPC8245: 390 case MPCG2: 391 curcpu()->ci_ci.dcache_size = 16 K; 392 curcpu()->ci_ci.icache_size = 16 K; 393 assoc = 4; 394 break; 395 case MPC604e: 396 case MPC604ev: 397 curcpu()->ci_ci.dcache_size = 32 K; 398 curcpu()->ci_ci.icache_size = 32 K; 399 assoc = 4; 400 break; 401 case IBMPOWER3II: 402 curcpu()->ci_ci.dcache_size = 64 K; 403 curcpu()->ci_ci.icache_size = 32 K; 404 curcpu()->ci_ci.dcache_line_size = 128; 405 curcpu()->ci_ci.icache_line_size = 128; 406 assoc = 128; /* not a typo */ 407 break; 408 case IBM970: 409 case IBM970FX: 410 case IBM970MP: 411 curcpu()->ci_ci.dcache_size = 32 K; 412 curcpu()->ci_ci.icache_size = 64 K; 413 curcpu()->ci_ci.dcache_line_size = 128; 414 curcpu()->ci_ci.icache_line_size = 128; 415 assoc = 2; 416 break; 417 418 default: 419 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 420 curcpu()->ci_ci.icache_size = PAGE_SIZE; 421 assoc = 1; 422 #undef K 423 } 424 425 /* 426 * Possibly recolor. 427 */ 428 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 429 } 430 431 struct cpu_info * 432 cpu_attach_common(device_t self, int id) 433 { 434 struct cpu_info *ci; 435 u_int pvr, vers; 436 437 ci = &cpu_info[id]; 438 #ifndef MULTIPROCESSOR 439 /* 440 * If this isn't the primary CPU, print an error message 441 * and just bail out. 442 */ 443 if (id != 0) { 444 aprint_naive("\n"); 445 aprint_normal(": ID %d\n", id); 446 aprint_normal_dev(self, 447 "processor off-line; " 448 "multiprocessor support not present in kernel\n"); 449 return (NULL); 450 } 451 #endif 452 453 ci->ci_cpuid = id; 454 ci->ci_idepth = -1; 455 ci->ci_dev = self; 456 ci->ci_idlespin = cpu_idlespin; 457 458 #ifdef MULTIPROCESSOR 459 /* Register IPI Interrupt */ 460 if ((ipiops.ppc_establish_ipi) && (id == 0)) 461 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 462 #endif 463 464 pvr = mfpvr(); 465 vers = (pvr >> 16) & 0xffff; 466 467 switch (id) { 468 case 0: 469 /* load my cpu_number to PIR */ 470 switch (vers) { 471 case MPC601: 472 case MPC604: 473 case MPC604e: 474 case MPC604ev: 475 case MPC7400: 476 case MPC7410: 477 case MPC7447A: 478 case MPC7448: 479 case MPC7450: 480 case MPC7455: 481 case MPC7457: 482 mtspr(SPR_PIR, id); 483 } 484 cpu_setup(self, ci); 485 break; 486 default: 487 aprint_naive("\n"); 488 if (id >= CPU_MAXNUM) { 489 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 490 panic("cpuattach"); 491 } 492 #ifndef MULTIPROCESSOR 493 aprint_normal(" not configured\n"); 494 return NULL; 495 #else 496 mi_cpu_attach(ci); 497 break; 498 #endif 499 } 500 return (ci); 501 } 502 503 void 504 cpu_setup(device_t self, struct cpu_info *ci) 505 { 506 u_int pvr, vers; 507 const char * const xname = device_xname(self); 508 const char *bitmask; 509 char hidbuf[128]; 510 char model[80]; 511 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 512 char hidbuf_u[128]; 513 const char *bitmasku = NULL; 514 volatile uint64_t hid64_0, hid64_0_save; 515 #endif 516 #if !defined(_ARCH_PPC64) 517 register_t hid0 = 0, hid0_save = 0; 518 #endif 519 520 pvr = mfpvr(); 521 vers = (pvr >> 16) & 0xffff; 522 523 cpu_identify(model, sizeof(model)); 524 aprint_naive("\n"); 525 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 526 cpu_number() == 0 ? " (primary)" : ""); 527 528 /* set the cpu number */ 529 ci->ci_cpuid = cpu_number(); 530 #if defined(_ARCH_PPC64) 531 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 532 hid64_0_save = hid64_0; 533 #else 534 #if defined(PPC_OEA64_BRIDGE) 535 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 536 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 537 else 538 #endif 539 hid0_save = hid0 = mfspr(SPR_HID0); 540 #endif 541 542 543 cpu_probe_cache(); 544 545 /* 546 * Configure power-saving mode. 547 */ 548 switch (vers) { 549 #if !defined(_ARCH_PPC64) 550 case MPC604: 551 case MPC604e: 552 case MPC604ev: 553 /* 554 * Do not have HID0 support settings, but can support 555 * MSR[POW] off 556 */ 557 powersave = 1; 558 break; 559 560 case MPC603: 561 case MPC603e: 562 case MPC603ev: 563 case MPC7400: 564 case MPC7410: 565 case MPC8240: 566 case MPC8245: 567 case MPCG2: 568 /* Select DOZE mode. */ 569 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 570 hid0 |= HID0_DOZE | HID0_DPM; 571 powersave = 1; 572 break; 573 574 case MPC750: 575 case IBM750FX: 576 case IBM750GX: 577 /* Select NAP mode. */ 578 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 579 hid0 |= HID0_NAP | HID0_DPM; 580 powersave = 1; 581 break; 582 583 case MPC7447A: 584 case MPC7448: 585 case MPC7457: 586 case MPC7455: 587 case MPC7450: 588 /* Enable the 7450 branch caches */ 589 hid0 |= HID0_SGE | HID0_BTIC; 590 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 591 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 592 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 593 hid0 &= ~HID0_BTIC; 594 /* Select NAP mode. */ 595 hid0 &= ~HID0_SLEEP; 596 /* XXX my quicksilver hangs if nap is enabled */ 597 if (vers != MPC7450) { 598 hid0 |= HID0_NAP | HID0_DPM; 599 powersave = 1; 600 } 601 break; 602 #endif 603 604 case IBM970: 605 case IBM970FX: 606 case IBM970MP: 607 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 608 #if !defined(_ARCH_PPC64) 609 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 610 #endif 611 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 612 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 613 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 614 powersave = 1; 615 break; 616 #endif 617 case IBMPOWER3II: 618 default: 619 /* No power-saving mode is available. */ ; 620 } 621 622 #ifdef NAPMODE 623 switch (vers) { 624 case IBM750FX: 625 case IBM750GX: 626 case MPC750: 627 case MPC7400: 628 /* Select NAP mode. */ 629 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 630 hid0 |= HID0_NAP; 631 break; 632 } 633 #endif 634 635 switch (vers) { 636 case IBM750FX: 637 case IBM750GX: 638 case MPC750: 639 hid0 &= ~HID0_DBP; /* XXX correct? */ 640 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 641 break; 642 643 case MPC7400: 644 case MPC7410: 645 hid0 &= ~HID0_SPD; 646 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 647 hid0 |= HID0_EIEC; 648 break; 649 } 650 651 /* 652 * according to the 603e manual this is necessary for an external L2 653 * cache to work properly 654 */ 655 switch (vers) { 656 case MPC603e: 657 hid0 |= HID0_ABE; 658 } 659 660 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 661 #if defined(PPC_OEA64_BRIDGE) 662 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 663 #endif 664 if (hid64_0 != hid64_0_save) { 665 mtspr64(SPR_HID0, hid64_0); 666 } 667 #if defined(PPC_OEA64_BRIDGE) 668 } else { 669 #endif 670 #endif 671 672 #if !defined(_ARCH_PPC64) 673 if (hid0 != hid0_save) { 674 mtspr(SPR_HID0, hid0); 675 __asm volatile("sync;isync"); 676 } 677 #endif 678 #if defined(PPC_OEA64_BRIDGE) 679 } 680 #endif 681 682 switch (vers) { 683 case MPC601: 684 bitmask = HID0_601_BITMASK; 685 break; 686 case MPC7447A: 687 case MPC7448: 688 case MPC7450: 689 case MPC7455: 690 case MPC7457: 691 bitmask = HID0_7450_BITMASK; 692 break; 693 case IBM970: 694 case IBM970FX: 695 case IBM970MP: 696 bitmask = HID0_970_BITMASK; 697 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 698 bitmasku = HID0_970_BITMASK_U; 699 #endif 700 break; 701 default: 702 bitmask = HID0_BITMASK; 703 break; 704 } 705 706 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 707 if (bitmasku != NULL) { 708 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 709 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 710 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 711 hidbuf_u, hidbuf, powersave); 712 } else 713 #endif 714 { 715 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 716 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 717 hidbuf, powersave); 718 } 719 720 ci->ci_khz = 0; 721 722 /* 723 * Display speed and cache configuration. 724 */ 725 switch (vers) { 726 case MPC604: 727 case MPC604e: 728 case MPC604ev: 729 case MPC750: 730 case IBM750FX: 731 case IBM750GX: 732 case MPC7400: 733 case MPC7410: 734 case MPC7447A: 735 case MPC7448: 736 case MPC7450: 737 case MPC7455: 738 case MPC7457: 739 aprint_normal_dev(self, ""); 740 cpu_probe_speed(ci); 741 aprint_normal("%u.%02u MHz", 742 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 743 switch (vers) { 744 case MPC7450: /* 7441 does not have L3! */ 745 case MPC7455: /* 7445 does not have L3! */ 746 case MPC7457: /* 7447 does not have L3! */ 747 cpu_config_l3cr(vers); 748 break; 749 case IBM750FX: 750 case IBM750GX: 751 case MPC750: 752 case MPC7400: 753 case MPC7410: 754 case MPC7447A: 755 case MPC7448: 756 cpu_config_l2cr(pvr); 757 break; 758 default: 759 break; 760 } 761 aprint_normal("\n"); 762 break; 763 } 764 765 #if NSYSMON_ENVSYS > 0 766 /* 767 * Attach MPC750 temperature sensor to the envsys subsystem. 768 * XXX the 74xx series also has this sensor, but it is not 769 * XXX supported by Motorola and may return values that are off by 770 * XXX 35-55 degrees C. 771 */ 772 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 773 cpu_tau_setup(ci); 774 #endif 775 776 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 777 if (vers == IBM970MP) 778 init_scom_speedctl(); 779 #endif 780 781 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 782 NULL, xname, "clock"); 783 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 784 NULL, xname, "traps"); 785 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 786 &ci->ci_ev_traps, xname, "kernel DSI traps"); 787 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 788 &ci->ci_ev_traps, xname, "user DSI traps"); 789 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 790 &ci->ci_ev_udsi, xname, "user DSI failures"); 791 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 792 &ci->ci_ev_traps, xname, "kernel ISI traps"); 793 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 794 &ci->ci_ev_traps, xname, "user ISI traps"); 795 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 796 &ci->ci_ev_isi, xname, "user ISI failures"); 797 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 798 &ci->ci_ev_traps, xname, "system call traps"); 799 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 800 &ci->ci_ev_traps, xname, "PGM traps"); 801 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 802 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 803 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 804 &ci->ci_ev_fpu, xname, "FPU context switches"); 805 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 806 &ci->ci_ev_traps, xname, "user alignment traps"); 807 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 808 &ci->ci_ev_ali, xname, "user alignment traps"); 809 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 810 &ci->ci_ev_umchk, xname, "user MCHK failures"); 811 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 812 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 813 #ifdef ALTIVEC 814 if (cpu_altivec) { 815 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 816 &ci->ci_ev_vec, xname, "AltiVec context switches"); 817 } 818 #endif 819 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 820 NULL, xname, "IPIs"); 821 } 822 823 /* 824 * According to a document labeled "PVR Register Settings": 825 ** For integrated microprocessors the PVR register inside the device 826 ** will identify the version of the microprocessor core. You must also 827 ** read the Device ID, PCI register 02, to identify the part and the 828 ** Revision ID, PCI register 08, to identify the revision of the 829 ** integrated microprocessor. 830 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 831 */ 832 833 void 834 cpu_identify(char *str, size_t len) 835 { 836 u_int pvr, major, minor; 837 uint16_t vers, rev, revfmt; 838 const struct cputab *cp; 839 size_t n; 840 841 pvr = mfpvr(); 842 vers = pvr >> 16; 843 rev = pvr; 844 845 switch (vers) { 846 case MPC7410: 847 minor = (pvr >> 0) & 0xff; 848 major = minor <= 4 ? 1 : 2; 849 break; 850 case MPCG2: /*XXX see note above */ 851 major = (pvr >> 4) & 0xf; 852 minor = (pvr >> 0) & 0xf; 853 break; 854 default: 855 major = (pvr >> 8) & 0xf; 856 minor = (pvr >> 0) & 0xf; 857 } 858 859 for (cp = models; cp->name[0] != '\0'; cp++) { 860 if (cp->version == vers) 861 break; 862 } 863 864 if (cpu == -1) 865 cpu = vers; 866 867 revfmt = cp->revfmt; 868 if (rev == MPC750 && pvr == 15) { 869 revfmt = REVFMT_HEX; 870 } 871 872 if (cp->name[0] != '\0') { 873 n = snprintf(str, len, "%s (Revision ", cp->name); 874 } else { 875 n = snprintf(str, len, "Version %#x (Revision ", vers); 876 } 877 if (len > n) { 878 switch (revfmt) { 879 case REVFMT_MAJMIN: 880 snprintf(str + n, len - n, "%u.%u)", major, minor); 881 break; 882 case REVFMT_HEX: 883 snprintf(str + n, len - n, "0x%04x)", rev); 884 break; 885 case REVFMT_DEC: 886 snprintf(str + n, len - n, "%u)", rev); 887 break; 888 } 889 } 890 } 891 892 #ifdef L2CR_CONFIG 893 u_int l2cr_config = L2CR_CONFIG; 894 #else 895 u_int l2cr_config = 0; 896 #endif 897 898 #ifdef L3CR_CONFIG 899 u_int l3cr_config = L3CR_CONFIG; 900 #else 901 u_int l3cr_config = 0; 902 #endif 903 904 void 905 cpu_enable_l2cr(register_t l2cr) 906 { 907 register_t msr, x; 908 uint16_t vers; 909 910 vers = mfpvr() >> 16; 911 912 /* Disable interrupts and set the cache config bits. */ 913 msr = mfmsr(); 914 mtmsr(msr & ~PSL_EE); 915 #ifdef ALTIVEC 916 if (cpu_altivec) 917 __asm volatile("dssall"); 918 #endif 919 __asm volatile("sync"); 920 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 921 __asm volatile("sync"); 922 923 /* Wait for L2 clock to be stable (640 L2 clocks). */ 924 delay(100); 925 926 /* Invalidate all L2 contents. */ 927 if (MPC745X_P(vers)) { 928 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 929 do { 930 x = mfspr(SPR_L2CR); 931 } while (x & L2CR_L2I); 932 } else { 933 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 934 do { 935 x = mfspr(SPR_L2CR); 936 } while (x & L2CR_L2IP); 937 } 938 /* Enable L2 cache. */ 939 l2cr |= L2CR_L2E; 940 mtspr(SPR_L2CR, l2cr); 941 mtmsr(msr); 942 } 943 944 void 945 cpu_enable_l3cr(register_t l3cr) 946 { 947 register_t x; 948 949 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 950 951 /* 952 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 953 * L3CLKEN. (also mask off reserved bits in case they were included 954 * in L3CR_CONFIG) 955 */ 956 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 957 mtspr(SPR_L3CR, l3cr); 958 959 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 960 l3cr |= 0x04000000; 961 mtspr(SPR_L3CR, l3cr); 962 963 /* 3: Set L3CLKEN to 1*/ 964 l3cr |= L3CR_L3CLKEN; 965 mtspr(SPR_L3CR, l3cr); 966 967 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 968 __asm volatile("dssall;sync"); 969 /* L3 cache is already disabled, no need to clear L3E */ 970 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 971 do { 972 x = mfspr(SPR_L3CR); 973 } while (x & L3CR_L3I); 974 975 /* 6: Clear L3CLKEN to 0 */ 976 l3cr &= ~L3CR_L3CLKEN; 977 mtspr(SPR_L3CR, l3cr); 978 979 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 980 __asm volatile("sync"); 981 delay(100); 982 983 /* 8: Set L3E and L3CLKEN */ 984 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 985 mtspr(SPR_L3CR, l3cr); 986 987 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 988 __asm volatile("sync"); 989 delay(100); 990 } 991 992 void 993 cpu_config_l2cr(int pvr) 994 { 995 register_t l2cr; 996 u_int vers = (pvr >> 16) & 0xffff; 997 998 l2cr = mfspr(SPR_L2CR); 999 1000 /* 1001 * For MP systems, the firmware may only configure the L2 cache 1002 * on the first CPU. In this case, assume that the other CPUs 1003 * should use the same value for L2CR. 1004 */ 1005 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1006 l2cr_config = l2cr; 1007 } 1008 1009 /* 1010 * Configure L2 cache if not enabled. 1011 */ 1012 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1013 cpu_enable_l2cr(l2cr_config); 1014 l2cr = mfspr(SPR_L2CR); 1015 } 1016 1017 if ((l2cr & L2CR_L2E) == 0) { 1018 aprint_normal(" L2 cache present but not enabled "); 1019 return; 1020 } 1021 aprint_normal(","); 1022 1023 switch (vers) { 1024 case IBM750FX: 1025 case IBM750GX: 1026 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1027 break; 1028 case MPC750: 1029 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1030 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 1031 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1032 else 1033 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1034 break; 1035 case MPC7447A: 1036 case MPC7457: 1037 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1038 return; 1039 case MPC7448: 1040 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1041 return; 1042 case MPC7450: 1043 case MPC7455: 1044 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1045 break; 1046 default: 1047 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1048 break; 1049 } 1050 } 1051 1052 void 1053 cpu_config_l3cr(int vers) 1054 { 1055 register_t l2cr; 1056 register_t l3cr; 1057 1058 l2cr = mfspr(SPR_L2CR); 1059 1060 /* 1061 * For MP systems, the firmware may only configure the L2 cache 1062 * on the first CPU. In this case, assume that the other CPUs 1063 * should use the same value for L2CR. 1064 */ 1065 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1066 l2cr_config = l2cr; 1067 } 1068 1069 /* 1070 * Configure L2 cache if not enabled. 1071 */ 1072 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1073 cpu_enable_l2cr(l2cr_config); 1074 l2cr = mfspr(SPR_L2CR); 1075 } 1076 1077 aprint_normal(","); 1078 switch (vers) { 1079 case MPC7447A: 1080 case MPC7457: 1081 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1082 return; 1083 case MPC7448: 1084 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1085 return; 1086 default: 1087 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1088 break; 1089 } 1090 1091 l3cr = mfspr(SPR_L3CR); 1092 1093 /* 1094 * For MP systems, the firmware may only configure the L3 cache 1095 * on the first CPU. In this case, assume that the other CPUs 1096 * should use the same value for L3CR. 1097 */ 1098 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1099 l3cr_config = l3cr; 1100 } 1101 1102 /* 1103 * Configure L3 cache if not enabled. 1104 */ 1105 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1106 cpu_enable_l3cr(l3cr_config); 1107 l3cr = mfspr(SPR_L3CR); 1108 } 1109 1110 if (l3cr & L3CR_L3E) { 1111 aprint_normal(","); 1112 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1113 } 1114 } 1115 1116 void 1117 cpu_probe_speed(struct cpu_info *ci) 1118 { 1119 uint64_t cps; 1120 1121 mtspr(SPR_MMCR0, MMCR0_FC); 1122 mtspr(SPR_PMC1, 0); 1123 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1124 delay(100000); 1125 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1126 1127 mtspr(SPR_MMCR0, MMCR0_FC); 1128 1129 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1130 } 1131 1132 /* 1133 * Read the Dynamic Frequency Switching state and return a divisor for 1134 * the maximum frequency. 1135 */ 1136 int 1137 cpu_get_dfs(void) 1138 { 1139 u_int pvr, vers; 1140 1141 pvr = mfpvr(); 1142 vers = pvr >> 16; 1143 1144 switch (vers) { 1145 case MPC7448: 1146 if (mfspr(SPR_HID1) & HID1_DFS4) 1147 return 4; 1148 /* FALLTHROUGH */ 1149 case MPC7447A: 1150 if (mfspr(SPR_HID1) & HID1_DFS2) 1151 return 2; 1152 } 1153 return 1; 1154 } 1155 1156 /* 1157 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1158 */ 1159 void 1160 cpu_set_dfs(int div) 1161 { 1162 u_int dfs_mask, pvr, vers; 1163 1164 pvr = mfpvr(); 1165 vers = pvr >> 16; 1166 dfs_mask = 0; 1167 1168 switch (vers) { 1169 case MPC7448: 1170 dfs_mask |= HID1_DFS4; 1171 /* FALLTHROUGH */ 1172 case MPC7447A: 1173 dfs_mask |= HID1_DFS2; 1174 break; 1175 default: 1176 printf("cpu_set_dfs: DFS not supported\n"); 1177 return; 1178 1179 } 1180 #ifdef MULTIPROCESSOR 1181 uint64_t where; 1182 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1183 xc_wait(where); 1184 #else 1185 cpu_set_dfs_xcall(&div, &dfs_mask); 1186 #endif 1187 } 1188 1189 static void 1190 cpu_set_dfs_xcall(void *arg1, void *arg2) 1191 { 1192 u_int dfs_mask, hid1, old_hid1; 1193 int *divisor, s; 1194 1195 divisor = arg1; 1196 dfs_mask = *(u_int *)arg2; 1197 1198 s = splhigh(); 1199 hid1 = old_hid1 = mfspr(SPR_HID1); 1200 1201 switch (*divisor) { 1202 case 1: 1203 hid1 &= ~dfs_mask; 1204 break; 1205 case 2: 1206 hid1 &= ~(dfs_mask & HID1_DFS4); 1207 hid1 |= dfs_mask & HID1_DFS2; 1208 break; 1209 case 4: 1210 hid1 &= ~(dfs_mask & HID1_DFS2); 1211 hid1 |= dfs_mask & HID1_DFS4; 1212 break; 1213 } 1214 1215 if (hid1 != old_hid1) { 1216 __asm volatile("sync"); 1217 mtspr(SPR_HID1, hid1); 1218 __asm volatile("sync;isync"); 1219 } 1220 1221 splx(s); 1222 } 1223 1224 #if NSYSMON_ENVSYS > 0 1225 void 1226 cpu_tau_setup(struct cpu_info *ci) 1227 { 1228 struct sysmon_envsys *sme; 1229 int error, therm_delay; 1230 1231 mtspr(SPR_THRM1, SPR_THRM_VALID); 1232 mtspr(SPR_THRM2, 0); 1233 1234 /* 1235 * we need to figure out how much 20+us in units of CPU clock cycles 1236 * are 1237 */ 1238 1239 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1240 1241 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1242 1243 sme = sysmon_envsys_create(); 1244 1245 sensor.units = ENVSYS_STEMP; 1246 sensor.state = ENVSYS_SINVALID; 1247 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1248 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1249 sysmon_envsys_destroy(sme); 1250 return; 1251 } 1252 1253 sme->sme_name = device_xname(ci->ci_dev); 1254 sme->sme_cookie = ci; 1255 sme->sme_refresh = cpu_tau_refresh; 1256 1257 if ((error = sysmon_envsys_register(sme)) != 0) { 1258 aprint_error_dev(ci->ci_dev, 1259 " unable to register with sysmon (%d)\n", error); 1260 sysmon_envsys_destroy(sme); 1261 } 1262 } 1263 1264 /* Find the temperature of the CPU. */ 1265 void 1266 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1267 { 1268 int i, threshold, count; 1269 1270 threshold = 64; /* Half of the 7-bit sensor range */ 1271 1272 /* Successive-approximation code adapted from Motorola 1273 * application note AN1800/D, "Programming the Thermal Assist 1274 * Unit in the MPC750 Microprocessor". 1275 */ 1276 for (i = 5; i >= 0 ; i--) { 1277 mtspr(SPR_THRM1, 1278 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1279 count = 0; 1280 while ((count < 100000) && 1281 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1282 count++; 1283 delay(1); 1284 } 1285 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1286 /* The interrupt bit was set, meaning the 1287 * temperature was above the threshold 1288 */ 1289 threshold += 1 << i; 1290 } else { 1291 /* Temperature was below the threshold */ 1292 threshold -= 1 << i; 1293 } 1294 } 1295 threshold += 2; 1296 1297 /* Convert the temperature in degrees C to microkelvin */ 1298 edata->value_cur = (threshold * 1000000) + 273150000; 1299 edata->state = ENVSYS_SVALID; 1300 } 1301 #endif /* NSYSMON_ENVSYS > 0 */ 1302 1303 #ifdef MULTIPROCESSOR 1304 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1305 1306 int 1307 cpu_spinup(device_t self, struct cpu_info *ci) 1308 { 1309 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1310 struct pglist mlist; 1311 int i, error; 1312 char *hp; 1313 1314 KASSERT(ci != curcpu()); 1315 1316 /* Now allocate a hatch stack */ 1317 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1318 &mlist, 1, 1); 1319 if (error) { 1320 aprint_error(": unable to allocate hatch stack\n"); 1321 return -1; 1322 } 1323 1324 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1325 memset(hp, 0, HATCH_STACK_SIZE); 1326 1327 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1328 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1329 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1330 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1331 1332 cpu_hatch_data = h; 1333 h->hatch_running = 0; 1334 h->hatch_self = self; 1335 h->hatch_ci = ci; 1336 h->hatch_pir = ci->ci_cpuid; 1337 1338 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1339 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1340 1341 /* copy special registers */ 1342 1343 h->hatch_hid0 = mfspr(SPR_HID0); 1344 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1345 h->hatch_hid1 = mfspr(SPR_HID1); 1346 h->hatch_hid4 = mfspr(SPR_HID4); 1347 h->hatch_hid5 = mfspr(SPR_HID5); 1348 #endif 1349 1350 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1351 for (i = 0; i < 16; i++) { 1352 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1353 "r"(i << ADDR_SR_SHFT)); 1354 } 1355 if (oeacpufeat & OEACPU_64) 1356 h->hatch_asr = mfspr(SPR_ASR); 1357 else 1358 h->hatch_asr = 0; 1359 1360 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1361 /* copy the bat regs */ 1362 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1363 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1364 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1365 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1366 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1367 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1368 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1369 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1370 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1371 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1372 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1373 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1374 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1375 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1376 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1377 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1378 __asm volatile ("sync; isync"); 1379 } 1380 1381 if (md_setup_trampoline(h, ci) == -1) 1382 return -1; 1383 md_presync_timebase(h); 1384 md_start_timebase(h); 1385 1386 /* wait for secondary printf */ 1387 1388 delay(200000); 1389 1390 #ifdef CACHE_PROTO_MEI 1391 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1392 __asm volatile ("sync; isync"); 1393 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1394 __asm volatile ("sync; isync"); 1395 #endif 1396 int hatch_bail = 0; 1397 while ((h->hatch_running < 1) && (hatch_bail < 100000)) { 1398 delay(1); 1399 hatch_bail++; 1400 #ifdef CACHE_PROTO_MEI 1401 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1402 __asm volatile ("sync; isync"); 1403 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1404 __asm volatile ("sync; isync"); 1405 #endif 1406 } 1407 if (h->hatch_running < 1) { 1408 #ifdef CACHE_PROTO_MEI 1409 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1410 __asm volatile ("sync; isync"); 1411 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1412 __asm volatile ("sync; isync"); 1413 #endif 1414 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1415 ci->ci_cpuid, cpu_spinstart_ack); 1416 Debugger(); 1417 return -1; 1418 } 1419 1420 return 0; 1421 } 1422 1423 static volatile int start_secondary_cpu; 1424 1425 register_t 1426 cpu_hatch(void) 1427 { 1428 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1429 struct cpu_info * const ci = h->hatch_ci; 1430 struct pcb *pcb; 1431 u_int msr; 1432 int i; 1433 1434 /* Initialize timebase. */ 1435 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1436 1437 /* 1438 * Set PIR (Processor Identification Register). i.e. whoami 1439 * Note that PIR is read-only on some CPU versions, so we write to it 1440 * only if it has a different value than we need. 1441 */ 1442 1443 msr = mfspr(SPR_PIR); 1444 if (msr != h->hatch_pir) 1445 mtspr(SPR_PIR, h->hatch_pir); 1446 1447 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1448 curlwp = ci->ci_curlwp; 1449 cpu_spinstart_ack = 0; 1450 1451 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1452 /* Initialize MMU. */ 1453 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1454 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1455 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1456 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1457 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1458 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1459 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1460 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1461 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1462 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1463 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1464 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1465 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1466 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1467 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1468 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1469 } 1470 1471 #ifdef PPC_OEA64_BRIDGE 1472 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1473 1474 mtspr64(SPR_HID0, h->hatch_hid0); 1475 mtspr64(SPR_HID1, h->hatch_hid1); 1476 mtspr64(SPR_HID4, h->hatch_hid4); 1477 mtspr64(SPR_HID5, h->hatch_hid5); 1478 mtspr64(SPR_HIOR, 0); 1479 } else 1480 #endif 1481 mtspr(SPR_HID0, h->hatch_hid0); 1482 1483 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1484 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1485 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1486 } 1487 1488 __asm volatile ("sync"); 1489 for (i = 0; i < 16; i++) 1490 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1491 __asm volatile ("sync; isync"); 1492 1493 if (oeacpufeat & OEACPU_64) 1494 mtspr(SPR_ASR, h->hatch_asr); 1495 1496 cpu_spinstart_ack = 1; 1497 __asm ("ptesync"); 1498 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1499 __asm volatile ("sync; isync"); 1500 1501 cpu_spinstart_ack = 5; 1502 for (i = 0; i < 16; i++) 1503 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1504 "r"(i << ADDR_SR_SHFT)); 1505 1506 /* Enable I/D address translations. */ 1507 msr = mfmsr(); 1508 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1509 mtmsr(msr); 1510 __asm volatile ("sync; isync"); 1511 cpu_spinstart_ack = 2; 1512 1513 md_sync_timebase(h); 1514 1515 cpu_setup(h->hatch_self, ci); 1516 1517 h->hatch_running = 1; 1518 __asm volatile ("sync; isync"); 1519 1520 while (start_secondary_cpu == 0) 1521 ; 1522 1523 __asm volatile ("sync; isync"); 1524 1525 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1526 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1527 1528 md_setup_interrupts(); 1529 1530 ci->ci_ipending = 0; 1531 ci->ci_cpl = 0; 1532 1533 mtmsr(mfmsr() | PSL_EE); 1534 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1535 return pcb->pcb_sp; 1536 } 1537 1538 void 1539 cpu_boot_secondary_processors(void) 1540 { 1541 start_secondary_cpu = 1; 1542 __asm volatile ("sync"); 1543 } 1544 1545 #endif /*MULTIPROCESSOR*/ 1546
Indexes created Tue Sep 23 02:09:52 GMT 2025