cpu_subr.c revision 1.19
1 /* $NetBSD: cpu_subr.c,v 1.19 2005/01/11 02:09:54 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.19 2005/01/11 02:09:54 chs Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_print_speed(void); 62 #if NSYSMON_ENVSYS > 0 63 static void cpu_tau_setup(struct cpu_info *); 64 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 65 struct envsys_tre_data *)); 66 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 67 struct envsys_basic_info *)); 68 #endif 69 70 int cpu; 71 int ncpus; 72 73 struct fmttab { 74 register_t fmt_mask; 75 register_t fmt_value; 76 const char *fmt_string; 77 }; 78 79 static const struct fmttab cpu_7450_l2cr_formats[] = { 80 { L2CR_L2E, 0, " disabled" }, 81 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 84 { L2CR_L2E, ~0, " 256KB L2 cache" }, 85 { 0 } 86 }; 87 88 static const struct fmttab cpu_7457_l2cr_formats[] = { 89 { L2CR_L2E, 0, " disabled" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 93 { L2CR_L2E, ~0, " 512KB L2 cache" }, 94 { 0 } 95 }; 96 97 static const struct fmttab cpu_7450_l3cr_formats[] = { 98 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 99 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 100 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 101 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 102 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 103 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 104 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 105 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 106 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 107 { L3CR_L3SIZ, ~0, " L3 cache" }, 108 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 109 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 110 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 111 { L3CR_L3CLK, ~0, " at" }, 112 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 113 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 114 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 115 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 116 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 117 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 118 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 119 { L3CR_L3CLK, ~0, " ratio" }, 120 { 0, 0 }, 121 }; 122 123 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 124 { L2CR_L2E, 0, " disabled" }, 125 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 126 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 127 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 128 { 0, ~0, " 512KB" }, 129 { L2CR_L2WT, L2CR_L2WT, " WT" }, 130 { L2CR_L2WT, 0, " WB" }, 131 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 132 { 0, ~0, " L2 cache" }, 133 { 0 } 134 }; 135 136 static const struct fmttab cpu_l2cr_formats[] = { 137 { L2CR_L2E, 0, " disabled" }, 138 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 139 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 140 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 141 { L2CR_L2PE, L2CR_L2PE, " parity" }, 142 { L2CR_L2PE, 0, " no-parity" }, 143 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 144 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 145 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 146 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 147 { L2CR_L2WT, L2CR_L2WT, " WT" }, 148 { L2CR_L2WT, 0, " WB" }, 149 { L2CR_L2E, ~0, " L2 cache" }, 150 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 151 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 152 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 153 { L2CR_L2CLK, ~0, " at" }, 154 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 155 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 156 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 157 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 158 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 159 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 160 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 161 { L2CR_L2CLK, ~0, " ratio" }, 162 { 0 } 163 }; 164 165 static void cpu_fmttab_print(const struct fmttab *, register_t); 166 167 struct cputab { 168 const char name[8]; 169 uint16_t version; 170 uint16_t revfmt; 171 }; 172 #define REVFMT_MAJMIN 1 /* %u.%u */ 173 #define REVFMT_HEX 2 /* 0x%04x */ 174 #define REVFMT_DEC 3 /* %u */ 175 static const struct cputab models[] = { 176 { "601", MPC601, REVFMT_DEC }, 177 { "602", MPC602, REVFMT_DEC }, 178 { "603", MPC603, REVFMT_MAJMIN }, 179 { "603e", MPC603e, REVFMT_MAJMIN }, 180 { "603ev", MPC603ev, REVFMT_MAJMIN }, 181 { "604", MPC604, REVFMT_MAJMIN }, 182 { "604e", MPC604e, REVFMT_MAJMIN }, 183 { "604ev", MPC604ev, REVFMT_MAJMIN }, 184 { "620", MPC620, REVFMT_HEX }, 185 { "750", MPC750, REVFMT_MAJMIN }, 186 { "750FX", IBM750FX, REVFMT_MAJMIN }, 187 { "7400", MPC7400, REVFMT_MAJMIN }, 188 { "7410", MPC7410, REVFMT_MAJMIN }, 189 { "7450", MPC7450, REVFMT_MAJMIN }, 190 { "7455", MPC7455, REVFMT_MAJMIN }, 191 { "7457", MPC7457, REVFMT_MAJMIN }, 192 { "8240", MPC8240, REVFMT_MAJMIN }, 193 { "", 0, REVFMT_HEX } 194 }; 195 196 197 #ifdef MULTIPROCESSOR 198 struct cpu_info cpu_info[CPU_MAXNUM]; 199 #else 200 struct cpu_info cpu_info[1]; 201 #endif 202 203 int cpu_altivec; 204 int cpu_psluserset, cpu_pslusermod; 205 char cpu_model[80]; 206 207 void 208 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 209 { 210 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 211 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 212 (data & fmt->fmt_mask) == fmt->fmt_value) 213 aprint_normal("%s", fmt->fmt_string); 214 } 215 } 216 217 void 218 cpu_probe_cache(void) 219 { 220 u_int assoc, pvr, vers; 221 222 pvr = mfpvr(); 223 vers = pvr >> 16; 224 225 switch (vers) { 226 #define K *1024 227 case IBM750FX: 228 case MPC601: 229 case MPC750: 230 case MPC7450: 231 case MPC7455: 232 case MPC7457: 233 curcpu()->ci_ci.dcache_size = 32 K; 234 curcpu()->ci_ci.icache_size = 32 K; 235 assoc = 8; 236 break; 237 case MPC603: 238 curcpu()->ci_ci.dcache_size = 8 K; 239 curcpu()->ci_ci.icache_size = 8 K; 240 assoc = 2; 241 break; 242 case MPC603e: 243 case MPC603ev: 244 case MPC604: 245 case MPC8240: 246 case MPC8245: 247 curcpu()->ci_ci.dcache_size = 16 K; 248 curcpu()->ci_ci.icache_size = 16 K; 249 assoc = 4; 250 break; 251 case MPC604e: 252 case MPC604ev: 253 curcpu()->ci_ci.dcache_size = 32 K; 254 curcpu()->ci_ci.icache_size = 32 K; 255 assoc = 4; 256 break; 257 default: 258 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 259 curcpu()->ci_ci.icache_size = PAGE_SIZE; 260 assoc = 1; 261 #undef K 262 } 263 264 /* Presently common across all implementations. */ 265 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 266 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 267 268 /* 269 * Possibly recolor. 270 */ 271 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 272 } 273 274 struct cpu_info * 275 cpu_attach_common(struct device *self, int id) 276 { 277 struct cpu_info *ci; 278 u_int pvr, vers; 279 280 ncpus++; 281 ci = &cpu_info[id]; 282 #ifndef MULTIPROCESSOR 283 /* 284 * If this isn't the primary CPU, print an error message 285 * and just bail out. 286 */ 287 if (id != 0) { 288 aprint_normal(": ID %d\n", id); 289 aprint_normal("%s: processor off-line; multiprocessor support " 290 "not present in kernel\n", self->dv_xname); 291 return (NULL); 292 } 293 #endif 294 295 ci->ci_cpuid = id; 296 ci->ci_intrdepth = -1; 297 ci->ci_dev = self; 298 299 pvr = mfpvr(); 300 vers = (pvr >> 16) & 0xffff; 301 302 switch (id) { 303 case 0: 304 /* load my cpu_number to PIR */ 305 switch (vers) { 306 case MPC601: 307 case MPC604: 308 case MPC604e: 309 case MPC604ev: 310 case MPC7400: 311 case MPC7410: 312 case MPC7450: 313 case MPC7455: 314 case MPC7457: 315 mtspr(SPR_PIR, id); 316 } 317 cpu_setup(self, ci); 318 break; 319 default: 320 if (id >= CPU_MAXNUM) { 321 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 322 panic("cpuattach"); 323 } 324 #ifndef MULTIPROCESSOR 325 aprint_normal(" not configured\n"); 326 return NULL; 327 #endif 328 } 329 return (ci); 330 } 331 332 void 333 cpu_setup(self, ci) 334 struct device *self; 335 struct cpu_info *ci; 336 { 337 u_int hid0, pvr, vers; 338 char *bitmask, hidbuf[128]; 339 char model[80]; 340 341 pvr = mfpvr(); 342 vers = (pvr >> 16) & 0xffff; 343 344 cpu_identify(model, sizeof(model)); 345 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 346 cpu_number() == 0 ? " (primary)" : ""); 347 348 hid0 = mfspr(SPR_HID0); 349 cpu_probe_cache(); 350 351 /* 352 * Configure power-saving mode. 353 */ 354 switch (vers) { 355 case MPC604: 356 case MPC604e: 357 case MPC604ev: 358 /* 359 * Do not have HID0 support settings, but can support 360 * MSR[POW] off 361 */ 362 powersave = 1; 363 break; 364 365 case MPC603: 366 case MPC603e: 367 case MPC603ev: 368 case MPC750: 369 case IBM750FX: 370 case MPC7400: 371 case MPC7410: 372 case MPC8240: 373 case MPC8245: 374 /* Select DOZE mode. */ 375 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 376 hid0 |= HID0_DOZE | HID0_DPM; 377 powersave = 1; 378 break; 379 380 case MPC7457: 381 case MPC7455: 382 case MPC7450: 383 /* Enable the 7450 branch caches */ 384 hid0 |= HID0_SGE | HID0_BTIC; 385 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 386 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 387 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 388 hid0 &= ~HID0_BTIC; 389 /* Select NAP mode. */ 390 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 391 hid0 |= HID0_NAP | HID0_DPM; 392 powersave = 1; 393 break; 394 395 default: 396 /* No power-saving mode is available. */ ; 397 } 398 399 #ifdef NAPMODE 400 switch (vers) { 401 case IBM750FX: 402 case MPC750: 403 case MPC7400: 404 /* Select NAP mode. */ 405 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 406 hid0 |= HID0_NAP; 407 break; 408 } 409 #endif 410 411 switch (vers) { 412 case IBM750FX: 413 case MPC750: 414 hid0 &= ~HID0_DBP; /* XXX correct? */ 415 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 416 break; 417 418 case MPC7400: 419 case MPC7410: 420 hid0 &= ~HID0_SPD; 421 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 422 hid0 |= HID0_EIEC; 423 break; 424 } 425 426 mtspr(SPR_HID0, hid0); 427 428 switch (vers) { 429 case MPC601: 430 bitmask = HID0_601_BITMASK; 431 break; 432 case MPC7450: 433 case MPC7455: 434 case MPC7457: 435 bitmask = HID0_7450_BITMASK; 436 break; 437 default: 438 bitmask = HID0_BITMASK; 439 break; 440 } 441 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 442 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 443 444 /* 445 * Display speed and cache configuration. 446 */ 447 switch (vers) { 448 case MPC604: 449 case MPC604e: 450 case MPC604ev: 451 case MPC750: 452 case IBM750FX: 453 case MPC7400: 454 case MPC7410: 455 case MPC7450: 456 case MPC7455: 457 case MPC7457: 458 aprint_normal("%s: ", self->dv_xname); 459 cpu_print_speed(); 460 461 if (vers == IBM750FX || vers == MPC750 || 462 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 463 if (MPC745X_P(vers)) { 464 cpu_config_l3cr(vers); 465 } else { 466 cpu_config_l2cr(pvr); 467 } 468 } 469 aprint_normal("\n"); 470 break; 471 } 472 473 #if NSYSMON_ENVSYS > 0 474 /* 475 * Attach MPC750 temperature sensor to the envsys subsystem. 476 * XXX the 74xx series also has this sensor, but it is not 477 * XXX supported by Motorola and may return values that are off by 478 * XXX 35-55 degrees C. 479 */ 480 if (vers == MPC750 || vers == IBM750FX) 481 cpu_tau_setup(ci); 482 #endif 483 484 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 485 NULL, self->dv_xname, "clock"); 486 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 487 NULL, self->dv_xname, "soft clock"); 488 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 489 NULL, self->dv_xname, "soft net"); 490 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 491 NULL, self->dv_xname, "soft serial"); 492 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 493 NULL, self->dv_xname, "traps"); 494 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 495 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 496 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 497 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 498 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 499 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 500 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 501 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 502 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 503 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 504 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 505 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 506 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 507 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 508 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 509 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 510 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 511 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 512 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 513 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 514 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 515 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 516 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 517 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 518 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 519 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 520 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 521 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 522 #ifdef ALTIVEC 523 if (cpu_altivec) { 524 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 525 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 526 } 527 #endif 528 } 529 530 void 531 cpu_identify(char *str, size_t len) 532 { 533 u_int pvr, maj, min; 534 uint16_t vers, rev, revfmt; 535 const struct cputab *cp; 536 const char *name; 537 size_t n; 538 539 pvr = mfpvr(); 540 vers = pvr >> 16; 541 rev = pvr; 542 switch (vers) { 543 case MPC7410: 544 min = (pvr >> 0) & 0xff; 545 maj = min <= 4 ? 1 : 2; 546 break; 547 default: 548 maj = (pvr >> 8) & 0xf; 549 min = (pvr >> 0) & 0xf; 550 } 551 552 for (cp = models; cp->name[0] != '\0'; cp++) { 553 if (cp->version == vers) 554 break; 555 } 556 557 if (str == NULL) { 558 str = cpu_model; 559 len = sizeof(cpu_model); 560 cpu = vers; 561 } 562 563 revfmt = cp->revfmt; 564 name = cp->name; 565 if (rev == MPC750 && pvr == 15) { 566 name = "755"; 567 revfmt = REVFMT_HEX; 568 } 569 570 if (cp->name[0] != '\0') { 571 n = snprintf(str, len, "%s (Revision ", cp->name); 572 } else { 573 n = snprintf(str, len, "Version %#x (Revision ", vers); 574 } 575 if (len > n) { 576 switch (revfmt) { 577 case REVFMT_MAJMIN: 578 snprintf(str + n, len - n, "%u.%u)", maj, min); 579 break; 580 case REVFMT_HEX: 581 snprintf(str + n, len - n, "0x%04x)", rev); 582 break; 583 case REVFMT_DEC: 584 snprintf(str + n, len - n, "%u)", rev); 585 break; 586 } 587 } 588 } 589 590 #ifdef L2CR_CONFIG 591 u_int l2cr_config = L2CR_CONFIG; 592 #else 593 u_int l2cr_config = 0; 594 #endif 595 596 #ifdef L3CR_CONFIG 597 u_int l3cr_config = L3CR_CONFIG; 598 #else 599 u_int l3cr_config = 0; 600 #endif 601 602 void 603 cpu_enable_l2cr(register_t l2cr) 604 { 605 register_t msr, x; 606 607 /* Disable interrupts and set the cache config bits. */ 608 msr = mfmsr(); 609 mtmsr(msr & ~PSL_EE); 610 #ifdef ALTIVEC 611 if (cpu_altivec) 612 __asm __volatile("dssall"); 613 #endif 614 __asm __volatile("sync"); 615 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 616 __asm __volatile("sync"); 617 618 /* Wait for L2 clock to be stable (640 L2 clocks). */ 619 delay(100); 620 621 /* Invalidate all L2 contents. */ 622 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 623 do { 624 x = mfspr(SPR_L2CR); 625 } while (x & L2CR_L2IP); 626 627 /* Enable L2 cache. */ 628 l2cr |= L2CR_L2E; 629 mtspr(SPR_L2CR, l2cr); 630 mtmsr(msr); 631 } 632 633 void 634 cpu_enable_l3cr(register_t l3cr) 635 { 636 register_t x; 637 638 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 639 640 /* 641 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 642 * L3CLKEN. (also mask off reserved bits in case they were included 643 * in L3CR_CONFIG) 644 */ 645 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 646 mtspr(SPR_L3CR, l3cr); 647 648 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 649 l3cr |= 0x04000000; 650 mtspr(SPR_L3CR, l3cr); 651 652 /* 3: Set L3CLKEN to 1*/ 653 l3cr |= L3CR_L3CLKEN; 654 mtspr(SPR_L3CR, l3cr); 655 656 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 657 __asm __volatile("dssall;sync"); 658 /* L3 cache is already disabled, no need to clear L3E */ 659 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 660 do { 661 x = mfspr(SPR_L3CR); 662 } while (x & L3CR_L3I); 663 664 /* 6: Clear L3CLKEN to 0 */ 665 l3cr &= ~L3CR_L3CLKEN; 666 mtspr(SPR_L3CR, l3cr); 667 668 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 669 __asm __volatile("sync"); 670 delay(100); 671 672 /* 8: Set L3E and L3CLKEN */ 673 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 674 mtspr(SPR_L3CR, l3cr); 675 676 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 677 __asm __volatile("sync"); 678 delay(100); 679 } 680 681 void 682 cpu_config_l2cr(int pvr) 683 { 684 register_t l2cr; 685 686 l2cr = mfspr(SPR_L2CR); 687 688 /* 689 * For MP systems, the firmware may only configure the L2 cache 690 * on the first CPU. In this case, assume that the other CPUs 691 * should use the same value for L2CR. 692 */ 693 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 694 l2cr_config = l2cr; 695 } 696 697 /* 698 * Configure L2 cache if not enabled. 699 */ 700 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 701 cpu_enable_l2cr(l2cr_config); 702 l2cr = mfspr(SPR_L2CR); 703 } 704 705 if ((l2cr & L2CR_L2E) == 0) { 706 aprint_normal(" L2 cache present but not enabled "); 707 return; 708 } 709 710 aprint_normal(","); 711 if ((pvr >> 16) == IBM750FX || 712 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 713 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 714 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 715 } else { 716 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 717 } 718 } 719 720 void 721 cpu_config_l3cr(int vers) 722 { 723 register_t l2cr; 724 register_t l3cr; 725 726 l2cr = mfspr(SPR_L2CR); 727 728 /* 729 * For MP systems, the firmware may only configure the L2 cache 730 * on the first CPU. In this case, assume that the other CPUs 731 * should use the same value for L2CR. 732 */ 733 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 734 l2cr_config = l2cr; 735 } 736 737 /* 738 * Configure L2 cache if not enabled. 739 */ 740 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 741 cpu_enable_l2cr(l2cr_config); 742 l2cr = mfspr(SPR_L2CR); 743 } 744 745 aprint_normal(","); 746 cpu_fmttab_print(vers == MPC7457 747 ? cpu_7457_l2cr_formats : cpu_7450_l2cr_formats, l2cr); 748 749 l3cr = mfspr(SPR_L3CR); 750 751 /* 752 * For MP systems, the firmware may only configure the L3 cache 753 * on the first CPU. In this case, assume that the other CPUs 754 * should use the same value for L3CR. 755 */ 756 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 757 l3cr_config = l3cr; 758 } 759 760 /* 761 * Configure L3 cache if not enabled. 762 */ 763 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 764 cpu_enable_l3cr(l3cr_config); 765 l3cr = mfspr(SPR_L3CR); 766 } 767 768 if (l3cr & L3CR_L3E) { 769 aprint_normal(","); 770 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 771 } 772 } 773 774 void 775 cpu_print_speed(void) 776 { 777 uint64_t cps; 778 779 mtspr(SPR_MMCR0, MMCR0_FC); 780 mtspr(SPR_PMC1, 0); 781 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 782 delay(100000); 783 cps = (mfspr(SPR_PMC1) * 10) + 4999; 784 785 mtspr(SPR_MMCR0, MMCR0_FC); 786 787 aprint_normal("%lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 788 } 789 790 #if NSYSMON_ENVSYS > 0 791 const struct envsys_range cpu_tau_ranges[] = { 792 { 0, 0, ENVSYS_STEMP} 793 }; 794 795 struct envsys_basic_info cpu_tau_info[] = { 796 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 797 }; 798 799 void 800 cpu_tau_setup(struct cpu_info *ci) 801 { 802 struct { 803 struct sysmon_envsys sme; 804 struct envsys_tre_data tau_info; 805 } *datap; 806 int error; 807 808 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 809 810 ci->ci_sysmon_cookie = &datap->sme; 811 datap->sme.sme_nsensors = 1; 812 datap->sme.sme_envsys_version = 1000; 813 datap->sme.sme_ranges = cpu_tau_ranges; 814 datap->sme.sme_sensor_info = cpu_tau_info; 815 datap->sme.sme_sensor_data = &datap->tau_info; 816 817 datap->sme.sme_sensor_data->sensor = 0; 818 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 819 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 820 datap->sme.sme_cookie = ci; 821 datap->sme.sme_gtredata = cpu_tau_gtredata; 822 datap->sme.sme_streinfo = cpu_tau_streinfo; 823 datap->sme.sme_flags = 0; 824 825 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 826 aprint_error("%s: unable to register with sysmon (%d)\n", 827 ci->ci_dev->dv_xname, error); 828 } 829 830 831 /* Find the temperature of the CPU. */ 832 int 833 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 834 { 835 int i, threshold, count; 836 837 if (tred->sensor != 0) { 838 tred->validflags = 0; 839 return 0; 840 } 841 842 threshold = 64; /* Half of the 7-bit sensor range */ 843 mtspr(SPR_THRM1, 0); 844 mtspr(SPR_THRM2, 0); 845 /* XXX This counter is supposed to be "at least 20 microseonds, in 846 * XXX units of clock cycles". Since we don't have convenient 847 * XXX access to the CPU speed, set it to a conservative value, 848 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 849 * XXX the fastest G3 processor is 700MHz) . The cost is that 850 * XXX measuring the temperature takes a bit longer. 851 */ 852 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 853 854 /* Successive-approximation code adapted from Motorola 855 * application note AN1800/D, "Programming the Thermal Assist 856 * Unit in the MPC750 Microprocessor". 857 */ 858 for (i = 4; i >= 0 ; i--) { 859 mtspr(SPR_THRM1, 860 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 861 count = 0; 862 while ((count < 100) && 863 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 864 count++; 865 delay(1); 866 } 867 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 868 /* The interrupt bit was set, meaning the 869 * temperature was above the threshold 870 */ 871 threshold += 2 << i; 872 } else { 873 /* Temperature was below the threshold */ 874 threshold -= 2 << i; 875 } 876 } 877 threshold += 2; 878 879 /* Convert the temperature in degrees C to microkelvin */ 880 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 881 882 *tred = *sme->sme_sensor_data; 883 884 return 0; 885 } 886 887 int 888 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 889 { 890 891 /* There is nothing to set here. */ 892 return (EINVAL); 893 } 894 #endif /* NSYSMON_ENVSYS > 0 */ 895
Indexes created Tue Sep 23 14:10:03 GMT 2025