cpu_subr.c revision 1.2
1 /* $NetBSD: cpu_subr.c,v 1.2 2003/02/26 21:05:23 jklos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include "opt_ppcparam.h" 37 #include "opt_multiprocessor.h" 38 #include "opt_altivec.h" 39 #include "sysmon_envsys.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <powerpc/oea/hid.h> 48 #include <powerpc/oea/hid_601.h> 49 #include <powerpc/spr.h> 50 51 #include <dev/sysmon/sysmonvar.h> 52 53 static void cpu_config_l2cr(int); 54 static void cpu_print_speed(void); 55 #if NSYSMON_ENVSYS > 0 56 static void cpu_tau_setup(struct cpu_info *); 57 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 58 struct envsys_tre_data *)); 59 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 60 struct envsys_basic_info *)); 61 #endif 62 63 int cpu; 64 int ncpus; 65 66 #ifdef MULTIPROCESSOR 67 struct cpu_info cpu_info[CPU_MAXNUM]; 68 #else 69 struct cpu_info cpu_info[1]; 70 #endif 71 72 int cpu_altivec; 73 char cpu_model[80]; 74 75 void 76 cpu_probe_cache(void) 77 { 78 u_int assoc, pvr, vers; 79 80 pvr = mfpvr(); 81 vers = pvr >> 16; 82 83 switch (vers) { 84 #define K *1024 85 case IBM750FX: 86 case MPC601: 87 case MPC750: 88 case MPC7450: 89 case MPC7455: 90 curcpu()->ci_ci.dcache_size = 32 K; 91 curcpu()->ci_ci.icache_size = 32 K; 92 assoc = 8; 93 break; 94 case MPC603: 95 curcpu()->ci_ci.dcache_size = 8 K; 96 curcpu()->ci_ci.icache_size = 8 K; 97 assoc = 2; 98 break; 99 case MPC603e: 100 case MPC603ev: 101 case MPC604: 102 case MPC8240: 103 case MPC8245: 104 curcpu()->ci_ci.dcache_size = 16 K; 105 curcpu()->ci_ci.icache_size = 16 K; 106 assoc = 4; 107 break; 108 case MPC604ev: 109 curcpu()->ci_ci.dcache_size = 32 K; 110 curcpu()->ci_ci.icache_size = 32 K; 111 assoc = 4; 112 break; 113 default: 114 curcpu()->ci_ci.dcache_size = NBPG; 115 curcpu()->ci_ci.icache_size = NBPG; 116 assoc = 1; 117 #undef K 118 } 119 120 /* Presently common across all implementations. */ 121 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 122 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 123 124 /* 125 * Possibly recolor. 126 */ 127 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 128 } 129 130 struct cpu_info * 131 cpu_attach_common(struct device *self, int id) 132 { 133 struct cpu_info *ci; 134 u_int pvr, vers; 135 136 ncpus++; 137 ci = &cpu_info[id]; 138 #ifndef MULTIPROCESSOR 139 /* 140 * If this isn't the primary CPU, print an error message 141 * and just bail out. 142 */ 143 if (id != 0) { 144 printf(": ID %d\n", id); 145 printf("%s: processor off-line; multiprocessor support " 146 "not present in kernel\n", self->dv_xname); 147 return (NULL); 148 } 149 #endif 150 151 ci->ci_cpuid = id; 152 ci->ci_intrdepth = -1; 153 ci->ci_dev = self; 154 155 pvr = mfpvr(); 156 vers = (pvr >> 16) & 0xffff; 157 158 switch (id) { 159 case 0: 160 /* load my cpu_number to PIR */ 161 switch (vers) { 162 case MPC601: 163 case MPC604: 164 case MPC604ev: 165 case MPC7400: 166 case MPC7410: 167 case MPC7450: 168 case MPC7455: 169 mtspr(SPR_PIR, id); 170 } 171 cpu_setup(self, ci); 172 break; 173 default: 174 if (id >= CPU_MAXNUM) { 175 printf(": more than %d cpus?\n", CPU_MAXNUM); 176 panic("cpuattach"); 177 } 178 #ifndef MULTIPROCESSOR 179 printf(" not configured\n"); 180 return NULL; 181 #endif 182 } 183 return (ci); 184 } 185 186 void 187 cpu_setup(self, ci) 188 struct device *self; 189 struct cpu_info *ci; 190 { 191 u_int hid0, pvr, vers; 192 char *bitmask, hidbuf[128]; 193 char model[80]; 194 195 pvr = mfpvr(); 196 vers = (pvr >> 16) & 0xffff; 197 198 cpu_identify(model, sizeof(model)); 199 printf(": %s, ID %d%s\n", model, cpu_number(), 200 cpu_number() == 0 ? " (primary)" : ""); 201 202 hid0 = mfspr(SPR_HID0); 203 cpu_probe_cache(); 204 205 /* 206 * Configure power-saving mode. 207 */ 208 switch (vers) { 209 case MPC603: 210 case MPC603e: 211 case MPC603ev: 212 case MPC604ev: 213 case MPC750: 214 case IBM750FX: 215 case MPC7400: 216 case MPC7410: 217 case MPC8240: 218 case MPC8245: 219 /* Select DOZE mode. */ 220 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 221 hid0 |= HID0_DOZE | HID0_DPM; 222 powersave = 1; 223 break; 224 225 case MPC7455: 226 case MPC7450: 227 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 228 if ((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 229 hid0 &= ~HID0_BTIC; 230 /* Select NAP mode. */ 231 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 232 hid0 |= HID0_NAP | HID0_DPM; 233 powersave = 0; /* but don't use it */ 234 break; 235 236 default: 237 /* No power-saving mode is available. */ ; 238 } 239 240 #ifdef NAPMODE 241 switch (vers) { 242 case IBM750FX: 243 case MPC750: 244 case MPC7400: 245 /* Select NAP mode. */ 246 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 247 hid0 |= HID0_NAP; 248 break; 249 } 250 #endif 251 252 switch (vers) { 253 case IBM750FX: 254 case MPC750: 255 hid0 &= ~HID0_DBP; /* XXX correct? */ 256 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 257 break; 258 259 case MPC7400: 260 case MPC7410: 261 hid0 &= ~HID0_SPD; 262 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 263 hid0 |= HID0_EIEC; 264 break; 265 } 266 267 mtspr(SPR_HID0, hid0); 268 269 switch (vers) { 270 case MPC601: 271 bitmask = HID0_601_BITMASK; 272 break; 273 case MPC7450: 274 case MPC7455: 275 bitmask = HID0_7450_BITMASK; 276 break; 277 default: 278 bitmask = HID0_BITMASK; 279 break; 280 } 281 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 282 printf("%s: HID0 %s\n", self->dv_xname, hidbuf); 283 284 /* 285 * Display speed and cache configuration. 286 */ 287 if (vers == MPC750 || vers == MPC7400 || vers == IBM750FX || 288 vers == MPC7410 || vers == MPC7450 || vers == MPC7455) { 289 printf("%s", self->dv_xname); 290 cpu_print_speed(); 291 printf("%s", self->dv_xname); 292 cpu_config_l2cr(vers); 293 } 294 295 #if NSYSMON_ENVSYS > 0 296 /* 297 * Attach MPC750 temperature sensor to the envsys subsystem. 298 * XXX the 74xx series also has this sensor, but it is not 299 * XXX supported by Motorola and may return values that are off by 300 * XXX 35-55 degrees C. 301 */ 302 if (vers == MPC750 || vers == IBM750FX) 303 cpu_tau_setup(ci); 304 #endif 305 306 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 307 NULL, self->dv_xname, "clock"); 308 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 309 NULL, self->dv_xname, "soft clock"); 310 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 311 NULL, self->dv_xname, "soft net"); 312 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 313 NULL, self->dv_xname, "soft serial"); 314 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 315 NULL, self->dv_xname, "traps"); 316 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 317 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 318 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 319 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 320 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 321 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 322 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 323 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 324 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 325 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 326 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 327 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 328 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 329 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 330 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 331 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 332 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 333 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 334 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 335 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 336 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 337 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 338 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 339 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 340 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 341 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 342 #ifdef ALTIVEC 343 if (cpu_altivec) { 344 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 345 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 346 } 347 #endif 348 } 349 350 struct cputab { 351 const char name[8]; 352 uint16_t version; 353 uint16_t revfmt; 354 }; 355 #define REVFMT_MAJMIN 1 /* %u.%u */ 356 #define REVFMT_HEX 2 /* 0x%04x */ 357 #define REVFMT_DEC 3 /* %u */ 358 static const struct cputab models[] = { 359 { "601", MPC601, REVFMT_DEC }, 360 { "602", MPC602, REVFMT_DEC }, 361 { "603", MPC603, REVFMT_MAJMIN }, 362 { "603e", MPC603e, REVFMT_MAJMIN }, 363 { "603ev", MPC603ev, REVFMT_MAJMIN }, 364 { "604", MPC604, REVFMT_MAJMIN }, 365 { "604ev", MPC604ev, REVFMT_MAJMIN }, 366 { "620", MPC620, REVFMT_HEX }, 367 { "750", MPC750, REVFMT_MAJMIN }, 368 { "750FX", IBM750FX, REVFMT_MAJMIN }, 369 { "7400", MPC7400, REVFMT_MAJMIN }, 370 { "7410", MPC7410, REVFMT_MAJMIN }, 371 { "7450", MPC7450, REVFMT_MAJMIN }, 372 { "7455", MPC7455, REVFMT_MAJMIN }, 373 { "8240", MPC8240, REVFMT_MAJMIN }, 374 { "", 0, REVFMT_HEX } 375 }; 376 377 void 378 cpu_identify(char *str, size_t len) 379 { 380 u_int pvr, maj, min; 381 uint16_t vers, rev, revfmt; 382 const struct cputab *cp; 383 const char *name; 384 size_t n; 385 386 pvr = mfpvr(); 387 vers = pvr >> 16; 388 rev = pvr; 389 switch (vers) { 390 case MPC7410: 391 min = (pvr >> 0) & 0xff; 392 maj = min <= 4 ? 1 : 2; 393 break; 394 default: 395 maj = (pvr >> 8) & 0xf; 396 min = (pvr >> 0) & 0xf; 397 } 398 399 for (cp = models; cp->name[0] != '\0'; cp++) { 400 if (cp->version == vers) 401 break; 402 } 403 404 if (str == NULL) { 405 str = cpu_model; 406 len = sizeof(cpu_model); 407 cpu = vers; 408 } 409 410 revfmt = cp->revfmt; 411 name = cp->name; 412 if (rev == MPC750 && pvr == 15) { 413 name = "755"; 414 revfmt = REVFMT_HEX; 415 } 416 417 if (cp->name[0] != '\0') { 418 n = snprintf(str, len, "%s (Revision ", cp->name); 419 } else { 420 n = snprintf(str, len, "Version %#x (Revision ", vers); 421 } 422 if (len > n) { 423 switch (revfmt) { 424 case REVFMT_MAJMIN: 425 snprintf(str + n, len - n, "%u.%u)", maj, min); 426 break; 427 case REVFMT_HEX: 428 snprintf(str + n, len - n, "0x%04x)", rev); 429 break; 430 case REVFMT_DEC: 431 snprintf(str + n, len - n, "%u)", rev); 432 break; 433 } 434 } 435 } 436 437 #ifdef L2CR_CONFIG 438 u_int l2cr_config = L2CR_CONFIG; 439 #else 440 u_int l2cr_config = 0; 441 #endif 442 443 #ifdef L3CR_CONFIG 444 u_int l3cr_config = L3CR_CONFIG; 445 #else 446 u_int l3cr_config = 0; 447 #endif 448 449 void 450 cpu_config_l2cr(int vers) 451 { 452 u_int l2cr, x, msr; 453 454 l2cr = mfspr(SPR_L2CR); 455 456 /* 457 * For MP systems, the firmware may only configure the L2 cache 458 * on the first CPU. In this case, assume that the other CPUs 459 * should use the same value for L2CR. 460 */ 461 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 462 l2cr_config = l2cr; 463 } 464 465 /* 466 * Configure L2 cache if not enabled. 467 */ 468 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 469 l2cr = l2cr_config; 470 471 /* Disable interrupts and set the cache config bits. */ 472 msr = mfmsr(); 473 mtmsr(msr & ~PSL_EE); 474 #ifdef ALTIVEC 475 if (cpu_altivec) 476 __asm __volatile("dssall"); 477 #endif 478 __asm __volatile("sync"); 479 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 480 __asm __volatile("sync"); 481 482 /* Wait for L2 clock to be stable (640 L2 clocks). */ 483 delay(100); 484 485 /* Invalidate all L2 contents. */ 486 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 487 do { 488 x = mfspr(SPR_L2CR); 489 } while (x & L2CR_L2IP); 490 491 /* Enable L2 cache. */ 492 l2cr |= L2CR_L2E; 493 mtspr(SPR_L2CR, l2cr); 494 mtmsr(msr); 495 } 496 497 if (l2cr & L2CR_L2E) { 498 if (vers == MPC7450 || vers == MPC7455) { 499 u_int l3cr; 500 501 printf(": 256KB L2 cache"); 502 503 l3cr = mfspr(SPR_L3CR); 504 505 /* 506 * Configure L3 cache if not enabled. 507 */ 508 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 509 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 510 511 /* 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and L3CLKEN */ 512 /* (also mask off reserved bits in case they were included in L3CR_CONFIG) */ 513 l3cr = l3cr_config & ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 514 mtspr(SPR_L3CR, l3cr); 515 516 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 517 l3cr |= 0x04000000; 518 mtspr(SPR_L3CR, l3cr); 519 520 /* 3: Set L3CLKEN to 1*/ 521 l3cr |= L3CR_L3CLKEN; 522 mtspr(SPR_L3CR, l3cr); 523 524 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 525 __asm __volatile("dssall;sync"); 526 /* L3 cache is already disabled, no need to clear L3E */ 527 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 528 do { 529 x = mfspr(SPR_L3CR); 530 } while (x & L3CR_L3I); 531 532 /* 6: Clear L3CLKEN to 0 */ 533 l3cr &= ~L3CR_L3CLKEN; 534 mtspr(SPR_L3CR, l3cr); 535 536 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 537 __asm __volatile("sync"); 538 delay(100); 539 540 /* 8: Set L3E and L3CLKEN */ 541 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 542 mtspr(SPR_L3CR, l3cr); 543 544 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 545 __asm __volatile("sync"); 546 delay(100); 547 } 548 549 if (l3cr & L3CR_L3E) { 550 printf(", %cMB L3 backside cache at ", 551 l3cr & L3CR_L3SIZ ? '2' : '1'); 552 switch (l3cr & L3CR_L3CLK) { 553 case L3CLK_20: 554 printf("2:1 ratio"); 555 break; 556 case L3CLK_25: 557 printf("2.5:1 ratio"); 558 break; 559 case L3CLK_30: 560 printf("3:1 ratio"); 561 break; 562 case L3CLK_35: 563 printf("3.5:1 ratio"); 564 break; 565 case L3CLK_40: 566 printf("4:1 ratio"); 567 break; 568 case L3CLK_50: 569 printf("5:1 ratio"); 570 break; 571 case L3CLK_60: 572 printf("6:1 ratio"); 573 break; 574 default: 575 printf("unknown ratio"); 576 break; 577 } 578 } 579 printf("\n"); 580 return; 581 } 582 if (vers == IBM750FX) { 583 printf(": 512KB L2 cache\n"); 584 return; 585 } 586 switch (l2cr & L2CR_L2SIZ) { 587 case L2SIZ_256K: 588 printf(": 256KB"); 589 break; 590 case L2SIZ_512K: 591 printf(": 512KB"); 592 break; 593 case L2SIZ_1M: 594 printf(": 1MB"); 595 break; 596 default: 597 printf(": unknown size"); 598 } 599 if (l2cr & L2CR_L2WT) { 600 printf(" write-through"); 601 } else { 602 printf(" write-back"); 603 } 604 switch (l2cr & L2CR_L2RAM) { 605 case L2RAM_FLOWTHRU_BURST: 606 printf(" Flow-through synchronous burst SRAM"); 607 break; 608 case L2RAM_PIPELINE_BURST: 609 printf(" Pipelined synchronous burst SRAM"); 610 break; 611 case L2RAM_PIPELINE_LATE: 612 printf(" Pipelined synchronous late-write SRAM"); 613 break; 614 default: 615 printf(" unknown type"); 616 } 617 618 if (l2cr & L2CR_L2PE) 619 printf(" with parity"); 620 printf(" backside cache"); 621 } else 622 printf(": L2 cache not enabled"); 623 624 printf("\n"); 625 } 626 627 void 628 cpu_print_speed(void) 629 { 630 uint64_t cps; 631 632 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 633 mtspr(SPR_PMC1, 0); 634 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 635 delay(100000); 636 cps = (mfspr(SPR_PMC1) * 10) + 4999; 637 638 printf(": %lld.%02lld MHz\n", cps / 1000000, (cps / 10000) % 100); 639 } 640 641 #if NSYSMON_ENVSYS > 0 642 const struct envsys_range cpu_tau_ranges[] = { 643 { 0, 0, ENVSYS_STEMP} 644 }; 645 646 struct envsys_basic_info cpu_tau_info[] = { 647 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 648 }; 649 650 void 651 cpu_tau_setup(struct cpu_info *ci) 652 { 653 struct sysmon_envsys *sme; 654 int error; 655 656 sme = &ci->ci_sysmon; 657 sme->sme_nsensors = 1; 658 sme->sme_envsys_version = 1000; 659 sme->sme_ranges = cpu_tau_ranges; 660 sme->sme_sensor_info = cpu_tau_info; 661 sme->sme_sensor_data = &ci->ci_tau_info; 662 663 sme->sme_sensor_data->sensor = 0; 664 sme->sme_sensor_data->warnflags = ENVSYS_WARN_OK; 665 sme->sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 666 sme->sme_cookie = ci; 667 sme->sme_gtredata = cpu_tau_gtredata; 668 sme->sme_streinfo = cpu_tau_streinfo; 669 670 if ((error = sysmon_envsys_register(sme)) != 0) 671 printf("%s: unable to register with sysmon (%d)\n", 672 ci->ci_dev->dv_xname, error); 673 } 674 675 676 /* Find the temperature of the CPU. */ 677 int 678 cpu_tau_gtredata(sme, tred) 679 struct sysmon_envsys *sme; 680 struct envsys_tre_data *tred; 681 { 682 struct cpu_info *ci; 683 int i, threshold, count; 684 685 if (tred->sensor != 0) { 686 tred->validflags = 0; 687 return 0; 688 } 689 690 threshold = 64; /* Half of the 7-bit sensor range */ 691 mtspr(SPR_THRM1, 0); 692 mtspr(SPR_THRM2, 0); 693 /* XXX This counter is supposed to be "at least 20 microseonds, in 694 * XXX units of clock cycles". Since we don't have convenient 695 * XXX access to the CPU speed, set it to a conservative value, 696 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 697 * XXX the fastest G3 processor is 700MHz) . The cost is that 698 * XXX measuring the temperature takes a bit longer. 699 */ 700 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 701 702 /* Successive-approximation code adapted from Motorola 703 * application note AN1800/D, "Programming the Thermal Assist 704 * Unit in the MPC750 Microprocessor". 705 */ 706 for (i = 4; i >= 0 ; i--) { 707 mtspr(SPR_THRM1, 708 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 709 count = 0; 710 while ((count < 100) && 711 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 712 count++; 713 delay(1); 714 } 715 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 716 /* The interrupt bit was set, meaning the 717 * temperature was above the threshold 718 */ 719 threshold += 2 << i; 720 } else { 721 /* Temperature was below the threshold */ 722 threshold -= 2 << i; 723 } 724 } 725 threshold += 2; 726 727 ci = (struct cpu_info *)sme->sme_cookie; 728 /* Convert the temperature in degrees C to microkelvin */ 729 ci->ci_tau_info.cur.data_us = (threshold * 1000000) + 273150000; 730 731 *tred = ci->ci_tau_info; 732 733 return 0; 734 } 735 736 int 737 cpu_tau_streinfo(sme, binfo) 738 struct sysmon_envsys *sme; 739 struct envsys_basic_info *binfo; 740 { 741 742 /* There is nothing to set here. */ 743 return (EINVAL); 744 } 745 #endif /* NSYSMON_ENVSYS > 0 */ 746
Indexes created Wed Sep 24 22:09:59 GMT 2025