cpu_subr.c revision 1.20
1 /* $NetBSD: cpu_subr.c,v 1.20 2005/01/19 22:22:56 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.20 2005/01/19 22:22:56 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_print_speed(void); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0 } 87 }; 88 89 static const struct fmttab cpu_7457_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 512KB L2 cache" }, 95 { 0 } 96 }; 97 98 static const struct fmttab cpu_7450_l3cr_formats[] = { 99 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 100 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 101 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 102 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 103 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 104 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 105 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 106 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 107 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 108 { L3CR_L3SIZ, ~0, " L3 cache" }, 109 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 110 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 111 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 112 { L3CR_L3CLK, ~0, " at" }, 113 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 114 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 115 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 116 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 117 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 118 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 119 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 120 { L3CR_L3CLK, ~0, " ratio" }, 121 { 0, 0 }, 122 }; 123 124 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 125 { L2CR_L2E, 0, " disabled" }, 126 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 127 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 128 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 129 { 0, ~0, " 512KB" }, 130 { L2CR_L2WT, L2CR_L2WT, " WT" }, 131 { L2CR_L2WT, 0, " WB" }, 132 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 133 { 0, ~0, " L2 cache" }, 134 { 0 } 135 }; 136 137 static const struct fmttab cpu_l2cr_formats[] = { 138 { L2CR_L2E, 0, " disabled" }, 139 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 140 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 141 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 142 { L2CR_L2PE, L2CR_L2PE, " parity" }, 143 { L2CR_L2PE, 0, " no-parity" }, 144 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 145 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 146 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 147 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 148 { L2CR_L2WT, L2CR_L2WT, " WT" }, 149 { L2CR_L2WT, 0, " WB" }, 150 { L2CR_L2E, ~0, " L2 cache" }, 151 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 152 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 153 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 154 { L2CR_L2CLK, ~0, " at" }, 155 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 156 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 157 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 158 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 159 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 160 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 161 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 162 { L2CR_L2CLK, ~0, " ratio" }, 163 { 0 } 164 }; 165 166 static void cpu_fmttab_print(const struct fmttab *, register_t); 167 168 struct cputab { 169 const char name[8]; 170 uint16_t version; 171 uint16_t revfmt; 172 }; 173 #define REVFMT_MAJMIN 1 /* %u.%u */ 174 #define REVFMT_HEX 2 /* 0x%04x */ 175 #define REVFMT_DEC 3 /* %u */ 176 static const struct cputab models[] = { 177 { "601", MPC601, REVFMT_DEC }, 178 { "602", MPC602, REVFMT_DEC }, 179 { "603", MPC603, REVFMT_MAJMIN }, 180 { "603e", MPC603e, REVFMT_MAJMIN }, 181 { "603ev", MPC603ev, REVFMT_MAJMIN }, 182 { "604", MPC604, REVFMT_MAJMIN }, 183 { "604e", MPC604e, REVFMT_MAJMIN }, 184 { "604ev", MPC604ev, REVFMT_MAJMIN }, 185 { "620", MPC620, REVFMT_HEX }, 186 { "750", MPC750, REVFMT_MAJMIN }, 187 { "750FX", IBM750FX, REVFMT_MAJMIN }, 188 { "7400", MPC7400, REVFMT_MAJMIN }, 189 { "7410", MPC7410, REVFMT_MAJMIN }, 190 { "7450", MPC7450, REVFMT_MAJMIN }, 191 { "7455", MPC7455, REVFMT_MAJMIN }, 192 { "7457", MPC7457, REVFMT_MAJMIN }, 193 { "8240", MPC8240, REVFMT_MAJMIN }, 194 { "", 0, REVFMT_HEX } 195 }; 196 197 198 #ifdef MULTIPROCESSOR 199 struct cpu_info cpu_info[CPU_MAXNUM]; 200 #else 201 struct cpu_info cpu_info[1]; 202 #endif 203 204 int cpu_altivec; 205 int cpu_psluserset, cpu_pslusermod; 206 char cpu_model[80]; 207 208 void 209 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 210 { 211 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 212 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 213 (data & fmt->fmt_mask) == fmt->fmt_value) 214 aprint_normal("%s", fmt->fmt_string); 215 } 216 } 217 218 void 219 cpu_idlespin(void) 220 { 221 register_t msr; 222 223 if (powersave <= 0) 224 return; 225 226 __asm __volatile( 227 "sync;" 228 "mfmsr %0;" 229 "oris %0,%0,%1@h;" /* enter power saving mode */ 230 "mtmsr %0;" 231 "isync;" 232 : "=r"(msr) 233 : "J"(PSL_POW)); 234 } 235 236 void 237 cpu_probe_cache(void) 238 { 239 u_int assoc, pvr, vers; 240 241 pvr = mfpvr(); 242 vers = pvr >> 16; 243 244 switch (vers) { 245 #define K *1024 246 case IBM750FX: 247 case MPC601: 248 case MPC750: 249 case MPC7450: 250 case MPC7455: 251 case MPC7457: 252 curcpu()->ci_ci.dcache_size = 32 K; 253 curcpu()->ci_ci.icache_size = 32 K; 254 assoc = 8; 255 break; 256 case MPC603: 257 curcpu()->ci_ci.dcache_size = 8 K; 258 curcpu()->ci_ci.icache_size = 8 K; 259 assoc = 2; 260 break; 261 case MPC603e: 262 case MPC603ev: 263 case MPC604: 264 case MPC8240: 265 case MPC8245: 266 curcpu()->ci_ci.dcache_size = 16 K; 267 curcpu()->ci_ci.icache_size = 16 K; 268 assoc = 4; 269 break; 270 case MPC604e: 271 case MPC604ev: 272 curcpu()->ci_ci.dcache_size = 32 K; 273 curcpu()->ci_ci.icache_size = 32 K; 274 assoc = 4; 275 break; 276 default: 277 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 278 curcpu()->ci_ci.icache_size = PAGE_SIZE; 279 assoc = 1; 280 #undef K 281 } 282 283 /* Presently common across all implementations. */ 284 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 285 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 286 287 /* 288 * Possibly recolor. 289 */ 290 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 291 } 292 293 struct cpu_info * 294 cpu_attach_common(struct device *self, int id) 295 { 296 struct cpu_info *ci; 297 u_int pvr, vers; 298 299 ncpus++; 300 ci = &cpu_info[id]; 301 #ifndef MULTIPROCESSOR 302 /* 303 * If this isn't the primary CPU, print an error message 304 * and just bail out. 305 */ 306 if (id != 0) { 307 aprint_normal(": ID %d\n", id); 308 aprint_normal("%s: processor off-line; multiprocessor support " 309 "not present in kernel\n", self->dv_xname); 310 return (NULL); 311 } 312 #endif 313 314 ci->ci_cpuid = id; 315 ci->ci_intrdepth = -1; 316 ci->ci_dev = self; 317 ci->ci_idlespin = cpu_idlespin; 318 319 pvr = mfpvr(); 320 vers = (pvr >> 16) & 0xffff; 321 322 switch (id) { 323 case 0: 324 /* load my cpu_number to PIR */ 325 switch (vers) { 326 case MPC601: 327 case MPC604: 328 case MPC604e: 329 case MPC604ev: 330 case MPC7400: 331 case MPC7410: 332 case MPC7450: 333 case MPC7455: 334 case MPC7457: 335 mtspr(SPR_PIR, id); 336 } 337 cpu_setup(self, ci); 338 break; 339 default: 340 if (id >= CPU_MAXNUM) { 341 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 342 panic("cpuattach"); 343 } 344 #ifndef MULTIPROCESSOR 345 aprint_normal(" not configured\n"); 346 return NULL; 347 #endif 348 } 349 return (ci); 350 } 351 352 void 353 cpu_setup(self, ci) 354 struct device *self; 355 struct cpu_info *ci; 356 { 357 u_int hid0, pvr, vers; 358 char *bitmask, hidbuf[128]; 359 char model[80]; 360 361 pvr = mfpvr(); 362 vers = (pvr >> 16) & 0xffff; 363 364 cpu_identify(model, sizeof(model)); 365 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 366 cpu_number() == 0 ? " (primary)" : ""); 367 368 hid0 = mfspr(SPR_HID0); 369 cpu_probe_cache(); 370 371 /* 372 * Configure power-saving mode. 373 */ 374 switch (vers) { 375 case MPC604: 376 case MPC604e: 377 case MPC604ev: 378 /* 379 * Do not have HID0 support settings, but can support 380 * MSR[POW] off 381 */ 382 powersave = 1; 383 break; 384 385 case MPC603: 386 case MPC603e: 387 case MPC603ev: 388 case MPC750: 389 case IBM750FX: 390 case MPC7400: 391 case MPC7410: 392 case MPC8240: 393 case MPC8245: 394 /* Select DOZE mode. */ 395 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 396 hid0 |= HID0_DOZE | HID0_DPM; 397 powersave = 1; 398 break; 399 400 case MPC7457: 401 case MPC7455: 402 case MPC7450: 403 /* Enable the 7450 branch caches */ 404 hid0 |= HID0_SGE | HID0_BTIC; 405 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 406 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 407 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 408 hid0 &= ~HID0_BTIC; 409 /* Select NAP mode. */ 410 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 411 hid0 |= HID0_NAP | HID0_DPM; 412 powersave = 1; 413 break; 414 415 default: 416 /* No power-saving mode is available. */ ; 417 } 418 419 #ifdef NAPMODE 420 switch (vers) { 421 case IBM750FX: 422 case MPC750: 423 case MPC7400: 424 /* Select NAP mode. */ 425 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 426 hid0 |= HID0_NAP; 427 break; 428 } 429 #endif 430 431 switch (vers) { 432 case IBM750FX: 433 case MPC750: 434 hid0 &= ~HID0_DBP; /* XXX correct? */ 435 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 436 break; 437 438 case MPC7400: 439 case MPC7410: 440 hid0 &= ~HID0_SPD; 441 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 442 hid0 |= HID0_EIEC; 443 break; 444 } 445 446 mtspr(SPR_HID0, hid0); 447 448 switch (vers) { 449 case MPC601: 450 bitmask = HID0_601_BITMASK; 451 break; 452 case MPC7450: 453 case MPC7455: 454 case MPC7457: 455 bitmask = HID0_7450_BITMASK; 456 break; 457 default: 458 bitmask = HID0_BITMASK; 459 break; 460 } 461 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 462 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 463 464 /* 465 * Display speed and cache configuration. 466 */ 467 switch (vers) { 468 case MPC604: 469 case MPC604e: 470 case MPC604ev: 471 case MPC750: 472 case IBM750FX: 473 case MPC7400: 474 case MPC7410: 475 case MPC7450: 476 case MPC7455: 477 case MPC7457: 478 aprint_normal("%s: ", self->dv_xname); 479 cpu_print_speed(); 480 481 if (vers == IBM750FX || vers == MPC750 || 482 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 483 if (MPC745X_P(vers)) { 484 cpu_config_l3cr(vers); 485 } else { 486 cpu_config_l2cr(pvr); 487 } 488 } 489 aprint_normal("\n"); 490 break; 491 } 492 493 #if NSYSMON_ENVSYS > 0 494 /* 495 * Attach MPC750 temperature sensor to the envsys subsystem. 496 * XXX the 74xx series also has this sensor, but it is not 497 * XXX supported by Motorola and may return values that are off by 498 * XXX 35-55 degrees C. 499 */ 500 if (vers == MPC750 || vers == IBM750FX) 501 cpu_tau_setup(ci); 502 #endif 503 504 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 505 NULL, self->dv_xname, "clock"); 506 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 507 NULL, self->dv_xname, "soft clock"); 508 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 509 NULL, self->dv_xname, "soft net"); 510 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 511 NULL, self->dv_xname, "soft serial"); 512 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 513 NULL, self->dv_xname, "traps"); 514 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 515 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 516 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 517 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 518 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 519 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 520 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 521 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 522 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 523 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 524 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 525 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 526 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 527 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 528 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 529 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 530 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 531 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 532 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 533 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 534 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 535 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 536 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 537 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 538 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 539 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 540 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 541 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 542 #ifdef ALTIVEC 543 if (cpu_altivec) { 544 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 545 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 546 } 547 #endif 548 } 549 550 void 551 cpu_identify(char *str, size_t len) 552 { 553 u_int pvr, maj, min; 554 uint16_t vers, rev, revfmt; 555 const struct cputab *cp; 556 const char *name; 557 size_t n; 558 559 pvr = mfpvr(); 560 vers = pvr >> 16; 561 rev = pvr; 562 switch (vers) { 563 case MPC7410: 564 min = (pvr >> 0) & 0xff; 565 maj = min <= 4 ? 1 : 2; 566 break; 567 default: 568 maj = (pvr >> 8) & 0xf; 569 min = (pvr >> 0) & 0xf; 570 } 571 572 for (cp = models; cp->name[0] != '\0'; cp++) { 573 if (cp->version == vers) 574 break; 575 } 576 577 if (str == NULL) { 578 str = cpu_model; 579 len = sizeof(cpu_model); 580 cpu = vers; 581 } 582 583 revfmt = cp->revfmt; 584 name = cp->name; 585 if (rev == MPC750 && pvr == 15) { 586 name = "755"; 587 revfmt = REVFMT_HEX; 588 } 589 590 if (cp->name[0] != '\0') { 591 n = snprintf(str, len, "%s (Revision ", cp->name); 592 } else { 593 n = snprintf(str, len, "Version %#x (Revision ", vers); 594 } 595 if (len > n) { 596 switch (revfmt) { 597 case REVFMT_MAJMIN: 598 snprintf(str + n, len - n, "%u.%u)", maj, min); 599 break; 600 case REVFMT_HEX: 601 snprintf(str + n, len - n, "0x%04x)", rev); 602 break; 603 case REVFMT_DEC: 604 snprintf(str + n, len - n, "%u)", rev); 605 break; 606 } 607 } 608 } 609 610 #ifdef L2CR_CONFIG 611 u_int l2cr_config = L2CR_CONFIG; 612 #else 613 u_int l2cr_config = 0; 614 #endif 615 616 #ifdef L3CR_CONFIG 617 u_int l3cr_config = L3CR_CONFIG; 618 #else 619 u_int l3cr_config = 0; 620 #endif 621 622 void 623 cpu_enable_l2cr(register_t l2cr) 624 { 625 register_t msr, x; 626 627 /* Disable interrupts and set the cache config bits. */ 628 msr = mfmsr(); 629 mtmsr(msr & ~PSL_EE); 630 #ifdef ALTIVEC 631 if (cpu_altivec) 632 __asm __volatile("dssall"); 633 #endif 634 __asm __volatile("sync"); 635 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 636 __asm __volatile("sync"); 637 638 /* Wait for L2 clock to be stable (640 L2 clocks). */ 639 delay(100); 640 641 /* Invalidate all L2 contents. */ 642 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 643 do { 644 x = mfspr(SPR_L2CR); 645 } while (x & L2CR_L2IP); 646 647 /* Enable L2 cache. */ 648 l2cr |= L2CR_L2E; 649 mtspr(SPR_L2CR, l2cr); 650 mtmsr(msr); 651 } 652 653 void 654 cpu_enable_l3cr(register_t l3cr) 655 { 656 register_t x; 657 658 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 659 660 /* 661 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 662 * L3CLKEN. (also mask off reserved bits in case they were included 663 * in L3CR_CONFIG) 664 */ 665 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 666 mtspr(SPR_L3CR, l3cr); 667 668 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 669 l3cr |= 0x04000000; 670 mtspr(SPR_L3CR, l3cr); 671 672 /* 3: Set L3CLKEN to 1*/ 673 l3cr |= L3CR_L3CLKEN; 674 mtspr(SPR_L3CR, l3cr); 675 676 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 677 __asm __volatile("dssall;sync"); 678 /* L3 cache is already disabled, no need to clear L3E */ 679 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 680 do { 681 x = mfspr(SPR_L3CR); 682 } while (x & L3CR_L3I); 683 684 /* 6: Clear L3CLKEN to 0 */ 685 l3cr &= ~L3CR_L3CLKEN; 686 mtspr(SPR_L3CR, l3cr); 687 688 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 689 __asm __volatile("sync"); 690 delay(100); 691 692 /* 8: Set L3E and L3CLKEN */ 693 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 694 mtspr(SPR_L3CR, l3cr); 695 696 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 697 __asm __volatile("sync"); 698 delay(100); 699 } 700 701 void 702 cpu_config_l2cr(int pvr) 703 { 704 register_t l2cr; 705 706 l2cr = mfspr(SPR_L2CR); 707 708 /* 709 * For MP systems, the firmware may only configure the L2 cache 710 * on the first CPU. In this case, assume that the other CPUs 711 * should use the same value for L2CR. 712 */ 713 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 714 l2cr_config = l2cr; 715 } 716 717 /* 718 * Configure L2 cache if not enabled. 719 */ 720 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 721 cpu_enable_l2cr(l2cr_config); 722 l2cr = mfspr(SPR_L2CR); 723 } 724 725 if ((l2cr & L2CR_L2E) == 0) { 726 aprint_normal(" L2 cache present but not enabled "); 727 return; 728 } 729 730 aprint_normal(","); 731 if ((pvr >> 16) == IBM750FX || 732 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 733 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 734 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 735 } else { 736 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 737 } 738 } 739 740 void 741 cpu_config_l3cr(int vers) 742 { 743 register_t l2cr; 744 register_t l3cr; 745 746 l2cr = mfspr(SPR_L2CR); 747 748 /* 749 * For MP systems, the firmware may only configure the L2 cache 750 * on the first CPU. In this case, assume that the other CPUs 751 * should use the same value for L2CR. 752 */ 753 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 754 l2cr_config = l2cr; 755 } 756 757 /* 758 * Configure L2 cache if not enabled. 759 */ 760 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 761 cpu_enable_l2cr(l2cr_config); 762 l2cr = mfspr(SPR_L2CR); 763 } 764 765 aprint_normal(","); 766 cpu_fmttab_print(vers == MPC7457 767 ? cpu_7457_l2cr_formats : cpu_7450_l2cr_formats, l2cr); 768 769 l3cr = mfspr(SPR_L3CR); 770 771 /* 772 * For MP systems, the firmware may only configure the L3 cache 773 * on the first CPU. In this case, assume that the other CPUs 774 * should use the same value for L3CR. 775 */ 776 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 777 l3cr_config = l3cr; 778 } 779 780 /* 781 * Configure L3 cache if not enabled. 782 */ 783 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 784 cpu_enable_l3cr(l3cr_config); 785 l3cr = mfspr(SPR_L3CR); 786 } 787 788 if (l3cr & L3CR_L3E) { 789 aprint_normal(","); 790 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 791 } 792 } 793 794 void 795 cpu_print_speed(void) 796 { 797 uint64_t cps; 798 799 mtspr(SPR_MMCR0, MMCR0_FC); 800 mtspr(SPR_PMC1, 0); 801 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 802 delay(100000); 803 cps = (mfspr(SPR_PMC1) * 10) + 4999; 804 805 mtspr(SPR_MMCR0, MMCR0_FC); 806 807 aprint_normal("%lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 808 } 809 810 #if NSYSMON_ENVSYS > 0 811 const struct envsys_range cpu_tau_ranges[] = { 812 { 0, 0, ENVSYS_STEMP} 813 }; 814 815 struct envsys_basic_info cpu_tau_info[] = { 816 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 817 }; 818 819 void 820 cpu_tau_setup(struct cpu_info *ci) 821 { 822 struct { 823 struct sysmon_envsys sme; 824 struct envsys_tre_data tau_info; 825 } *datap; 826 int error; 827 828 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 829 830 ci->ci_sysmon_cookie = &datap->sme; 831 datap->sme.sme_nsensors = 1; 832 datap->sme.sme_envsys_version = 1000; 833 datap->sme.sme_ranges = cpu_tau_ranges; 834 datap->sme.sme_sensor_info = cpu_tau_info; 835 datap->sme.sme_sensor_data = &datap->tau_info; 836 837 datap->sme.sme_sensor_data->sensor = 0; 838 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 839 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 840 datap->sme.sme_cookie = ci; 841 datap->sme.sme_gtredata = cpu_tau_gtredata; 842 datap->sme.sme_streinfo = cpu_tau_streinfo; 843 datap->sme.sme_flags = 0; 844 845 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 846 aprint_error("%s: unable to register with sysmon (%d)\n", 847 ci->ci_dev->dv_xname, error); 848 } 849 850 851 /* Find the temperature of the CPU. */ 852 int 853 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 854 { 855 int i, threshold, count; 856 857 if (tred->sensor != 0) { 858 tred->validflags = 0; 859 return 0; 860 } 861 862 threshold = 64; /* Half of the 7-bit sensor range */ 863 mtspr(SPR_THRM1, 0); 864 mtspr(SPR_THRM2, 0); 865 /* XXX This counter is supposed to be "at least 20 microseonds, in 866 * XXX units of clock cycles". Since we don't have convenient 867 * XXX access to the CPU speed, set it to a conservative value, 868 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 869 * XXX the fastest G3 processor is 700MHz) . The cost is that 870 * XXX measuring the temperature takes a bit longer. 871 */ 872 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 873 874 /* Successive-approximation code adapted from Motorola 875 * application note AN1800/D, "Programming the Thermal Assist 876 * Unit in the MPC750 Microprocessor". 877 */ 878 for (i = 4; i >= 0 ; i--) { 879 mtspr(SPR_THRM1, 880 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 881 count = 0; 882 while ((count < 100) && 883 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 884 count++; 885 delay(1); 886 } 887 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 888 /* The interrupt bit was set, meaning the 889 * temperature was above the threshold 890 */ 891 threshold += 2 << i; 892 } else { 893 /* Temperature was below the threshold */ 894 threshold -= 2 << i; 895 } 896 } 897 threshold += 2; 898 899 /* Convert the temperature in degrees C to microkelvin */ 900 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 901 902 *tred = *sme->sme_sensor_data; 903 904 return 0; 905 } 906 907 int 908 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 909 { 910 911 /* There is nothing to set here. */ 912 return (EINVAL); 913 } 914 #endif /* NSYSMON_ENVSYS > 0 */ 915
Indexes created Thu Sep 25 16:09:42 GMT 2025