cpu_subr.c revision 1.21
1 /* $NetBSD: cpu_subr.c,v 1.21 2005/01/20 21:28:47 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.21 2005/01/20 21:28:47 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_print_speed(void); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0 } 87 }; 88 89 static const struct fmttab cpu_7457_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 512KB L2 cache" }, 95 { 0 } 96 }; 97 98 static const struct fmttab cpu_7450_l3cr_formats[] = { 99 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 100 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 101 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 102 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 103 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 104 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 105 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 106 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 107 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 108 { L3CR_L3SIZ, ~0, " L3 cache" }, 109 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 110 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 111 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 112 { L3CR_L3CLK, ~0, " at" }, 113 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 114 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 115 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 116 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 117 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 118 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 119 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 120 { L3CR_L3CLK, ~0, " ratio" }, 121 { 0, 0 }, 122 }; 123 124 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 125 { L2CR_L2E, 0, " disabled" }, 126 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 127 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 128 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 129 { 0, ~0, " 512KB" }, 130 { L2CR_L2WT, L2CR_L2WT, " WT" }, 131 { L2CR_L2WT, 0, " WB" }, 132 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 133 { 0, ~0, " L2 cache" }, 134 { 0 } 135 }; 136 137 static const struct fmttab cpu_l2cr_formats[] = { 138 { L2CR_L2E, 0, " disabled" }, 139 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 140 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 141 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 142 { L2CR_L2PE, L2CR_L2PE, " parity" }, 143 { L2CR_L2PE, 0, " no-parity" }, 144 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 145 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 146 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 147 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 148 { L2CR_L2WT, L2CR_L2WT, " WT" }, 149 { L2CR_L2WT, 0, " WB" }, 150 { L2CR_L2E, ~0, " L2 cache" }, 151 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 152 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 153 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 154 { L2CR_L2CLK, ~0, " at" }, 155 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 156 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 157 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 158 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 159 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 160 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 161 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 162 { L2CR_L2CLK, ~0, " ratio" }, 163 { 0 } 164 }; 165 166 static void cpu_fmttab_print(const struct fmttab *, register_t); 167 168 struct cputab { 169 const char name[8]; 170 uint16_t version; 171 uint16_t revfmt; 172 }; 173 #define REVFMT_MAJMIN 1 /* %u.%u */ 174 #define REVFMT_HEX 2 /* 0x%04x */ 175 #define REVFMT_DEC 3 /* %u */ 176 static const struct cputab models[] = { 177 { "601", MPC601, REVFMT_DEC }, 178 { "602", MPC602, REVFMT_DEC }, 179 { "603", MPC603, REVFMT_MAJMIN }, 180 { "603e", MPC603e, REVFMT_MAJMIN }, 181 { "603ev", MPC603ev, REVFMT_MAJMIN }, 182 { "604", MPC604, REVFMT_MAJMIN }, 183 { "604e", MPC604e, REVFMT_MAJMIN }, 184 { "604ev", MPC604ev, REVFMT_MAJMIN }, 185 { "620", MPC620, REVFMT_HEX }, 186 { "750", MPC750, REVFMT_MAJMIN }, 187 { "750FX", IBM750FX, REVFMT_MAJMIN }, 188 { "7400", MPC7400, REVFMT_MAJMIN }, 189 { "7410", MPC7410, REVFMT_MAJMIN }, 190 { "7450", MPC7450, REVFMT_MAJMIN }, 191 { "7455", MPC7455, REVFMT_MAJMIN }, 192 { "7457", MPC7457, REVFMT_MAJMIN }, 193 { "7447A", MPC7447A, REVFMT_MAJMIN }, 194 { "8240", MPC8240, REVFMT_MAJMIN }, 195 { "", 0, REVFMT_HEX } 196 }; 197 198 199 #ifdef MULTIPROCESSOR 200 struct cpu_info cpu_info[CPU_MAXNUM]; 201 #else 202 struct cpu_info cpu_info[1]; 203 #endif 204 205 int cpu_altivec; 206 int cpu_psluserset, cpu_pslusermod; 207 char cpu_model[80]; 208 209 void 210 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 211 { 212 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 213 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 214 (data & fmt->fmt_mask) == fmt->fmt_value) 215 aprint_normal("%s", fmt->fmt_string); 216 } 217 } 218 219 void 220 cpu_idlespin(void) 221 { 222 register_t msr; 223 224 if (powersave <= 0) 225 return; 226 227 __asm __volatile( 228 "sync;" 229 "mfmsr %0;" 230 "oris %0,%0,%1@h;" /* enter power saving mode */ 231 "mtmsr %0;" 232 "isync;" 233 : "=r"(msr) 234 : "J"(PSL_POW)); 235 } 236 237 void 238 cpu_probe_cache(void) 239 { 240 u_int assoc, pvr, vers; 241 242 pvr = mfpvr(); 243 vers = pvr >> 16; 244 245 switch (vers) { 246 #define K *1024 247 case IBM750FX: 248 case MPC601: 249 case MPC750: 250 case MPC7450: 251 case MPC7455: 252 case MPC7457: 253 curcpu()->ci_ci.dcache_size = 32 K; 254 curcpu()->ci_ci.icache_size = 32 K; 255 assoc = 8; 256 break; 257 case MPC603: 258 curcpu()->ci_ci.dcache_size = 8 K; 259 curcpu()->ci_ci.icache_size = 8 K; 260 assoc = 2; 261 break; 262 case MPC603e: 263 case MPC603ev: 264 case MPC604: 265 case MPC8240: 266 case MPC8245: 267 curcpu()->ci_ci.dcache_size = 16 K; 268 curcpu()->ci_ci.icache_size = 16 K; 269 assoc = 4; 270 break; 271 case MPC604e: 272 case MPC604ev: 273 curcpu()->ci_ci.dcache_size = 32 K; 274 curcpu()->ci_ci.icache_size = 32 K; 275 assoc = 4; 276 break; 277 default: 278 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 279 curcpu()->ci_ci.icache_size = PAGE_SIZE; 280 assoc = 1; 281 #undef K 282 } 283 284 /* Presently common across all implementations. */ 285 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 286 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 287 288 /* 289 * Possibly recolor. 290 */ 291 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 292 } 293 294 struct cpu_info * 295 cpu_attach_common(struct device *self, int id) 296 { 297 struct cpu_info *ci; 298 u_int pvr, vers; 299 300 ncpus++; 301 ci = &cpu_info[id]; 302 #ifndef MULTIPROCESSOR 303 /* 304 * If this isn't the primary CPU, print an error message 305 * and just bail out. 306 */ 307 if (id != 0) { 308 aprint_normal(": ID %d\n", id); 309 aprint_normal("%s: processor off-line; multiprocessor support " 310 "not present in kernel\n", self->dv_xname); 311 return (NULL); 312 } 313 #endif 314 315 ci->ci_cpuid = id; 316 ci->ci_intrdepth = -1; 317 ci->ci_dev = self; 318 ci->ci_idlespin = cpu_idlespin; 319 320 pvr = mfpvr(); 321 vers = (pvr >> 16) & 0xffff; 322 323 switch (id) { 324 case 0: 325 /* load my cpu_number to PIR */ 326 switch (vers) { 327 case MPC601: 328 case MPC604: 329 case MPC604e: 330 case MPC604ev: 331 case MPC7400: 332 case MPC7410: 333 case MPC7450: 334 case MPC7455: 335 case MPC7457: 336 mtspr(SPR_PIR, id); 337 } 338 cpu_setup(self, ci); 339 break; 340 default: 341 if (id >= CPU_MAXNUM) { 342 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 343 panic("cpuattach"); 344 } 345 #ifndef MULTIPROCESSOR 346 aprint_normal(" not configured\n"); 347 return NULL; 348 #endif 349 } 350 return (ci); 351 } 352 353 void 354 cpu_setup(self, ci) 355 struct device *self; 356 struct cpu_info *ci; 357 { 358 u_int hid0, pvr, vers; 359 char *bitmask, hidbuf[128]; 360 char model[80]; 361 362 pvr = mfpvr(); 363 vers = (pvr >> 16) & 0xffff; 364 365 cpu_identify(model, sizeof(model)); 366 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 367 cpu_number() == 0 ? " (primary)" : ""); 368 369 hid0 = mfspr(SPR_HID0); 370 cpu_probe_cache(); 371 372 /* 373 * Configure power-saving mode. 374 */ 375 switch (vers) { 376 case MPC604: 377 case MPC604e: 378 case MPC604ev: 379 /* 380 * Do not have HID0 support settings, but can support 381 * MSR[POW] off 382 */ 383 powersave = 1; 384 break; 385 386 case MPC603: 387 case MPC603e: 388 case MPC603ev: 389 case MPC750: 390 case IBM750FX: 391 case MPC7400: 392 case MPC7410: 393 case MPC8240: 394 case MPC8245: 395 /* Select DOZE mode. */ 396 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 397 hid0 |= HID0_DOZE | HID0_DPM; 398 powersave = 1; 399 break; 400 401 case MPC7457: 402 case MPC7455: 403 case MPC7450: 404 /* Enable the 7450 branch caches */ 405 hid0 |= HID0_SGE | HID0_BTIC; 406 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 407 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 408 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 409 hid0 &= ~HID0_BTIC; 410 /* Select NAP mode. */ 411 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 412 hid0 |= HID0_NAP | HID0_DPM; 413 powersave = 1; 414 break; 415 416 default: 417 /* No power-saving mode is available. */ ; 418 } 419 420 #ifdef NAPMODE 421 switch (vers) { 422 case IBM750FX: 423 case MPC750: 424 case MPC7400: 425 /* Select NAP mode. */ 426 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 427 hid0 |= HID0_NAP; 428 break; 429 } 430 #endif 431 432 switch (vers) { 433 case IBM750FX: 434 case MPC750: 435 hid0 &= ~HID0_DBP; /* XXX correct? */ 436 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 437 break; 438 439 case MPC7400: 440 case MPC7410: 441 hid0 &= ~HID0_SPD; 442 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 443 hid0 |= HID0_EIEC; 444 break; 445 } 446 447 mtspr(SPR_HID0, hid0); 448 449 switch (vers) { 450 case MPC601: 451 bitmask = HID0_601_BITMASK; 452 break; 453 case MPC7450: 454 case MPC7455: 455 case MPC7457: 456 bitmask = HID0_7450_BITMASK; 457 break; 458 default: 459 bitmask = HID0_BITMASK; 460 break; 461 } 462 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 463 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 464 465 /* 466 * Display speed and cache configuration. 467 */ 468 switch (vers) { 469 case MPC604: 470 case MPC604e: 471 case MPC604ev: 472 case MPC750: 473 case IBM750FX: 474 case MPC7400: 475 case MPC7410: 476 case MPC7450: 477 case MPC7455: 478 case MPC7457: 479 aprint_normal("%s: ", self->dv_xname); 480 cpu_print_speed(); 481 482 if (vers == IBM750FX || vers == MPC750 || 483 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 484 if (MPC745X_P(vers)) { 485 cpu_config_l3cr(vers); 486 } else { 487 cpu_config_l2cr(pvr); 488 } 489 } 490 aprint_normal("\n"); 491 break; 492 } 493 494 #if NSYSMON_ENVSYS > 0 495 /* 496 * Attach MPC750 temperature sensor to the envsys subsystem. 497 * XXX the 74xx series also has this sensor, but it is not 498 * XXX supported by Motorola and may return values that are off by 499 * XXX 35-55 degrees C. 500 */ 501 if (vers == MPC750 || vers == IBM750FX) 502 cpu_tau_setup(ci); 503 #endif 504 505 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 506 NULL, self->dv_xname, "clock"); 507 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 508 NULL, self->dv_xname, "soft clock"); 509 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 510 NULL, self->dv_xname, "soft net"); 511 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 512 NULL, self->dv_xname, "soft serial"); 513 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 514 NULL, self->dv_xname, "traps"); 515 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 516 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 517 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 518 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 519 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 520 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 521 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 522 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 523 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 524 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 525 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 526 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 527 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 528 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 529 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 530 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 531 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 532 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 533 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 534 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 535 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 536 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 537 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 538 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 539 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 540 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 541 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 542 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 543 #ifdef ALTIVEC 544 if (cpu_altivec) { 545 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 546 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 547 } 548 #endif 549 } 550 551 void 552 cpu_identify(char *str, size_t len) 553 { 554 u_int pvr, maj, min; 555 uint16_t vers, rev, revfmt; 556 const struct cputab *cp; 557 const char *name; 558 size_t n; 559 560 pvr = mfpvr(); 561 vers = pvr >> 16; 562 rev = pvr; 563 switch (vers) { 564 case MPC7410: 565 min = (pvr >> 0) & 0xff; 566 maj = min <= 4 ? 1 : 2; 567 break; 568 default: 569 maj = (pvr >> 8) & 0xf; 570 min = (pvr >> 0) & 0xf; 571 } 572 573 for (cp = models; cp->name[0] != '\0'; cp++) { 574 if (cp->version == vers) 575 break; 576 } 577 578 if (str == NULL) { 579 str = cpu_model; 580 len = sizeof(cpu_model); 581 cpu = vers; 582 } 583 584 revfmt = cp->revfmt; 585 name = cp->name; 586 if (rev == MPC750 && pvr == 15) { 587 name = "755"; 588 revfmt = REVFMT_HEX; 589 } 590 591 if (cp->name[0] != '\0') { 592 n = snprintf(str, len, "%s (Revision ", cp->name); 593 } else { 594 n = snprintf(str, len, "Version %#x (Revision ", vers); 595 } 596 if (len > n) { 597 switch (revfmt) { 598 case REVFMT_MAJMIN: 599 snprintf(str + n, len - n, "%u.%u)", maj, min); 600 break; 601 case REVFMT_HEX: 602 snprintf(str + n, len - n, "0x%04x)", rev); 603 break; 604 case REVFMT_DEC: 605 snprintf(str + n, len - n, "%u)", rev); 606 break; 607 } 608 } 609 } 610 611 #ifdef L2CR_CONFIG 612 u_int l2cr_config = L2CR_CONFIG; 613 #else 614 u_int l2cr_config = 0; 615 #endif 616 617 #ifdef L3CR_CONFIG 618 u_int l3cr_config = L3CR_CONFIG; 619 #else 620 u_int l3cr_config = 0; 621 #endif 622 623 void 624 cpu_enable_l2cr(register_t l2cr) 625 { 626 register_t msr, x; 627 628 /* Disable interrupts and set the cache config bits. */ 629 msr = mfmsr(); 630 mtmsr(msr & ~PSL_EE); 631 #ifdef ALTIVEC 632 if (cpu_altivec) 633 __asm __volatile("dssall"); 634 #endif 635 __asm __volatile("sync"); 636 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 637 __asm __volatile("sync"); 638 639 /* Wait for L2 clock to be stable (640 L2 clocks). */ 640 delay(100); 641 642 /* Invalidate all L2 contents. */ 643 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 644 do { 645 x = mfspr(SPR_L2CR); 646 } while (x & L2CR_L2IP); 647 648 /* Enable L2 cache. */ 649 l2cr |= L2CR_L2E; 650 mtspr(SPR_L2CR, l2cr); 651 mtmsr(msr); 652 } 653 654 void 655 cpu_enable_l3cr(register_t l3cr) 656 { 657 register_t x; 658 659 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 660 661 /* 662 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 663 * L3CLKEN. (also mask off reserved bits in case they were included 664 * in L3CR_CONFIG) 665 */ 666 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 667 mtspr(SPR_L3CR, l3cr); 668 669 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 670 l3cr |= 0x04000000; 671 mtspr(SPR_L3CR, l3cr); 672 673 /* 3: Set L3CLKEN to 1*/ 674 l3cr |= L3CR_L3CLKEN; 675 mtspr(SPR_L3CR, l3cr); 676 677 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 678 __asm __volatile("dssall;sync"); 679 /* L3 cache is already disabled, no need to clear L3E */ 680 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 681 do { 682 x = mfspr(SPR_L3CR); 683 } while (x & L3CR_L3I); 684 685 /* 6: Clear L3CLKEN to 0 */ 686 l3cr &= ~L3CR_L3CLKEN; 687 mtspr(SPR_L3CR, l3cr); 688 689 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 690 __asm __volatile("sync"); 691 delay(100); 692 693 /* 8: Set L3E and L3CLKEN */ 694 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 695 mtspr(SPR_L3CR, l3cr); 696 697 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 698 __asm __volatile("sync"); 699 delay(100); 700 } 701 702 void 703 cpu_config_l2cr(int pvr) 704 { 705 register_t l2cr; 706 707 l2cr = mfspr(SPR_L2CR); 708 709 /* 710 * For MP systems, the firmware may only configure the L2 cache 711 * on the first CPU. In this case, assume that the other CPUs 712 * should use the same value for L2CR. 713 */ 714 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 715 l2cr_config = l2cr; 716 } 717 718 /* 719 * Configure L2 cache if not enabled. 720 */ 721 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 722 cpu_enable_l2cr(l2cr_config); 723 l2cr = mfspr(SPR_L2CR); 724 } 725 726 if ((l2cr & L2CR_L2E) == 0) { 727 aprint_normal(" L2 cache present but not enabled "); 728 return; 729 } 730 731 aprint_normal(","); 732 if ((pvr >> 16) == IBM750FX || 733 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 734 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 735 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 736 } else { 737 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 738 } 739 } 740 741 void 742 cpu_config_l3cr(int vers) 743 { 744 register_t l2cr; 745 register_t l3cr; 746 747 l2cr = mfspr(SPR_L2CR); 748 749 /* 750 * For MP systems, the firmware may only configure the L2 cache 751 * on the first CPU. In this case, assume that the other CPUs 752 * should use the same value for L2CR. 753 */ 754 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 755 l2cr_config = l2cr; 756 } 757 758 /* 759 * Configure L2 cache if not enabled. 760 */ 761 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 762 cpu_enable_l2cr(l2cr_config); 763 l2cr = mfspr(SPR_L2CR); 764 } 765 766 aprint_normal(","); 767 cpu_fmttab_print(vers == MPC7457 768 ? cpu_7457_l2cr_formats : cpu_7450_l2cr_formats, l2cr); 769 770 l3cr = mfspr(SPR_L3CR); 771 772 /* 773 * For MP systems, the firmware may only configure the L3 cache 774 * on the first CPU. In this case, assume that the other CPUs 775 * should use the same value for L3CR. 776 */ 777 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 778 l3cr_config = l3cr; 779 } 780 781 /* 782 * Configure L3 cache if not enabled. 783 */ 784 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 785 cpu_enable_l3cr(l3cr_config); 786 l3cr = mfspr(SPR_L3CR); 787 } 788 789 if (l3cr & L3CR_L3E) { 790 aprint_normal(","); 791 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 792 } 793 } 794 795 void 796 cpu_print_speed(void) 797 { 798 uint64_t cps; 799 800 mtspr(SPR_MMCR0, MMCR0_FC); 801 mtspr(SPR_PMC1, 0); 802 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 803 delay(100000); 804 cps = (mfspr(SPR_PMC1) * 10) + 4999; 805 806 mtspr(SPR_MMCR0, MMCR0_FC); 807 808 aprint_normal("%lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 809 } 810 811 #if NSYSMON_ENVSYS > 0 812 const struct envsys_range cpu_tau_ranges[] = { 813 { 0, 0, ENVSYS_STEMP} 814 }; 815 816 struct envsys_basic_info cpu_tau_info[] = { 817 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 818 }; 819 820 void 821 cpu_tau_setup(struct cpu_info *ci) 822 { 823 struct { 824 struct sysmon_envsys sme; 825 struct envsys_tre_data tau_info; 826 } *datap; 827 int error; 828 829 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 830 831 ci->ci_sysmon_cookie = &datap->sme; 832 datap->sme.sme_nsensors = 1; 833 datap->sme.sme_envsys_version = 1000; 834 datap->sme.sme_ranges = cpu_tau_ranges; 835 datap->sme.sme_sensor_info = cpu_tau_info; 836 datap->sme.sme_sensor_data = &datap->tau_info; 837 838 datap->sme.sme_sensor_data->sensor = 0; 839 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 840 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 841 datap->sme.sme_cookie = ci; 842 datap->sme.sme_gtredata = cpu_tau_gtredata; 843 datap->sme.sme_streinfo = cpu_tau_streinfo; 844 datap->sme.sme_flags = 0; 845 846 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 847 aprint_error("%s: unable to register with sysmon (%d)\n", 848 ci->ci_dev->dv_xname, error); 849 } 850 851 852 /* Find the temperature of the CPU. */ 853 int 854 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 855 { 856 int i, threshold, count; 857 858 if (tred->sensor != 0) { 859 tred->validflags = 0; 860 return 0; 861 } 862 863 threshold = 64; /* Half of the 7-bit sensor range */ 864 mtspr(SPR_THRM1, 0); 865 mtspr(SPR_THRM2, 0); 866 /* XXX This counter is supposed to be "at least 20 microseonds, in 867 * XXX units of clock cycles". Since we don't have convenient 868 * XXX access to the CPU speed, set it to a conservative value, 869 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 870 * XXX the fastest G3 processor is 700MHz) . The cost is that 871 * XXX measuring the temperature takes a bit longer. 872 */ 873 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 874 875 /* Successive-approximation code adapted from Motorola 876 * application note AN1800/D, "Programming the Thermal Assist 877 * Unit in the MPC750 Microprocessor". 878 */ 879 for (i = 4; i >= 0 ; i--) { 880 mtspr(SPR_THRM1, 881 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 882 count = 0; 883 while ((count < 100) && 884 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 885 count++; 886 delay(1); 887 } 888 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 889 /* The interrupt bit was set, meaning the 890 * temperature was above the threshold 891 */ 892 threshold += 2 << i; 893 } else { 894 /* Temperature was below the threshold */ 895 threshold -= 2 << i; 896 } 897 } 898 threshold += 2; 899 900 /* Convert the temperature in degrees C to microkelvin */ 901 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 902 903 *tred = *sme->sme_sensor_data; 904 905 return 0; 906 } 907 908 int 909 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 910 { 911 912 /* There is nothing to set here. */ 913 return (EINVAL); 914 } 915 #endif /* NSYSMON_ENVSYS > 0 */ 916
Indexes created Tue Sep 23 07:09:52 GMT 2025