cpu_subr.c revision 1.22
1 /* $NetBSD: cpu_subr.c,v 1.22 2005/01/21 00:58:34 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.22 2005/01/21 00:58:34 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_print_speed(void); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0 } 87 }; 88 89 static const struct fmttab cpu_7448_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 1MB L2 cache" }, 95 { 0 } 96 }; 97 98 static const struct fmttab cpu_7457_l2cr_formats[] = { 99 { L2CR_L2E, 0, " disabled" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 103 { L2CR_L2E, ~0, " 512KB L2 cache" }, 104 { 0 } 105 }; 106 107 static const struct fmttab cpu_7450_l3cr_formats[] = { 108 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 109 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 110 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 111 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 112 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 113 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 114 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 115 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 116 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 117 { L3CR_L3SIZ, ~0, " L3 cache" }, 118 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 119 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 120 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 121 { L3CR_L3CLK, ~0, " at" }, 122 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 123 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 124 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 125 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 126 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 127 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 128 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 129 { L3CR_L3CLK, ~0, " ratio" }, 130 { 0, 0 }, 131 }; 132 133 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 134 { L2CR_L2E, 0, " disabled" }, 135 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 136 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 137 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 138 { 0, ~0, " 512KB" }, 139 { L2CR_L2WT, L2CR_L2WT, " WT" }, 140 { L2CR_L2WT, 0, " WB" }, 141 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 142 { 0, ~0, " L2 cache" }, 143 { 0 } 144 }; 145 146 static const struct fmttab cpu_l2cr_formats[] = { 147 { L2CR_L2E, 0, " disabled" }, 148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 151 { L2CR_L2PE, L2CR_L2PE, " parity" }, 152 { L2CR_L2PE, 0, " no-parity" }, 153 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 154 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 155 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 156 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 157 { L2CR_L2WT, L2CR_L2WT, " WT" }, 158 { L2CR_L2WT, 0, " WB" }, 159 { L2CR_L2E, ~0, " L2 cache" }, 160 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 161 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 162 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 163 { L2CR_L2CLK, ~0, " at" }, 164 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 165 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 166 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 167 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 168 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 169 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 170 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 171 { L2CR_L2CLK, ~0, " ratio" }, 172 { 0 } 173 }; 174 175 static void cpu_fmttab_print(const struct fmttab *, register_t); 176 177 struct cputab { 178 const char name[8]; 179 uint16_t version; 180 uint16_t revfmt; 181 }; 182 #define REVFMT_MAJMIN 1 /* %u.%u */ 183 #define REVFMT_HEX 2 /* 0x%04x */ 184 #define REVFMT_DEC 3 /* %u */ 185 static const struct cputab models[] = { 186 { "601", MPC601, REVFMT_DEC }, 187 { "602", MPC602, REVFMT_DEC }, 188 { "603", MPC603, REVFMT_MAJMIN }, 189 { "603e", MPC603e, REVFMT_MAJMIN }, 190 { "603ev", MPC603ev, REVFMT_MAJMIN }, 191 { "604", MPC604, REVFMT_MAJMIN }, 192 { "604e", MPC604e, REVFMT_MAJMIN }, 193 { "604ev", MPC604ev, REVFMT_MAJMIN }, 194 { "620", MPC620, REVFMT_HEX }, 195 { "750", MPC750, REVFMT_MAJMIN }, 196 { "750FX", IBM750FX, REVFMT_MAJMIN }, 197 { "7400", MPC7400, REVFMT_MAJMIN }, 198 { "7410", MPC7410, REVFMT_MAJMIN }, 199 { "7450", MPC7450, REVFMT_MAJMIN }, 200 { "7455", MPC7455, REVFMT_MAJMIN }, 201 { "7457", MPC7457, REVFMT_MAJMIN }, 202 { "7447A", MPC7447A, REVFMT_MAJMIN }, 203 { "7448", MPC7448, REVFMT_MAJMIN }, 204 { "8240", MPC8240, REVFMT_MAJMIN }, 205 { "", 0, REVFMT_HEX } 206 }; 207 208 209 #ifdef MULTIPROCESSOR 210 struct cpu_info cpu_info[CPU_MAXNUM]; 211 #else 212 struct cpu_info cpu_info[1]; 213 #endif 214 215 int cpu_altivec; 216 int cpu_psluserset, cpu_pslusermod; 217 char cpu_model[80]; 218 219 void 220 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 221 { 222 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 223 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 224 (data & fmt->fmt_mask) == fmt->fmt_value) 225 aprint_normal("%s", fmt->fmt_string); 226 } 227 } 228 229 void 230 cpu_idlespin(void) 231 { 232 register_t msr; 233 234 if (powersave <= 0) 235 return; 236 237 __asm __volatile( 238 "sync;" 239 "mfmsr %0;" 240 "oris %0,%0,%1@h;" /* enter power saving mode */ 241 "mtmsr %0;" 242 "isync;" 243 : "=r"(msr) 244 : "J"(PSL_POW)); 245 } 246 247 void 248 cpu_probe_cache(void) 249 { 250 u_int assoc, pvr, vers; 251 252 pvr = mfpvr(); 253 vers = pvr >> 16; 254 255 switch (vers) { 256 #define K *1024 257 case IBM750FX: 258 case MPC601: 259 case MPC750: 260 case MPC7447A: 261 case MPC7448: 262 case MPC7450: 263 case MPC7455: 264 case MPC7457: 265 curcpu()->ci_ci.dcache_size = 32 K; 266 curcpu()->ci_ci.icache_size = 32 K; 267 assoc = 8; 268 break; 269 case MPC603: 270 curcpu()->ci_ci.dcache_size = 8 K; 271 curcpu()->ci_ci.icache_size = 8 K; 272 assoc = 2; 273 break; 274 case MPC603e: 275 case MPC603ev: 276 case MPC604: 277 case MPC8240: 278 case MPC8245: 279 curcpu()->ci_ci.dcache_size = 16 K; 280 curcpu()->ci_ci.icache_size = 16 K; 281 assoc = 4; 282 break; 283 case MPC604e: 284 case MPC604ev: 285 curcpu()->ci_ci.dcache_size = 32 K; 286 curcpu()->ci_ci.icache_size = 32 K; 287 assoc = 4; 288 break; 289 default: 290 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 291 curcpu()->ci_ci.icache_size = PAGE_SIZE; 292 assoc = 1; 293 #undef K 294 } 295 296 /* Presently common across all implementations. */ 297 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 298 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 299 300 /* 301 * Possibly recolor. 302 */ 303 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 304 } 305 306 struct cpu_info * 307 cpu_attach_common(struct device *self, int id) 308 { 309 struct cpu_info *ci; 310 u_int pvr, vers; 311 312 ncpus++; 313 ci = &cpu_info[id]; 314 #ifndef MULTIPROCESSOR 315 /* 316 * If this isn't the primary CPU, print an error message 317 * and just bail out. 318 */ 319 if (id != 0) { 320 aprint_normal(": ID %d\n", id); 321 aprint_normal("%s: processor off-line; multiprocessor support " 322 "not present in kernel\n", self->dv_xname); 323 return (NULL); 324 } 325 #endif 326 327 ci->ci_cpuid = id; 328 ci->ci_intrdepth = -1; 329 ci->ci_dev = self; 330 ci->ci_idlespin = cpu_idlespin; 331 332 pvr = mfpvr(); 333 vers = (pvr >> 16) & 0xffff; 334 335 switch (id) { 336 case 0: 337 /* load my cpu_number to PIR */ 338 switch (vers) { 339 case MPC601: 340 case MPC604: 341 case MPC604e: 342 case MPC604ev: 343 case MPC7400: 344 case MPC7410: 345 case MPC7447A: 346 case MPC7448: 347 case MPC7450: 348 case MPC7455: 349 case MPC7457: 350 mtspr(SPR_PIR, id); 351 } 352 cpu_setup(self, ci); 353 break; 354 default: 355 if (id >= CPU_MAXNUM) { 356 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 357 panic("cpuattach"); 358 } 359 #ifndef MULTIPROCESSOR 360 aprint_normal(" not configured\n"); 361 return NULL; 362 #endif 363 } 364 return (ci); 365 } 366 367 void 368 cpu_setup(self, ci) 369 struct device *self; 370 struct cpu_info *ci; 371 { 372 u_int hid0, pvr, vers; 373 char *bitmask, hidbuf[128]; 374 char model[80]; 375 376 pvr = mfpvr(); 377 vers = (pvr >> 16) & 0xffff; 378 379 cpu_identify(model, sizeof(model)); 380 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 381 cpu_number() == 0 ? " (primary)" : ""); 382 383 hid0 = mfspr(SPR_HID0); 384 cpu_probe_cache(); 385 386 /* 387 * Configure power-saving mode. 388 */ 389 switch (vers) { 390 case MPC604: 391 case MPC604e: 392 case MPC604ev: 393 /* 394 * Do not have HID0 support settings, but can support 395 * MSR[POW] off 396 */ 397 powersave = 1; 398 break; 399 400 case MPC603: 401 case MPC603e: 402 case MPC603ev: 403 case MPC750: 404 case IBM750FX: 405 case MPC7400: 406 case MPC7410: 407 case MPC8240: 408 case MPC8245: 409 /* Select DOZE mode. */ 410 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 411 hid0 |= HID0_DOZE | HID0_DPM; 412 powersave = 1; 413 break; 414 415 case MPC7447A: 416 case MPC7448: 417 case MPC7457: 418 case MPC7455: 419 case MPC7450: 420 /* Enable the 7450 branch caches */ 421 hid0 |= HID0_SGE | HID0_BTIC; 422 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 423 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 424 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 425 hid0 &= ~HID0_BTIC; 426 /* Select NAP mode. */ 427 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 428 hid0 |= HID0_NAP | HID0_DPM /* | HID0_XBSEN */; 429 powersave = 1; 430 break; 431 432 default: 433 /* No power-saving mode is available. */ ; 434 } 435 436 #ifdef NAPMODE 437 switch (vers) { 438 case IBM750FX: 439 case MPC750: 440 case MPC7400: 441 /* Select NAP mode. */ 442 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 443 hid0 |= HID0_NAP; 444 break; 445 } 446 #endif 447 448 switch (vers) { 449 case IBM750FX: 450 case MPC750: 451 hid0 &= ~HID0_DBP; /* XXX correct? */ 452 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 453 break; 454 455 case MPC7400: 456 case MPC7410: 457 hid0 &= ~HID0_SPD; 458 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 459 hid0 |= HID0_EIEC; 460 break; 461 } 462 463 mtspr(SPR_HID0, hid0); 464 __asm __volatile("sync;isync"); 465 466 switch (vers) { 467 case MPC601: 468 bitmask = HID0_601_BITMASK; 469 break; 470 case MPC7450: 471 case MPC7455: 472 case MPC7457: 473 bitmask = HID0_7450_BITMASK; 474 break; 475 default: 476 bitmask = HID0_BITMASK; 477 break; 478 } 479 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 480 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 481 482 /* 483 * Display speed and cache configuration. 484 */ 485 switch (vers) { 486 case MPC604: 487 case MPC604e: 488 case MPC604ev: 489 case MPC750: 490 case IBM750FX: 491 case MPC7400: 492 case MPC7410: 493 case MPC7447A: 494 case MPC7448: 495 case MPC7450: 496 case MPC7455: 497 case MPC7457: 498 aprint_normal("%s: ", self->dv_xname); 499 cpu_print_speed(); 500 501 if (vers == IBM750FX || vers == MPC750 || 502 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 503 if (MPC745X_P(vers)) { 504 cpu_config_l3cr(vers); 505 } else { 506 cpu_config_l2cr(pvr); 507 } 508 } 509 aprint_normal("\n"); 510 break; 511 } 512 513 #if NSYSMON_ENVSYS > 0 514 /* 515 * Attach MPC750 temperature sensor to the envsys subsystem. 516 * XXX the 74xx series also has this sensor, but it is not 517 * XXX supported by Motorola and may return values that are off by 518 * XXX 35-55 degrees C. 519 */ 520 if (vers == MPC750 || vers == IBM750FX) 521 cpu_tau_setup(ci); 522 #endif 523 524 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 525 NULL, self->dv_xname, "clock"); 526 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 527 NULL, self->dv_xname, "soft clock"); 528 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 529 NULL, self->dv_xname, "soft net"); 530 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 531 NULL, self->dv_xname, "soft serial"); 532 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 533 NULL, self->dv_xname, "traps"); 534 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 535 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 536 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 537 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 538 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 539 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 540 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 541 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 542 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 543 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 544 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 545 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 546 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 547 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 548 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 549 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 550 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 551 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 552 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 553 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 554 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 555 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 556 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 557 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 558 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 559 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 560 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 561 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 562 #ifdef ALTIVEC 563 if (cpu_altivec) { 564 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 565 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 566 } 567 #endif 568 } 569 570 void 571 cpu_identify(char *str, size_t len) 572 { 573 u_int pvr, maj, min; 574 uint16_t vers, rev, revfmt; 575 const struct cputab *cp; 576 const char *name; 577 size_t n; 578 579 pvr = mfpvr(); 580 vers = pvr >> 16; 581 rev = pvr; 582 switch (vers) { 583 case MPC7410: 584 min = (pvr >> 0) & 0xff; 585 maj = min <= 4 ? 1 : 2; 586 break; 587 default: 588 maj = (pvr >> 8) & 0xf; 589 min = (pvr >> 0) & 0xf; 590 } 591 592 for (cp = models; cp->name[0] != '\0'; cp++) { 593 if (cp->version == vers) 594 break; 595 } 596 597 if (str == NULL) { 598 str = cpu_model; 599 len = sizeof(cpu_model); 600 cpu = vers; 601 } 602 603 revfmt = cp->revfmt; 604 name = cp->name; 605 if (rev == MPC750 && pvr == 15) { 606 name = "755"; 607 revfmt = REVFMT_HEX; 608 } 609 610 if (cp->name[0] != '\0') { 611 n = snprintf(str, len, "%s (Revision ", cp->name); 612 } else { 613 n = snprintf(str, len, "Version %#x (Revision ", vers); 614 } 615 if (len > n) { 616 switch (revfmt) { 617 case REVFMT_MAJMIN: 618 snprintf(str + n, len - n, "%u.%u)", maj, min); 619 break; 620 case REVFMT_HEX: 621 snprintf(str + n, len - n, "0x%04x)", rev); 622 break; 623 case REVFMT_DEC: 624 snprintf(str + n, len - n, "%u)", rev); 625 break; 626 } 627 } 628 } 629 630 #ifdef L2CR_CONFIG 631 u_int l2cr_config = L2CR_CONFIG; 632 #else 633 u_int l2cr_config = 0; 634 #endif 635 636 #ifdef L3CR_CONFIG 637 u_int l3cr_config = L3CR_CONFIG; 638 #else 639 u_int l3cr_config = 0; 640 #endif 641 642 void 643 cpu_enable_l2cr(register_t l2cr) 644 { 645 register_t msr, x; 646 647 /* Disable interrupts and set the cache config bits. */ 648 msr = mfmsr(); 649 mtmsr(msr & ~PSL_EE); 650 #ifdef ALTIVEC 651 if (cpu_altivec) 652 __asm __volatile("dssall"); 653 #endif 654 __asm __volatile("sync"); 655 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 656 __asm __volatile("sync"); 657 658 /* Wait for L2 clock to be stable (640 L2 clocks). */ 659 delay(100); 660 661 /* Invalidate all L2 contents. */ 662 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 663 do { 664 x = mfspr(SPR_L2CR); 665 } while (x & L2CR_L2IP); 666 667 /* Enable L2 cache. */ 668 l2cr |= L2CR_L2E; 669 mtspr(SPR_L2CR, l2cr); 670 mtmsr(msr); 671 } 672 673 void 674 cpu_enable_l3cr(register_t l3cr) 675 { 676 register_t x; 677 678 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 679 680 /* 681 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 682 * L3CLKEN. (also mask off reserved bits in case they were included 683 * in L3CR_CONFIG) 684 */ 685 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 686 mtspr(SPR_L3CR, l3cr); 687 688 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 689 l3cr |= 0x04000000; 690 mtspr(SPR_L3CR, l3cr); 691 692 /* 3: Set L3CLKEN to 1*/ 693 l3cr |= L3CR_L3CLKEN; 694 mtspr(SPR_L3CR, l3cr); 695 696 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 697 __asm __volatile("dssall;sync"); 698 /* L3 cache is already disabled, no need to clear L3E */ 699 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 700 do { 701 x = mfspr(SPR_L3CR); 702 } while (x & L3CR_L3I); 703 704 /* 6: Clear L3CLKEN to 0 */ 705 l3cr &= ~L3CR_L3CLKEN; 706 mtspr(SPR_L3CR, l3cr); 707 708 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 709 __asm __volatile("sync"); 710 delay(100); 711 712 /* 8: Set L3E and L3CLKEN */ 713 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 714 mtspr(SPR_L3CR, l3cr); 715 716 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 717 __asm __volatile("sync"); 718 delay(100); 719 } 720 721 void 722 cpu_config_l2cr(int pvr) 723 { 724 register_t l2cr; 725 726 l2cr = mfspr(SPR_L2CR); 727 728 /* 729 * For MP systems, the firmware may only configure the L2 cache 730 * on the first CPU. In this case, assume that the other CPUs 731 * should use the same value for L2CR. 732 */ 733 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 734 l2cr_config = l2cr; 735 } 736 737 /* 738 * Configure L2 cache if not enabled. 739 */ 740 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 741 cpu_enable_l2cr(l2cr_config); 742 l2cr = mfspr(SPR_L2CR); 743 } 744 745 if ((l2cr & L2CR_L2E) == 0) { 746 aprint_normal(" L2 cache present but not enabled "); 747 return; 748 } 749 750 aprint_normal(","); 751 if ((pvr >> 16) == IBM750FX || 752 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 753 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 754 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 755 } else { 756 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 757 } 758 } 759 760 void 761 cpu_config_l3cr(int vers) 762 { 763 register_t l2cr; 764 register_t l3cr; 765 766 l2cr = mfspr(SPR_L2CR); 767 768 /* 769 * For MP systems, the firmware may only configure the L2 cache 770 * on the first CPU. In this case, assume that the other CPUs 771 * should use the same value for L2CR. 772 */ 773 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 774 l2cr_config = l2cr; 775 } 776 777 /* 778 * Configure L2 cache if not enabled. 779 */ 780 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 781 cpu_enable_l2cr(l2cr_config); 782 l2cr = mfspr(SPR_L2CR); 783 } 784 785 aprint_normal(","); 786 switch (vers) { 787 case MPC7447A: 788 case MPC7457: 789 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 790 return; 791 case MPC7448: 792 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 793 return; 794 default: 795 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 796 break; 797 } 798 799 l3cr = mfspr(SPR_L3CR); 800 801 /* 802 * For MP systems, the firmware may only configure the L3 cache 803 * on the first CPU. In this case, assume that the other CPUs 804 * should use the same value for L3CR. 805 */ 806 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 807 l3cr_config = l3cr; 808 } 809 810 /* 811 * Configure L3 cache if not enabled. 812 */ 813 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 814 cpu_enable_l3cr(l3cr_config); 815 l3cr = mfspr(SPR_L3CR); 816 } 817 818 if (l3cr & L3CR_L3E) { 819 aprint_normal(","); 820 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 821 } 822 } 823 824 void 825 cpu_print_speed(void) 826 { 827 uint64_t cps; 828 829 mtspr(SPR_MMCR0, MMCR0_FC); 830 mtspr(SPR_PMC1, 0); 831 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 832 delay(100000); 833 cps = (mfspr(SPR_PMC1) * 10) + 4999; 834 835 mtspr(SPR_MMCR0, MMCR0_FC); 836 837 aprint_normal("%lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 838 } 839 840 #if NSYSMON_ENVSYS > 0 841 const struct envsys_range cpu_tau_ranges[] = { 842 { 0, 0, ENVSYS_STEMP} 843 }; 844 845 struct envsys_basic_info cpu_tau_info[] = { 846 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 847 }; 848 849 void 850 cpu_tau_setup(struct cpu_info *ci) 851 { 852 struct { 853 struct sysmon_envsys sme; 854 struct envsys_tre_data tau_info; 855 } *datap; 856 int error; 857 858 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 859 860 ci->ci_sysmon_cookie = &datap->sme; 861 datap->sme.sme_nsensors = 1; 862 datap->sme.sme_envsys_version = 1000; 863 datap->sme.sme_ranges = cpu_tau_ranges; 864 datap->sme.sme_sensor_info = cpu_tau_info; 865 datap->sme.sme_sensor_data = &datap->tau_info; 866 867 datap->sme.sme_sensor_data->sensor = 0; 868 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 869 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 870 datap->sme.sme_cookie = ci; 871 datap->sme.sme_gtredata = cpu_tau_gtredata; 872 datap->sme.sme_streinfo = cpu_tau_streinfo; 873 datap->sme.sme_flags = 0; 874 875 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 876 aprint_error("%s: unable to register with sysmon (%d)\n", 877 ci->ci_dev->dv_xname, error); 878 } 879 880 881 /* Find the temperature of the CPU. */ 882 int 883 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 884 { 885 int i, threshold, count; 886 887 if (tred->sensor != 0) { 888 tred->validflags = 0; 889 return 0; 890 } 891 892 threshold = 64; /* Half of the 7-bit sensor range */ 893 mtspr(SPR_THRM1, 0); 894 mtspr(SPR_THRM2, 0); 895 /* XXX This counter is supposed to be "at least 20 microseonds, in 896 * XXX units of clock cycles". Since we don't have convenient 897 * XXX access to the CPU speed, set it to a conservative value, 898 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 899 * XXX the fastest G3 processor is 700MHz) . The cost is that 900 * XXX measuring the temperature takes a bit longer. 901 */ 902 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 903 904 /* Successive-approximation code adapted from Motorola 905 * application note AN1800/D, "Programming the Thermal Assist 906 * Unit in the MPC750 Microprocessor". 907 */ 908 for (i = 4; i >= 0 ; i--) { 909 mtspr(SPR_THRM1, 910 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 911 count = 0; 912 while ((count < 100) && 913 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 914 count++; 915 delay(1); 916 } 917 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 918 /* The interrupt bit was set, meaning the 919 * temperature was above the threshold 920 */ 921 threshold += 2 << i; 922 } else { 923 /* Temperature was below the threshold */ 924 threshold -= 2 << i; 925 } 926 } 927 threshold += 2; 928 929 /* Convert the temperature in degrees C to microkelvin */ 930 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 931 932 *tred = *sme->sme_sensor_data; 933 934 return 0; 935 } 936 937 int 938 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 939 { 940 941 /* There is nothing to set here. */ 942 return (EINVAL); 943 } 944 #endif /* NSYSMON_ENVSYS > 0 */ 945
Indexes created Tue Sep 23 07:09:52 GMT 2025