cpu_subr.c revision 1.27
1 /* $NetBSD: cpu_subr.c,v 1.27 2006/08/05 21:26:49 sanjayl Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.27 2006/08/05 21:26:49 sanjayl Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_probe_speed(struct cpu_info *); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0 } 87 }; 88 89 static const struct fmttab cpu_7448_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 1MB L2 cache" }, 95 { 0 } 96 }; 97 98 static const struct fmttab cpu_7457_l2cr_formats[] = { 99 { L2CR_L2E, 0, " disabled" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 103 { L2CR_L2E, ~0, " 512KB L2 cache" }, 104 { 0 } 105 }; 106 107 static const struct fmttab cpu_7450_l3cr_formats[] = { 108 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 109 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 110 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 111 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 112 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 113 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 114 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 115 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 116 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 117 { L3CR_L3SIZ, ~0, " L3 cache" }, 118 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 119 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 120 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 121 { L3CR_L3CLK, ~0, " at" }, 122 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 123 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 124 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 125 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 126 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 127 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 128 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 129 { L3CR_L3CLK, ~0, " ratio" }, 130 { 0, 0 }, 131 }; 132 133 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 134 { L2CR_L2E, 0, " disabled" }, 135 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 136 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 137 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 138 { 0, ~0, " 512KB" }, 139 { L2CR_L2WT, L2CR_L2WT, " WT" }, 140 { L2CR_L2WT, 0, " WB" }, 141 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 142 { 0, ~0, " L2 cache" }, 143 { 0 } 144 }; 145 146 static const struct fmttab cpu_l2cr_formats[] = { 147 { L2CR_L2E, 0, " disabled" }, 148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 151 { L2CR_L2PE, L2CR_L2PE, " parity" }, 152 { L2CR_L2PE, 0, " no-parity" }, 153 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 154 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 155 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 156 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 157 { L2CR_L2WT, L2CR_L2WT, " WT" }, 158 { L2CR_L2WT, 0, " WB" }, 159 { L2CR_L2E, ~0, " L2 cache" }, 160 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 161 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 162 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 163 { L2CR_L2CLK, ~0, " at" }, 164 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 165 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 166 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 167 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 168 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 169 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 170 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 171 { L2CR_L2CLK, ~0, " ratio" }, 172 { 0 } 173 }; 174 175 static void cpu_fmttab_print(const struct fmttab *, register_t); 176 177 struct cputab { 178 const char name[8]; 179 uint16_t version; 180 uint16_t revfmt; 181 }; 182 #define REVFMT_MAJMIN 1 /* %u.%u */ 183 #define REVFMT_HEX 2 /* 0x%04x */ 184 #define REVFMT_DEC 3 /* %u */ 185 static const struct cputab models[] = { 186 { "601", MPC601, REVFMT_DEC }, 187 { "602", MPC602, REVFMT_DEC }, 188 { "603", MPC603, REVFMT_MAJMIN }, 189 { "603e", MPC603e, REVFMT_MAJMIN }, 190 { "603ev", MPC603ev, REVFMT_MAJMIN }, 191 { "604", MPC604, REVFMT_MAJMIN }, 192 { "604e", MPC604e, REVFMT_MAJMIN }, 193 { "604ev", MPC604ev, REVFMT_MAJMIN }, 194 { "620", MPC620, REVFMT_HEX }, 195 { "750", MPC750, REVFMT_MAJMIN }, 196 { "750FX", IBM750FX, REVFMT_MAJMIN }, 197 { "7400", MPC7400, REVFMT_MAJMIN }, 198 { "7410", MPC7410, REVFMT_MAJMIN }, 199 { "7450", MPC7450, REVFMT_MAJMIN }, 200 { "7455", MPC7455, REVFMT_MAJMIN }, 201 { "7457", MPC7457, REVFMT_MAJMIN }, 202 { "7447A", MPC7447A, REVFMT_MAJMIN }, 203 { "7448", MPC7448, REVFMT_MAJMIN }, 204 { "8240", MPC8240, REVFMT_MAJMIN }, 205 { "970", IBM970, REVFMT_MAJMIN }, 206 { "970FX", IBM970FX, REVFMT_MAJMIN }, 207 { "", 0, REVFMT_HEX } 208 }; 209 210 211 #ifdef MULTIPROCESSOR 212 struct cpu_info cpu_info[CPU_MAXNUM]; 213 #else 214 struct cpu_info cpu_info[1]; 215 #endif 216 217 int cpu_altivec; 218 int cpu_psluserset, cpu_pslusermod; 219 char cpu_model[80]; 220 221 void 222 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 223 { 224 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 225 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 226 (data & fmt->fmt_mask) == fmt->fmt_value) 227 aprint_normal("%s", fmt->fmt_string); 228 } 229 } 230 231 void 232 cpu_idlespin(void) 233 { 234 register_t msr; 235 236 if (powersave <= 0) 237 return; 238 239 __asm volatile( 240 "sync;" 241 "mfmsr %0;" 242 "oris %0,%0,%1@h;" /* enter power saving mode */ 243 "mtmsr %0;" 244 "isync;" 245 : "=r"(msr) 246 : "J"(PSL_POW)); 247 } 248 249 void 250 cpu_probe_cache(void) 251 { 252 u_int assoc, pvr, vers; 253 254 pvr = mfpvr(); 255 vers = pvr >> 16; 256 257 258 /* Presently common across almost all implementations. */ 259 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 260 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 261 262 263 switch (vers) { 264 #define K *1024 265 case IBM750FX: 266 case MPC601: 267 case MPC750: 268 case MPC7447A: 269 case MPC7448: 270 case MPC7450: 271 case MPC7455: 272 case MPC7457: 273 curcpu()->ci_ci.dcache_size = 32 K; 274 curcpu()->ci_ci.icache_size = 32 K; 275 assoc = 8; 276 break; 277 case MPC603: 278 curcpu()->ci_ci.dcache_size = 8 K; 279 curcpu()->ci_ci.icache_size = 8 K; 280 assoc = 2; 281 break; 282 case MPC603e: 283 case MPC603ev: 284 case MPC604: 285 case MPC8240: 286 case MPC8245: 287 curcpu()->ci_ci.dcache_size = 16 K; 288 curcpu()->ci_ci.icache_size = 16 K; 289 assoc = 4; 290 break; 291 case MPC604e: 292 case MPC604ev: 293 curcpu()->ci_ci.dcache_size = 32 K; 294 curcpu()->ci_ci.icache_size = 32 K; 295 assoc = 4; 296 break; 297 case IBM970: 298 case IBM970FX: 299 curcpu()->ci_ci.dcache_size = 32 K; 300 curcpu()->ci_ci.icache_size = 64 K; 301 curcpu()->ci_ci.dcache_line_size = 128; 302 curcpu()->ci_ci.icache_line_size = 128; 303 assoc = 2; 304 break; 305 306 default: 307 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 308 curcpu()->ci_ci.icache_size = PAGE_SIZE; 309 assoc = 1; 310 #undef K 311 } 312 313 /* 314 * Possibly recolor. 315 */ 316 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 317 } 318 319 struct cpu_info * 320 cpu_attach_common(struct device *self, int id) 321 { 322 struct cpu_info *ci; 323 u_int pvr, vers; 324 325 ncpus++; 326 ci = &cpu_info[id]; 327 #ifndef MULTIPROCESSOR 328 /* 329 * If this isn't the primary CPU, print an error message 330 * and just bail out. 331 */ 332 if (id != 0) { 333 aprint_normal(": ID %d\n", id); 334 aprint_normal("%s: processor off-line; multiprocessor support " 335 "not present in kernel\n", self->dv_xname); 336 return (NULL); 337 } 338 #endif 339 340 ci->ci_cpuid = id; 341 ci->ci_intrdepth = -1; 342 ci->ci_dev = self; 343 ci->ci_idlespin = cpu_idlespin; 344 345 pvr = mfpvr(); 346 vers = (pvr >> 16) & 0xffff; 347 348 switch (id) { 349 case 0: 350 /* load my cpu_number to PIR */ 351 switch (vers) { 352 case MPC601: 353 case MPC604: 354 case MPC604e: 355 case MPC604ev: 356 case MPC7400: 357 case MPC7410: 358 case MPC7447A: 359 case MPC7448: 360 case MPC7450: 361 case MPC7455: 362 case MPC7457: 363 mtspr(SPR_PIR, id); 364 } 365 cpu_setup(self, ci); 366 break; 367 default: 368 if (id >= CPU_MAXNUM) { 369 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 370 panic("cpuattach"); 371 } 372 #ifndef MULTIPROCESSOR 373 aprint_normal(" not configured\n"); 374 return NULL; 375 #endif 376 } 377 return (ci); 378 } 379 380 void 381 cpu_setup(self, ci) 382 struct device *self; 383 struct cpu_info *ci; 384 { 385 u_int hid0, pvr, vers; 386 const char *bitmask; 387 char hidbuf[128]; 388 char model[80]; 389 390 pvr = mfpvr(); 391 vers = (pvr >> 16) & 0xffff; 392 393 cpu_identify(model, sizeof(model)); 394 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 395 cpu_number() == 0 ? " (primary)" : ""); 396 397 #if defined (PPC_OEA) || defined (PPC_OEA64) 398 hid0 = mfspr(SPR_HID0); 399 #elif defined (PPC_OEA64_BRIDGE) 400 hid0 = mfspr(SPR_HID0); 401 #endif 402 403 cpu_probe_cache(); 404 405 /* 406 * Configure power-saving mode. 407 */ 408 switch (vers) { 409 case MPC604: 410 case MPC604e: 411 case MPC604ev: 412 /* 413 * Do not have HID0 support settings, but can support 414 * MSR[POW] off 415 */ 416 powersave = 1; 417 break; 418 419 case MPC603: 420 case MPC603e: 421 case MPC603ev: 422 case MPC750: 423 case IBM750FX: 424 case MPC7400: 425 case MPC7410: 426 case MPC8240: 427 case MPC8245: 428 /* Select DOZE mode. */ 429 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 430 hid0 |= HID0_DOZE | HID0_DPM; 431 powersave = 1; 432 break; 433 434 case MPC7447A: 435 case MPC7448: 436 case MPC7457: 437 case MPC7455: 438 case MPC7450: 439 /* Enable the 7450 branch caches */ 440 hid0 |= HID0_SGE | HID0_BTIC; 441 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 442 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 443 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 444 hid0 &= ~HID0_BTIC; 445 /* Select NAP mode. */ 446 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 447 hid0 |= HID0_NAP | HID0_DPM /* | HID0_XBSEN */; 448 powersave = 1; 449 break; 450 451 case IBM970: 452 case IBM970FX: 453 default: 454 /* No power-saving mode is available. */ ; 455 } 456 457 #ifdef NAPMODE 458 switch (vers) { 459 case IBM750FX: 460 case MPC750: 461 case MPC7400: 462 /* Select NAP mode. */ 463 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 464 hid0 |= HID0_NAP; 465 break; 466 } 467 #endif 468 469 switch (vers) { 470 case IBM750FX: 471 case MPC750: 472 hid0 &= ~HID0_DBP; /* XXX correct? */ 473 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 474 break; 475 476 case MPC7400: 477 case MPC7410: 478 hid0 &= ~HID0_SPD; 479 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 480 hid0 |= HID0_EIEC; 481 break; 482 } 483 484 #if defined (PPC_OEA) 485 mtspr(SPR_HID0, hid0); 486 __asm volatile("sync;isync"); 487 #endif 488 489 switch (vers) { 490 case MPC601: 491 bitmask = HID0_601_BITMASK; 492 break; 493 case MPC7450: 494 case MPC7455: 495 case MPC7457: 496 bitmask = HID0_7450_BITMASK; 497 break; 498 case IBM970: 499 case IBM970FX: 500 bitmask = 0; 501 break; 502 default: 503 bitmask = HID0_BITMASK; 504 break; 505 } 506 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 507 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, powersave); 508 509 ci->ci_khz = 0; 510 511 /* 512 * Display speed and cache configuration. 513 */ 514 switch (vers) { 515 case MPC604: 516 case MPC604e: 517 case MPC604ev: 518 case MPC750: 519 case IBM750FX: 520 case MPC7400: 521 case MPC7410: 522 case MPC7447A: 523 case MPC7448: 524 case MPC7450: 525 case MPC7455: 526 case MPC7457: 527 aprint_normal("%s: ", self->dv_xname); 528 cpu_probe_speed(ci); 529 aprint_normal("%u.%02u MHz", 530 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 531 532 if (vers == IBM750FX || vers == MPC750 || 533 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 534 if (MPC745X_P(vers)) { 535 cpu_config_l3cr(vers); 536 } else { 537 cpu_config_l2cr(pvr); 538 } 539 } 540 aprint_normal("\n"); 541 break; 542 } 543 544 #if NSYSMON_ENVSYS > 0 545 /* 546 * Attach MPC750 temperature sensor to the envsys subsystem. 547 * XXX the 74xx series also has this sensor, but it is not 548 * XXX supported by Motorola and may return values that are off by 549 * XXX 35-55 degrees C. 550 */ 551 if (vers == MPC750 || vers == IBM750FX) 552 cpu_tau_setup(ci); 553 #endif 554 555 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 556 NULL, self->dv_xname, "clock"); 557 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 558 NULL, self->dv_xname, "soft clock"); 559 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 560 NULL, self->dv_xname, "soft net"); 561 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 562 NULL, self->dv_xname, "soft serial"); 563 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 564 NULL, self->dv_xname, "traps"); 565 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 566 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 567 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 568 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 569 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 570 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 571 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 572 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 573 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 574 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 575 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 576 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 577 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 578 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 579 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 580 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 581 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 582 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 583 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 584 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 585 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 586 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 587 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 588 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 589 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 590 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 591 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 592 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 593 #ifdef ALTIVEC 594 if (cpu_altivec) { 595 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 596 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 597 } 598 #endif 599 } 600 601 void 602 cpu_identify(char *str, size_t len) 603 { 604 u_int pvr, major, minor; 605 uint16_t vers, rev, revfmt; 606 const struct cputab *cp; 607 const char *name; 608 size_t n; 609 610 pvr = mfpvr(); 611 vers = pvr >> 16; 612 rev = pvr; 613 614 switch (vers) { 615 case MPC7410: 616 minor = (pvr >> 0) & 0xff; 617 major = minor <= 4 ? 1 : 2; 618 break; 619 default: 620 major = (pvr >> 8) & 0xf; 621 minor = (pvr >> 0) & 0xf; 622 } 623 624 for (cp = models; cp->name[0] != '\0'; cp++) { 625 if (cp->version == vers) 626 break; 627 } 628 629 if (str == NULL) { 630 str = cpu_model; 631 len = sizeof(cpu_model); 632 cpu = vers; 633 } 634 635 revfmt = cp->revfmt; 636 name = cp->name; 637 if (rev == MPC750 && pvr == 15) { 638 name = "755"; 639 revfmt = REVFMT_HEX; 640 } 641 642 if (cp->name[0] != '\0') { 643 n = snprintf(str, len, "%s (Revision ", cp->name); 644 } else { 645 n = snprintf(str, len, "Version %#x (Revision ", vers); 646 } 647 if (len > n) { 648 switch (revfmt) { 649 case REVFMT_MAJMIN: 650 snprintf(str + n, len - n, "%u.%u)", major, minor); 651 break; 652 case REVFMT_HEX: 653 snprintf(str + n, len - n, "0x%04x)", rev); 654 break; 655 case REVFMT_DEC: 656 snprintf(str + n, len - n, "%u)", rev); 657 break; 658 } 659 } 660 } 661 662 #ifdef L2CR_CONFIG 663 u_int l2cr_config = L2CR_CONFIG; 664 #else 665 u_int l2cr_config = 0; 666 #endif 667 668 #ifdef L3CR_CONFIG 669 u_int l3cr_config = L3CR_CONFIG; 670 #else 671 u_int l3cr_config = 0; 672 #endif 673 674 void 675 cpu_enable_l2cr(register_t l2cr) 676 { 677 register_t msr, x; 678 679 /* Disable interrupts and set the cache config bits. */ 680 msr = mfmsr(); 681 mtmsr(msr & ~PSL_EE); 682 #ifdef ALTIVEC 683 if (cpu_altivec) 684 __asm volatile("dssall"); 685 #endif 686 __asm volatile("sync"); 687 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 688 __asm volatile("sync"); 689 690 /* Wait for L2 clock to be stable (640 L2 clocks). */ 691 delay(100); 692 693 /* Invalidate all L2 contents. */ 694 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 695 do { 696 x = mfspr(SPR_L2CR); 697 } while (x & L2CR_L2IP); 698 699 /* Enable L2 cache. */ 700 l2cr |= L2CR_L2E; 701 mtspr(SPR_L2CR, l2cr); 702 mtmsr(msr); 703 } 704 705 void 706 cpu_enable_l3cr(register_t l3cr) 707 { 708 register_t x; 709 710 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 711 712 /* 713 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 714 * L3CLKEN. (also mask off reserved bits in case they were included 715 * in L3CR_CONFIG) 716 */ 717 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 718 mtspr(SPR_L3CR, l3cr); 719 720 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 721 l3cr |= 0x04000000; 722 mtspr(SPR_L3CR, l3cr); 723 724 /* 3: Set L3CLKEN to 1*/ 725 l3cr |= L3CR_L3CLKEN; 726 mtspr(SPR_L3CR, l3cr); 727 728 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 729 __asm volatile("dssall;sync"); 730 /* L3 cache is already disabled, no need to clear L3E */ 731 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 732 do { 733 x = mfspr(SPR_L3CR); 734 } while (x & L3CR_L3I); 735 736 /* 6: Clear L3CLKEN to 0 */ 737 l3cr &= ~L3CR_L3CLKEN; 738 mtspr(SPR_L3CR, l3cr); 739 740 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 741 __asm volatile("sync"); 742 delay(100); 743 744 /* 8: Set L3E and L3CLKEN */ 745 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 746 mtspr(SPR_L3CR, l3cr); 747 748 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 749 __asm volatile("sync"); 750 delay(100); 751 } 752 753 void 754 cpu_config_l2cr(int pvr) 755 { 756 register_t l2cr; 757 758 l2cr = mfspr(SPR_L2CR); 759 760 /* 761 * For MP systems, the firmware may only configure the L2 cache 762 * on the first CPU. In this case, assume that the other CPUs 763 * should use the same value for L2CR. 764 */ 765 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 766 l2cr_config = l2cr; 767 } 768 769 /* 770 * Configure L2 cache if not enabled. 771 */ 772 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 773 cpu_enable_l2cr(l2cr_config); 774 l2cr = mfspr(SPR_L2CR); 775 } 776 777 if ((l2cr & L2CR_L2E) == 0) { 778 aprint_normal(" L2 cache present but not enabled "); 779 return; 780 } 781 782 aprint_normal(","); 783 if ((pvr >> 16) == IBM750FX || 784 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 785 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 786 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 787 } else { 788 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 789 } 790 } 791 792 void 793 cpu_config_l3cr(int vers) 794 { 795 register_t l2cr; 796 register_t l3cr; 797 798 l2cr = mfspr(SPR_L2CR); 799 800 /* 801 * For MP systems, the firmware may only configure the L2 cache 802 * on the first CPU. In this case, assume that the other CPUs 803 * should use the same value for L2CR. 804 */ 805 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 806 l2cr_config = l2cr; 807 } 808 809 /* 810 * Configure L2 cache if not enabled. 811 */ 812 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 813 cpu_enable_l2cr(l2cr_config); 814 l2cr = mfspr(SPR_L2CR); 815 } 816 817 aprint_normal(","); 818 switch (vers) { 819 case MPC7447A: 820 case MPC7457: 821 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 822 return; 823 case MPC7448: 824 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 825 return; 826 default: 827 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 828 break; 829 } 830 831 l3cr = mfspr(SPR_L3CR); 832 833 /* 834 * For MP systems, the firmware may only configure the L3 cache 835 * on the first CPU. In this case, assume that the other CPUs 836 * should use the same value for L3CR. 837 */ 838 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 839 l3cr_config = l3cr; 840 } 841 842 /* 843 * Configure L3 cache if not enabled. 844 */ 845 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 846 cpu_enable_l3cr(l3cr_config); 847 l3cr = mfspr(SPR_L3CR); 848 } 849 850 if (l3cr & L3CR_L3E) { 851 aprint_normal(","); 852 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 853 } 854 } 855 856 void 857 cpu_probe_speed(struct cpu_info *ci) 858 { 859 uint64_t cps; 860 861 mtspr(SPR_MMCR0, MMCR0_FC); 862 mtspr(SPR_PMC1, 0); 863 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 864 delay(100000); 865 cps = (mfspr(SPR_PMC1) * 10) + 4999; 866 867 mtspr(SPR_MMCR0, MMCR0_FC); 868 869 ci->ci_khz = cps / 1000; 870 } 871 872 #if NSYSMON_ENVSYS > 0 873 const struct envsys_range cpu_tau_ranges[] = { 874 { 0, 0, ENVSYS_STEMP} 875 }; 876 877 struct envsys_basic_info cpu_tau_info[] = { 878 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 879 }; 880 881 void 882 cpu_tau_setup(struct cpu_info *ci) 883 { 884 struct { 885 struct sysmon_envsys sme; 886 struct envsys_tre_data tau_info; 887 } *datap; 888 int error; 889 890 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 891 892 ci->ci_sysmon_cookie = &datap->sme; 893 datap->sme.sme_nsensors = 1; 894 datap->sme.sme_envsys_version = 1000; 895 datap->sme.sme_ranges = cpu_tau_ranges; 896 datap->sme.sme_sensor_info = cpu_tau_info; 897 datap->sme.sme_sensor_data = &datap->tau_info; 898 899 datap->sme.sme_sensor_data->sensor = 0; 900 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 901 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 902 datap->sme.sme_cookie = ci; 903 datap->sme.sme_gtredata = cpu_tau_gtredata; 904 datap->sme.sme_streinfo = cpu_tau_streinfo; 905 datap->sme.sme_flags = 0; 906 907 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 908 aprint_error("%s: unable to register with sysmon (%d)\n", 909 ci->ci_dev->dv_xname, error); 910 } 911 912 913 /* Find the temperature of the CPU. */ 914 int 915 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 916 { 917 int i, threshold, count; 918 919 if (tred->sensor != 0) { 920 tred->validflags = 0; 921 return 0; 922 } 923 924 threshold = 64; /* Half of the 7-bit sensor range */ 925 mtspr(SPR_THRM1, 0); 926 mtspr(SPR_THRM2, 0); 927 /* XXX This counter is supposed to be "at least 20 microseonds, in 928 * XXX units of clock cycles". Since we don't have convenient 929 * XXX access to the CPU speed, set it to a conservative value, 930 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 931 * XXX the fastest G3 processor is 700MHz) . The cost is that 932 * XXX measuring the temperature takes a bit longer. 933 */ 934 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 935 936 /* Successive-approximation code adapted from Motorola 937 * application note AN1800/D, "Programming the Thermal Assist 938 * Unit in the MPC750 Microprocessor". 939 */ 940 for (i = 4; i >= 0 ; i--) { 941 mtspr(SPR_THRM1, 942 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 943 count = 0; 944 while ((count < 100) && 945 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 946 count++; 947 delay(1); 948 } 949 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 950 /* The interrupt bit was set, meaning the 951 * temperature was above the threshold 952 */ 953 threshold += 2 << i; 954 } else { 955 /* Temperature was below the threshold */ 956 threshold -= 2 << i; 957 } 958 } 959 threshold += 2; 960 961 /* Convert the temperature in degrees C to microkelvin */ 962 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 963 964 *tred = *sme->sme_sensor_data; 965 966 return 0; 967 } 968 969 int 970 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 971 { 972 973 /* There is nothing to set here. */ 974 return (EINVAL); 975 } 976 #endif /* NSYSMON_ENVSYS > 0 */ 977
Indexes created Wed Sep 24 15:09:51 GMT 2025