cpu_subr.c revision 1.30
1 /* $NetBSD: cpu_subr.c,v 1.30 2007/06/02 02:41:41 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.30 2007/06/02 02:41:41 nisimura Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_probe_speed(struct cpu_info *); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0, 0, NULL } 87 }; 88 89 static const struct fmttab cpu_7448_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 1MB L2 cache" }, 95 { 0, 0, NULL } 96 }; 97 98 static const struct fmttab cpu_7457_l2cr_formats[] = { 99 { L2CR_L2E, 0, " disabled" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 103 { L2CR_L2E, ~0, " 512KB L2 cache" }, 104 { 0, 0, NULL } 105 }; 106 107 static const struct fmttab cpu_7450_l3cr_formats[] = { 108 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 109 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 110 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 111 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 112 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 113 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 114 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 115 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 116 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 117 { L3CR_L3SIZ, ~0, " L3 cache" }, 118 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 119 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 120 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 121 { L3CR_L3CLK, ~0, " at" }, 122 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 123 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 124 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 125 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 126 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 127 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 128 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 129 { L3CR_L3CLK, ~0, " ratio" }, 130 { 0, 0, NULL }, 131 }; 132 133 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 134 { L2CR_L2E, 0, " disabled" }, 135 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 136 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 137 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 138 { 0, ~0, " 512KB" }, 139 { L2CR_L2WT, L2CR_L2WT, " WT" }, 140 { L2CR_L2WT, 0, " WB" }, 141 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 142 { 0, ~0, " L2 cache" }, 143 { 0, 0, NULL } 144 }; 145 146 static const struct fmttab cpu_l2cr_formats[] = { 147 { L2CR_L2E, 0, " disabled" }, 148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 151 { L2CR_L2PE, L2CR_L2PE, " parity" }, 152 { L2CR_L2PE, 0, " no-parity" }, 153 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 154 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 155 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 156 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 157 { L2CR_L2WT, L2CR_L2WT, " WT" }, 158 { L2CR_L2WT, 0, " WB" }, 159 { L2CR_L2E, ~0, " L2 cache" }, 160 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 161 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 162 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 163 { L2CR_L2CLK, ~0, " at" }, 164 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 165 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 166 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 167 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 168 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 169 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 170 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 171 { L2CR_L2CLK, ~0, " ratio" }, 172 { 0, 0, NULL } 173 }; 174 175 static void cpu_fmttab_print(const struct fmttab *, register_t); 176 177 struct cputab { 178 const char name[8]; 179 uint16_t version; 180 uint16_t revfmt; 181 }; 182 #define REVFMT_MAJMIN 1 /* %u.%u */ 183 #define REVFMT_HEX 2 /* 0x%04x */ 184 #define REVFMT_DEC 3 /* %u */ 185 static const struct cputab models[] = { 186 { "601", MPC601, REVFMT_DEC }, 187 { "602", MPC602, REVFMT_DEC }, 188 { "603", MPC603, REVFMT_MAJMIN }, 189 { "603e", MPC603e, REVFMT_MAJMIN }, 190 { "603ev", MPC603ev, REVFMT_MAJMIN }, 191 { "604", MPC604, REVFMT_MAJMIN }, 192 { "604e", MPC604e, REVFMT_MAJMIN }, 193 { "604ev", MPC604ev, REVFMT_MAJMIN }, 194 { "620", MPC620, REVFMT_HEX }, 195 { "750", MPC750, REVFMT_MAJMIN }, 196 { "750FX", IBM750FX, REVFMT_MAJMIN }, 197 { "7400", MPC7400, REVFMT_MAJMIN }, 198 { "7410", MPC7410, REVFMT_MAJMIN }, 199 { "7450", MPC7450, REVFMT_MAJMIN }, 200 { "7455", MPC7455, REVFMT_MAJMIN }, 201 { "7457", MPC7457, REVFMT_MAJMIN }, 202 { "7447A", MPC7447A, REVFMT_MAJMIN }, 203 { "7448", MPC7448, REVFMT_MAJMIN }, 204 { "8240", MPC8240, REVFMT_MAJMIN }, 205 { "8245", MPC8245, REVFMT_MAJMIN }, 206 { "970", IBM970, REVFMT_MAJMIN }, 207 { "970FX", IBM970FX, REVFMT_MAJMIN }, 208 { "", 0, REVFMT_HEX } 209 }; 210 211 212 #ifdef MULTIPROCESSOR 213 struct cpu_info cpu_info[CPU_MAXNUM]; 214 #else 215 struct cpu_info cpu_info[1]; 216 #endif 217 218 int cpu_altivec; 219 int cpu_psluserset, cpu_pslusermod; 220 char cpu_model[80]; 221 222 void 223 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 224 { 225 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 226 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 227 (data & fmt->fmt_mask) == fmt->fmt_value) 228 aprint_normal("%s", fmt->fmt_string); 229 } 230 } 231 232 void 233 cpu_idlespin(void) 234 { 235 register_t msr; 236 237 if (powersave <= 0) 238 return; 239 240 __asm volatile( 241 "sync;" 242 "mfmsr %0;" 243 "oris %0,%0,%1@h;" /* enter power saving mode */ 244 "mtmsr %0;" 245 "isync;" 246 : "=r"(msr) 247 : "J"(PSL_POW)); 248 } 249 250 void 251 cpu_probe_cache(void) 252 { 253 u_int assoc, pvr, vers; 254 255 pvr = mfpvr(); 256 vers = pvr >> 16; 257 258 259 /* Presently common across almost all implementations. */ 260 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 261 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 262 263 264 switch (vers) { 265 #define K *1024 266 case IBM750FX: 267 case MPC601: 268 case MPC750: 269 case MPC7447A: 270 case MPC7448: 271 case MPC7450: 272 case MPC7455: 273 case MPC7457: 274 curcpu()->ci_ci.dcache_size = 32 K; 275 curcpu()->ci_ci.icache_size = 32 K; 276 assoc = 8; 277 break; 278 case MPC603: 279 curcpu()->ci_ci.dcache_size = 8 K; 280 curcpu()->ci_ci.icache_size = 8 K; 281 assoc = 2; 282 break; 283 case MPC603e: 284 case MPC603ev: 285 case MPC604: 286 case MPC8240: 287 case MPC8245: 288 curcpu()->ci_ci.dcache_size = 16 K; 289 curcpu()->ci_ci.icache_size = 16 K; 290 assoc = 4; 291 break; 292 case MPC604e: 293 case MPC604ev: 294 curcpu()->ci_ci.dcache_size = 32 K; 295 curcpu()->ci_ci.icache_size = 32 K; 296 assoc = 4; 297 break; 298 case IBM970: 299 case IBM970FX: 300 curcpu()->ci_ci.dcache_size = 32 K; 301 curcpu()->ci_ci.icache_size = 64 K; 302 curcpu()->ci_ci.dcache_line_size = 128; 303 curcpu()->ci_ci.icache_line_size = 128; 304 assoc = 2; 305 break; 306 307 default: 308 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 309 curcpu()->ci_ci.icache_size = PAGE_SIZE; 310 assoc = 1; 311 #undef K 312 } 313 314 /* 315 * Possibly recolor. 316 */ 317 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 318 } 319 320 struct cpu_info * 321 cpu_attach_common(struct device *self, int id) 322 { 323 struct cpu_info *ci; 324 u_int pvr, vers; 325 326 ci = &cpu_info[id]; 327 #ifndef MULTIPROCESSOR 328 /* 329 * If this isn't the primary CPU, print an error message 330 * and just bail out. 331 */ 332 if (id != 0) { 333 aprint_normal(": ID %d\n", id); 334 aprint_normal("%s: processor off-line; multiprocessor support " 335 "not present in kernel\n", self->dv_xname); 336 return (NULL); 337 } 338 #endif 339 340 ci->ci_cpuid = id; 341 ci->ci_intrdepth = -1; 342 ci->ci_dev = self; 343 ci->ci_idlespin = cpu_idlespin; 344 345 pvr = mfpvr(); 346 vers = (pvr >> 16) & 0xffff; 347 348 switch (id) { 349 case 0: 350 /* load my cpu_number to PIR */ 351 switch (vers) { 352 case MPC601: 353 case MPC604: 354 case MPC604e: 355 case MPC604ev: 356 case MPC7400: 357 case MPC7410: 358 case MPC7447A: 359 case MPC7448: 360 case MPC7450: 361 case MPC7455: 362 case MPC7457: 363 mtspr(SPR_PIR, id); 364 } 365 cpu_setup(self, ci); 366 break; 367 default: 368 if (id >= CPU_MAXNUM) { 369 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 370 panic("cpuattach"); 371 } 372 #ifndef MULTIPROCESSOR 373 aprint_normal(" not configured\n"); 374 return NULL; 375 #else 376 mi_cpu_attach(ci); 377 break; 378 #endif 379 } 380 return (ci); 381 } 382 383 void 384 cpu_setup(self, ci) 385 struct device *self; 386 struct cpu_info *ci; 387 { 388 u_int hid0, pvr, vers; 389 const char *bitmask; 390 char hidbuf[128]; 391 char model[80]; 392 393 pvr = mfpvr(); 394 vers = (pvr >> 16) & 0xffff; 395 396 cpu_identify(model, sizeof(model)); 397 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 398 cpu_number() == 0 ? " (primary)" : ""); 399 400 #if defined (PPC_OEA) || defined (PPC_OEA64) 401 hid0 = mfspr(SPR_HID0); 402 #elif defined (PPC_OEA64_BRIDGE) 403 hid0 = mfspr(SPR_HID0); 404 #endif 405 406 cpu_probe_cache(); 407 408 /* 409 * Configure power-saving mode. 410 */ 411 switch (vers) { 412 case MPC604: 413 case MPC604e: 414 case MPC604ev: 415 /* 416 * Do not have HID0 support settings, but can support 417 * MSR[POW] off 418 */ 419 powersave = 1; 420 break; 421 422 case MPC603: 423 case MPC603e: 424 case MPC603ev: 425 case MPC750: 426 case IBM750FX: 427 case MPC7400: 428 case MPC7410: 429 case MPC8240: 430 case MPC8245: 431 /* Select DOZE mode. */ 432 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 433 hid0 |= HID0_DOZE | HID0_DPM; 434 powersave = 1; 435 break; 436 437 case MPC7447A: 438 case MPC7448: 439 case MPC7457: 440 case MPC7455: 441 case MPC7450: 442 /* Enable the 7450 branch caches */ 443 hid0 |= HID0_SGE | HID0_BTIC; 444 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 445 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 446 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 447 hid0 &= ~HID0_BTIC; 448 /* Select NAP mode. */ 449 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 450 hid0 |= HID0_NAP | HID0_DPM /* | HID0_XBSEN */; 451 powersave = 1; 452 break; 453 454 case IBM970: 455 case IBM970FX: 456 default: 457 /* No power-saving mode is available. */ ; 458 } 459 460 #ifdef NAPMODE 461 switch (vers) { 462 case IBM750FX: 463 case MPC750: 464 case MPC7400: 465 /* Select NAP mode. */ 466 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 467 hid0 |= HID0_NAP; 468 break; 469 } 470 #endif 471 472 switch (vers) { 473 case IBM750FX: 474 case MPC750: 475 hid0 &= ~HID0_DBP; /* XXX correct? */ 476 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 477 break; 478 479 case MPC7400: 480 case MPC7410: 481 hid0 &= ~HID0_SPD; 482 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 483 hid0 |= HID0_EIEC; 484 break; 485 } 486 487 #if defined (PPC_OEA) 488 mtspr(SPR_HID0, hid0); 489 __asm volatile("sync;isync"); 490 #endif 491 492 switch (vers) { 493 case MPC601: 494 bitmask = HID0_601_BITMASK; 495 break; 496 case MPC7450: 497 case MPC7455: 498 case MPC7457: 499 bitmask = HID0_7450_BITMASK; 500 break; 501 case IBM970: 502 case IBM970FX: 503 bitmask = 0; 504 break; 505 default: 506 bitmask = HID0_BITMASK; 507 break; 508 } 509 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 510 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, powersave); 511 512 ci->ci_khz = 0; 513 514 /* 515 * Display speed and cache configuration. 516 */ 517 switch (vers) { 518 case MPC604: 519 case MPC604e: 520 case MPC604ev: 521 case MPC750: 522 case IBM750FX: 523 case MPC7400: 524 case MPC7410: 525 case MPC7447A: 526 case MPC7448: 527 case MPC7450: 528 case MPC7455: 529 case MPC7457: 530 aprint_normal("%s: ", self->dv_xname); 531 cpu_probe_speed(ci); 532 aprint_normal("%u.%02u MHz", 533 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 534 535 if (vers == IBM750FX || vers == MPC750 || 536 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 537 if (MPC745X_P(vers)) { 538 cpu_config_l3cr(vers); 539 } else { 540 cpu_config_l2cr(pvr); 541 } 542 } 543 aprint_normal("\n"); 544 break; 545 } 546 547 #if NSYSMON_ENVSYS > 0 548 /* 549 * Attach MPC750 temperature sensor to the envsys subsystem. 550 * XXX the 74xx series also has this sensor, but it is not 551 * XXX supported by Motorola and may return values that are off by 552 * XXX 35-55 degrees C. 553 */ 554 if (vers == MPC750 || vers == IBM750FX) 555 cpu_tau_setup(ci); 556 #endif 557 558 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 559 NULL, self->dv_xname, "clock"); 560 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 561 NULL, self->dv_xname, "soft clock"); 562 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 563 NULL, self->dv_xname, "soft net"); 564 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 565 NULL, self->dv_xname, "soft serial"); 566 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 567 NULL, self->dv_xname, "traps"); 568 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 569 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 570 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 571 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 572 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 573 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 574 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 575 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 576 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 577 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 578 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 579 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 580 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 581 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 582 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 583 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 584 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 585 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 586 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 587 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 588 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 589 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 590 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 591 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 592 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 593 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 594 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 595 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 596 #ifdef ALTIVEC 597 if (cpu_altivec) { 598 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 599 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 600 } 601 #endif 602 } 603 604 void 605 cpu_identify(char *str, size_t len) 606 { 607 u_int pvr, major, minor; 608 uint16_t vers, rev, revfmt; 609 const struct cputab *cp; 610 const char *name; 611 size_t n; 612 613 pvr = mfpvr(); 614 vers = pvr >> 16; 615 rev = pvr; 616 617 switch (vers) { 618 case MPC7410: 619 minor = (pvr >> 0) & 0xff; 620 major = minor <= 4 ? 1 : 2; 621 break; 622 default: 623 major = (pvr >> 8) & 0xf; 624 minor = (pvr >> 0) & 0xf; 625 } 626 627 for (cp = models; cp->name[0] != '\0'; cp++) { 628 if (cp->version == vers) 629 break; 630 } 631 632 if (str == NULL) { 633 str = cpu_model; 634 len = sizeof(cpu_model); 635 cpu = vers; 636 } 637 638 revfmt = cp->revfmt; 639 name = cp->name; 640 if (rev == MPC750 && pvr == 15) { 641 name = "755"; 642 revfmt = REVFMT_HEX; 643 } 644 645 if (cp->name[0] != '\0') { 646 n = snprintf(str, len, "%s (Revision ", cp->name); 647 } else { 648 n = snprintf(str, len, "Version %#x (Revision ", vers); 649 } 650 if (len > n) { 651 switch (revfmt) { 652 case REVFMT_MAJMIN: 653 snprintf(str + n, len - n, "%u.%u)", major, minor); 654 break; 655 case REVFMT_HEX: 656 snprintf(str + n, len - n, "0x%04x)", rev); 657 break; 658 case REVFMT_DEC: 659 snprintf(str + n, len - n, "%u)", rev); 660 break; 661 } 662 } 663 } 664 665 #ifdef L2CR_CONFIG 666 u_int l2cr_config = L2CR_CONFIG; 667 #else 668 u_int l2cr_config = 0; 669 #endif 670 671 #ifdef L3CR_CONFIG 672 u_int l3cr_config = L3CR_CONFIG; 673 #else 674 u_int l3cr_config = 0; 675 #endif 676 677 void 678 cpu_enable_l2cr(register_t l2cr) 679 { 680 register_t msr, x; 681 682 /* Disable interrupts and set the cache config bits. */ 683 msr = mfmsr(); 684 mtmsr(msr & ~PSL_EE); 685 #ifdef ALTIVEC 686 if (cpu_altivec) 687 __asm volatile("dssall"); 688 #endif 689 __asm volatile("sync"); 690 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 691 __asm volatile("sync"); 692 693 /* Wait for L2 clock to be stable (640 L2 clocks). */ 694 delay(100); 695 696 /* Invalidate all L2 contents. */ 697 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 698 do { 699 x = mfspr(SPR_L2CR); 700 } while (x & L2CR_L2IP); 701 702 /* Enable L2 cache. */ 703 l2cr |= L2CR_L2E; 704 mtspr(SPR_L2CR, l2cr); 705 mtmsr(msr); 706 } 707 708 void 709 cpu_enable_l3cr(register_t l3cr) 710 { 711 register_t x; 712 713 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 714 715 /* 716 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 717 * L3CLKEN. (also mask off reserved bits in case they were included 718 * in L3CR_CONFIG) 719 */ 720 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 721 mtspr(SPR_L3CR, l3cr); 722 723 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 724 l3cr |= 0x04000000; 725 mtspr(SPR_L3CR, l3cr); 726 727 /* 3: Set L3CLKEN to 1*/ 728 l3cr |= L3CR_L3CLKEN; 729 mtspr(SPR_L3CR, l3cr); 730 731 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 732 __asm volatile("dssall;sync"); 733 /* L3 cache is already disabled, no need to clear L3E */ 734 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 735 do { 736 x = mfspr(SPR_L3CR); 737 } while (x & L3CR_L3I); 738 739 /* 6: Clear L3CLKEN to 0 */ 740 l3cr &= ~L3CR_L3CLKEN; 741 mtspr(SPR_L3CR, l3cr); 742 743 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 744 __asm volatile("sync"); 745 delay(100); 746 747 /* 8: Set L3E and L3CLKEN */ 748 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 749 mtspr(SPR_L3CR, l3cr); 750 751 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 752 __asm volatile("sync"); 753 delay(100); 754 } 755 756 void 757 cpu_config_l2cr(int pvr) 758 { 759 register_t l2cr; 760 761 l2cr = mfspr(SPR_L2CR); 762 763 /* 764 * For MP systems, the firmware may only configure the L2 cache 765 * on the first CPU. In this case, assume that the other CPUs 766 * should use the same value for L2CR. 767 */ 768 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 769 l2cr_config = l2cr; 770 } 771 772 /* 773 * Configure L2 cache if not enabled. 774 */ 775 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 776 cpu_enable_l2cr(l2cr_config); 777 l2cr = mfspr(SPR_L2CR); 778 } 779 780 if ((l2cr & L2CR_L2E) == 0) { 781 aprint_normal(" L2 cache present but not enabled "); 782 return; 783 } 784 785 aprint_normal(","); 786 if ((pvr >> 16) == IBM750FX || 787 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 788 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 789 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 790 } else { 791 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 792 } 793 } 794 795 void 796 cpu_config_l3cr(int vers) 797 { 798 register_t l2cr; 799 register_t l3cr; 800 801 l2cr = mfspr(SPR_L2CR); 802 803 /* 804 * For MP systems, the firmware may only configure the L2 cache 805 * on the first CPU. In this case, assume that the other CPUs 806 * should use the same value for L2CR. 807 */ 808 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 809 l2cr_config = l2cr; 810 } 811 812 /* 813 * Configure L2 cache if not enabled. 814 */ 815 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 816 cpu_enable_l2cr(l2cr_config); 817 l2cr = mfspr(SPR_L2CR); 818 } 819 820 aprint_normal(","); 821 switch (vers) { 822 case MPC7447A: 823 case MPC7457: 824 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 825 return; 826 case MPC7448: 827 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 828 return; 829 default: 830 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 831 break; 832 } 833 834 l3cr = mfspr(SPR_L3CR); 835 836 /* 837 * For MP systems, the firmware may only configure the L3 cache 838 * on the first CPU. In this case, assume that the other CPUs 839 * should use the same value for L3CR. 840 */ 841 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 842 l3cr_config = l3cr; 843 } 844 845 /* 846 * Configure L3 cache if not enabled. 847 */ 848 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 849 cpu_enable_l3cr(l3cr_config); 850 l3cr = mfspr(SPR_L3CR); 851 } 852 853 if (l3cr & L3CR_L3E) { 854 aprint_normal(","); 855 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 856 } 857 } 858 859 void 860 cpu_probe_speed(struct cpu_info *ci) 861 { 862 uint64_t cps; 863 864 mtspr(SPR_MMCR0, MMCR0_FC); 865 mtspr(SPR_PMC1, 0); 866 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 867 delay(100000); 868 cps = (mfspr(SPR_PMC1) * 10) + 4999; 869 870 mtspr(SPR_MMCR0, MMCR0_FC); 871 872 ci->ci_khz = cps / 1000; 873 } 874 875 #if NSYSMON_ENVSYS > 0 876 const struct envsys_range cpu_tau_ranges[] = { 877 { 0, 0, ENVSYS_STEMP} 878 }; 879 880 struct envsys_basic_info cpu_tau_info[] = { 881 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 882 }; 883 884 void 885 cpu_tau_setup(struct cpu_info *ci) 886 { 887 struct { 888 struct sysmon_envsys sme; 889 struct envsys_tre_data tau_info; 890 } *datap; 891 int error; 892 893 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 894 895 ci->ci_sysmon_cookie = &datap->sme; 896 datap->sme.sme_nsensors = 1; 897 datap->sme.sme_envsys_version = 1000; 898 datap->sme.sme_ranges = cpu_tau_ranges; 899 datap->sme.sme_sensor_info = cpu_tau_info; 900 datap->sme.sme_sensor_data = &datap->tau_info; 901 902 datap->sme.sme_sensor_data->sensor = 0; 903 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 904 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 905 datap->sme.sme_cookie = ci; 906 datap->sme.sme_gtredata = cpu_tau_gtredata; 907 datap->sme.sme_streinfo = cpu_tau_streinfo; 908 datap->sme.sme_flags = 0; 909 910 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 911 aprint_error("%s: unable to register with sysmon (%d)\n", 912 ci->ci_dev->dv_xname, error); 913 } 914 915 916 /* Find the temperature of the CPU. */ 917 int 918 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 919 { 920 int i, threshold, count; 921 922 if (tred->sensor != 0) { 923 tred->validflags = 0; 924 return 0; 925 } 926 927 threshold = 64; /* Half of the 7-bit sensor range */ 928 mtspr(SPR_THRM1, 0); 929 mtspr(SPR_THRM2, 0); 930 /* XXX This counter is supposed to be "at least 20 microseonds, in 931 * XXX units of clock cycles". Since we don't have convenient 932 * XXX access to the CPU speed, set it to a conservative value, 933 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 934 * XXX the fastest G3 processor is 700MHz) . The cost is that 935 * XXX measuring the temperature takes a bit longer. 936 */ 937 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 938 939 /* Successive-approximation code adapted from Motorola 940 * application note AN1800/D, "Programming the Thermal Assist 941 * Unit in the MPC750 Microprocessor". 942 */ 943 for (i = 4; i >= 0 ; i--) { 944 mtspr(SPR_THRM1, 945 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 946 count = 0; 947 while ((count < 100) && 948 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 949 count++; 950 delay(1); 951 } 952 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 953 /* The interrupt bit was set, meaning the 954 * temperature was above the threshold 955 */ 956 threshold += 2 << i; 957 } else { 958 /* Temperature was below the threshold */ 959 threshold -= 2 << i; 960 } 961 } 962 threshold += 2; 963 964 /* Convert the temperature in degrees C to microkelvin */ 965 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 966 967 *tred = *sme->sme_sensor_data; 968 969 return 0; 970 } 971 972 int 973 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 974 { 975 976 /* There is nothing to set here. */ 977 return (EINVAL); 978 } 979 #endif /* NSYSMON_ENVSYS > 0 */ 980
Indexes created Thu Sep 25 16:09:42 GMT 2025